source: asp3_wo_tecs/trunk/arch/arm_m_gcc/stm32f4xx_stm32cube/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h@ 303

Last change on this file since 303 was 303, checked in by ertl-honda, 7 years ago

nucleo_f401re依存部の追加

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1/**
2 ******************************************************************************
3 * @file stm32_hal_legacy.h
4 * @author MCD Application Team
5 * @version V1.4.1
6 * @date 09-October-2015
7 * @brief This file contains aliases definition for the STM32Cube HAL constants
8 * macros and functions maintained for legacy purpose.
9 ******************************************************************************
10 * @attention
11 *
12 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
13 *
14 * Redistribution and use in source and binary forms, with or without modification,
15 * are permitted provided that the following conditions are met:
16 * 1. Redistributions of source code must retain the above copyright notice,
17 * this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright notice,
19 * this list of conditions and the following disclaimer in the documentation
20 * and/or other materials provided with the distribution.
21 * 3. Neither the name of STMicroelectronics nor the names of its contributors
22 * may be used to endorse or promote products derived from this software
23 * without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
28 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
32 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 *
36 ******************************************************************************
37 */
38
39/* Define to prevent recursive inclusion -------------------------------------*/
40#ifndef __STM32_HAL_LEGACY
41#define __STM32_HAL_LEGACY
42
43#ifdef __cplusplus
44 extern "C" {
45#endif
46
47/* Includes ------------------------------------------------------------------*/
48/* Exported types ------------------------------------------------------------*/
49/* Exported constants --------------------------------------------------------*/
50
51/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose
52 * @{
53 */
54#define AES_FLAG_RDERR CRYP_FLAG_RDERR
55#define AES_FLAG_WRERR CRYP_FLAG_WRERR
56#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
57#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
58#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
59
60/**
61 * @}
62 */
63
64/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose
65 * @{
66 */
67#define ADC_RESOLUTION12b ADC_RESOLUTION_12B
68#define ADC_RESOLUTION10b ADC_RESOLUTION_10B
69#define ADC_RESOLUTION8b ADC_RESOLUTION_8B
70#define ADC_RESOLUTION6b ADC_RESOLUTION_6B
71#define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN
72#define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED
73#define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV
74#define EOC_SEQ_CONV ADC_EOC_SEQ_CONV
75#define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV
76#define REGULAR_GROUP ADC_REGULAR_GROUP
77#define INJECTED_GROUP ADC_INJECTED_GROUP
78#define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP
79#define AWD_EVENT ADC_AWD_EVENT
80#define AWD1_EVENT ADC_AWD1_EVENT
81#define AWD2_EVENT ADC_AWD2_EVENT
82#define AWD3_EVENT ADC_AWD3_EVENT
83#define OVR_EVENT ADC_OVR_EVENT
84#define JQOVF_EVENT ADC_JQOVF_EVENT
85#define ALL_CHANNELS ADC_ALL_CHANNELS
86#define REGULAR_CHANNELS ADC_REGULAR_CHANNELS
87#define INJECTED_CHANNELS ADC_INJECTED_CHANNELS
88#define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR
89#define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT
90#define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1
91#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2
92#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4
93#define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6
94#define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8
95#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO
96#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2
97#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO
98#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4
99#define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO
100#define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11
101#define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1
102#define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE
103#define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING
104#define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING
105#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING
106/**
107 * @}
108 */
109
110/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose
111 * @{
112 */
113
114#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG
115
116/**
117 * @}
118 */
119
120/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose
121 * @{
122 */
123
124#define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE
125#define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE
126#define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1
127#define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2
128
129/**
130 * @}
131 */
132
133/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose
134 * @{
135 */
136
137#define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE
138#define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE
139
140/**
141 * @}
142 */
143
144/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose
145 * @{
146 */
147
148#define DAC1_CHANNEL_1 DAC_CHANNEL_1
149#define DAC1_CHANNEL_2 DAC_CHANNEL_2
150#define DAC2_CHANNEL_1 DAC_CHANNEL_1
151#define DAC_WAVE_NONE ((uint32_t)0x00000000)
152#define DAC_WAVE_NOISE ((uint32_t)DAC_CR_WAVE1_0)
153#define DAC_WAVE_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1)
154#define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE
155#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
156#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
157
158/**
159 * @}
160 */
161
162/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose
163 * @{
164 */
165#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2
166#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4
167#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5
168#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4
169#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2
170#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32
171#define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6
172#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7
173#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67
174#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67
175#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32
176#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76
177#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6
178#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7
179#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6
180
181#define IS_HAL_REMAPDMA IS_DMA_REMAP
182#define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE
183#define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE
184
185
186
187/**
188 * @}
189 */
190
191/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose
192 * @{
193 */
194
195#define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE
196#define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD
197#define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD
198#define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD
199#define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS
200#define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES
201#define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES
202#define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE
203#define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE
204#define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE
205#define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE
206#define OBEX_PCROP OPTIONBYTE_PCROP
207#define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG
208#define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE
209#define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE
210#define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE
211#define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD
212#define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD
213#define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE
214#define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD
215#define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD
216#define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE
217#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD
218#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD
219#define PAGESIZE FLASH_PAGE_SIZE
220#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE
221#define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD
222#define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD
223#define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1
224#define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2
225#define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3
226#define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4
227#define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST
228#define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST
229#define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA
230#define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB
231#define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA
232#define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB
233#define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE
234#define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN
235#define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE
236#define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN
237#define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE
238#define FLASH_ERROR_RD HAL_FLASH_ERROR_RD
239#define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG
240#define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS
241#define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP
242#define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV
243#define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR
244#define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG
245#define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION
246#define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA
247#define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE
248#define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE
249#define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS
250#define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS
251#define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST
252#define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR
253#define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO
254#define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION
255#define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS
256#define OB_WDG_SW OB_IWDG_SW
257#define OB_WDG_HW OB_IWDG_HW
258#define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET
259#define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET
260#define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET
261#define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET
262#define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR
263#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0
264#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1
265#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2
266/**
267 * @}
268 */
269
270/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose
271 * @{
272 */
273
274#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9
275#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10
276#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6
277#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7
278#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8
279#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9
280#define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1
281#define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2
282#define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3
283/**
284 * @}
285 */
286
287
288/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
289 * @{
290 */
291#if defined(STM32L4) || defined(STM32F7)
292#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE
293#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE
294#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8
295#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16
296#else
297#define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE
298#define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE
299#define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8
300#define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16
301#endif
302/**
303 * @}
304 */
305
306/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose
307 * @{
308 */
309
310#define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef
311#define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef
312/**
313 * @}
314 */
315
316/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose
317 * @{
318 */
319#define GET_GPIO_SOURCE GPIO_GET_INDEX
320#define GET_GPIO_INDEX GPIO_GET_INDEX
321
322#if defined(STM32F4)
323#define GPIO_AF12_SDMMC GPIO_AF12_SDIO
324#define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO
325#endif
326
327#if defined(STM32F7)
328#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1
329#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
330#endif
331
332#if defined(STM32L4)
333#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1
334#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
335#endif
336
337#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1
338#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
339#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
340
341#if defined(STM32L0) || defined(STM32F4)
342#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
343#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
344#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
345#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
346#endif /* STM32L0 || STM32F4 */
347
348/**
349 * @}
350 */
351
352/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose
353 * @{
354 */
355#define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED
356#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6
357#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6
358#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6
359#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6
360#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7
361#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7
362#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7
363#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7
364/**
365 * @}
366 */
367
368/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose
369 * @{
370 */
371#define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE
372#define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE
373#define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE
374#define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE
375#define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE
376#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE
377#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE
378#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE
379/**
380 * @}
381 */
382
383/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose
384 * @{
385 */
386#define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE
387#define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE
388
389/**
390 * @}
391 */
392
393/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose
394 * @{
395 */
396#define KR_KEY_RELOAD IWDG_KEY_RELOAD
397#define KR_KEY_ENABLE IWDG_KEY_ENABLE
398#define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE
399#define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE
400/**
401 * @}
402 */
403
404/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
405 * @{
406 */
407
408#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION
409#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS
410#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS
411#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS
412
413#define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING
414#define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING
415#define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING
416
417#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION
418#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS
419#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS
420#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS
421
422/* The following 3 definition have also been present in a temporary version of lptim.h */
423/* They need to be renamed also to the right name, just in case */
424#define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS
425#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS
426#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS
427
428/**
429 * @}
430 */
431
432/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose
433 * @{
434 */
435#define NAND_AddressTypedef NAND_AddressTypeDef
436
437#define __ARRAY_ADDRESS ARRAY_ADDRESS
438#define __ADDR_1st_CYCLE ADDR_1ST_CYCLE
439#define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE
440#define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE
441#define __ADDR_4th_CYCLE ADDR_4TH_CYCLE
442/**
443 * @}
444 */
445
446/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose
447 * @{
448 */
449#define NOR_StatusTypedef HAL_NOR_StatusTypeDef
450#define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS
451#define NOR_ONGOING HAL_NOR_STATUS_ONGOING
452#define NOR_ERROR HAL_NOR_STATUS_ERROR
453#define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT
454
455#define __NOR_WRITE NOR_WRITE
456#define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT
457/**
458 * @}
459 */
460
461/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose
462 * @{
463 */
464
465#define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0
466#define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1
467#define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2
468#define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3
469
470#define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0
471#define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1
472#define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2
473#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3
474
475#define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
476#define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
477
478#define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
479#define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
480
481#define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0
482#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1
483
484#define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1
485
486#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO
487#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
488#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
489
490/**
491 * @}
492 */
493
494/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose
495 * @{
496 */
497#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS
498/**
499 * @}
500 */
501
502/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose
503 * @{
504 */
505
506/* Compact Flash-ATA registers description */
507#define CF_DATA ATA_DATA
508#define CF_SECTOR_COUNT ATA_SECTOR_COUNT
509#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER
510#define CF_CYLINDER_LOW ATA_CYLINDER_LOW
511#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH
512#define CF_CARD_HEAD ATA_CARD_HEAD
513#define CF_STATUS_CMD ATA_STATUS_CMD
514#define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE
515#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA
516
517/* Compact Flash-ATA commands */
518#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD
519#define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD
520#define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD
521#define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD
522
523#define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef
524#define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS
525#define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING
526#define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR
527#define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT
528/**
529 * @}
530 */
531
532/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose
533 * @{
534 */
535
536#define FORMAT_BIN RTC_FORMAT_BIN
537#define FORMAT_BCD RTC_FORMAT_BCD
538
539#define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE
540#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
541#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
542#define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
543#define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
544
545#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
546#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
547#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
548#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
549#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
550#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
551#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
552#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
553
554#define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT
555#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1
556#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
557#define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2
558
559#define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE
560#define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1
561#define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1
562
563#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT
564#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
565#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
566
567/**
568 * @}
569 */
570
571
572/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose
573 * @{
574 */
575#define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE
576#define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE
577
578#define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE
579#define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE
580#define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE
581#define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE
582
583#define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE
584#define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE
585
586#define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE
587#define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE
588/**
589 * @}
590 */
591
592
593 /** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose
594 * @{
595 */
596#define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE
597#define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE
598#define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE
599#define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE
600#define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE
601#define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE
602#define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE
603#define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE
604#define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE
605#define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE
606#define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN
607/**
608 * @}
609 */
610
611 /** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose
612 * @{
613 */
614#define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE
615#define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE
616
617#define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE
618#define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE
619
620#define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE
621#define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE
622
623/**
624 * @}
625 */
626
627/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose
628 * @{
629 */
630#define CCER_CCxE_MASK TIM_CCER_CCxE_MASK
631#define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK
632
633#define TIM_DMABase_CR1 TIM_DMABASE_CR1
634#define TIM_DMABase_CR2 TIM_DMABASE_CR2
635#define TIM_DMABase_SMCR TIM_DMABASE_SMCR
636#define TIM_DMABase_DIER TIM_DMABASE_DIER
637#define TIM_DMABase_SR TIM_DMABASE_SR
638#define TIM_DMABase_EGR TIM_DMABASE_EGR
639#define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1
640#define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2
641#define TIM_DMABase_CCER TIM_DMABASE_CCER
642#define TIM_DMABase_CNT TIM_DMABASE_CNT
643#define TIM_DMABase_PSC TIM_DMABASE_PSC
644#define TIM_DMABase_ARR TIM_DMABASE_ARR
645#define TIM_DMABase_RCR TIM_DMABASE_RCR
646#define TIM_DMABase_CCR1 TIM_DMABASE_CCR1
647#define TIM_DMABase_CCR2 TIM_DMABASE_CCR2
648#define TIM_DMABase_CCR3 TIM_DMABASE_CCR3
649#define TIM_DMABase_CCR4 TIM_DMABASE_CCR4
650#define TIM_DMABase_BDTR TIM_DMABASE_BDTR
651#define TIM_DMABase_DCR TIM_DMABASE_DCR
652#define TIM_DMABase_DMAR TIM_DMABASE_DMAR
653#define TIM_DMABase_OR1 TIM_DMABASE_OR1
654#define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3
655#define TIM_DMABase_CCR5 TIM_DMABASE_CCR5
656#define TIM_DMABase_CCR6 TIM_DMABASE_CCR6
657#define TIM_DMABase_OR2 TIM_DMABASE_OR2
658#define TIM_DMABase_OR3 TIM_DMABASE_OR3
659#define TIM_DMABase_OR TIM_DMABASE_OR
660
661#define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE
662#define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1
663#define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2
664#define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3
665#define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4
666#define TIM_EventSource_COM TIM_EVENTSOURCE_COM
667#define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER
668#define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK
669#define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2
670
671#define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER
672#define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS
673#define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS
674#define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS
675#define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS
676#define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS
677#define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS
678#define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS
679#define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS
680#define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS
681#define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS
682#define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS
683#define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS
684#define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS
685#define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS
686#define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS
687#define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS
688#define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS
689
690/**
691 * @}
692 */
693
694/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose
695 * @{
696 */
697#define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING
698#define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING
699/**
700 * @}
701 */
702
703/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose
704 * @{
705 */
706#define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
707#define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
708#define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
709#define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
710
711#define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE
712#define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE
713
714#define __DIV_SAMPLING16 UART_DIV_SAMPLING16
715#define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16
716#define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16
717#define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16
718
719#define __DIV_SAMPLING8 UART_DIV_SAMPLING8
720#define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8
721#define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8
722#define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8
723
724#define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE
725#define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK
726
727/**
728 * @}
729 */
730
731
732/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose
733 * @{
734 */
735
736#define USART_CLOCK_DISABLED USART_CLOCK_DISABLE
737#define USART_CLOCK_ENABLED USART_CLOCK_ENABLE
738
739#define USARTNACK_ENABLED USART_NACK_ENABLE
740#define USARTNACK_DISABLED USART_NACK_DISABLE
741/**
742 * @}
743 */
744
745/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose
746 * @{
747 */
748#define CFR_BASE WWDG_CFR_BASE
749
750/**
751 * @}
752 */
753
754/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose
755 * @{
756 */
757#define CAN_FilterFIFO0 CAN_FILTER_FIFO0
758#define CAN_FilterFIFO1 CAN_FILTER_FIFO1
759#define CAN_IT_RQCP0 CAN_IT_TME
760#define CAN_IT_RQCP1 CAN_IT_TME
761#define CAN_IT_RQCP2 CAN_IT_TME
762#define INAK_TIMEOUT CAN_TIMEOUT_VALUE
763#define SLAK_TIMEOUT CAN_TIMEOUT_VALUE
764#define CAN_TXSTATUS_FAILED ((uint8_t)0x00)
765#define CAN_TXSTATUS_OK ((uint8_t)0x01)
766#define CAN_TXSTATUS_PENDING ((uint8_t)0x02)
767
768/**
769 * @}
770 */
771
772/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose
773 * @{
774 */
775
776#define VLAN_TAG ETH_VLAN_TAG
777#define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD
778#define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD
779#define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD
780#define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK
781#define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK
782#define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK
783#define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK
784
785#define ETH_MMCCR ((uint32_t)0x00000100)
786#define ETH_MMCRIR ((uint32_t)0x00000104)
787#define ETH_MMCTIR ((uint32_t)0x00000108)
788#define ETH_MMCRIMR ((uint32_t)0x0000010C)
789#define ETH_MMCTIMR ((uint32_t)0x00000110)
790#define ETH_MMCTGFSCCR ((uint32_t)0x0000014C)
791#define ETH_MMCTGFMSCCR ((uint32_t)0x00000150)
792#define ETH_MMCTGFCR ((uint32_t)0x00000168)
793#define ETH_MMCRFCECR ((uint32_t)0x00000194)
794#define ETH_MMCRFAECR ((uint32_t)0x00000198)
795#define ETH_MMCRGUFCR ((uint32_t)0x000001C4)
796
797/**
798 * @}
799 */
800
801/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
802 * @{
803 */
804
805/**
806 * @}
807 */
808
809/* Exported functions --------------------------------------------------------*/
810
811/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose
812 * @{
813 */
814#define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback
815/**
816 * @}
817 */
818
819/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose
820 * @{
821 */
822
823#define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish
824#define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish
825#define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish
826#define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish
827
828/*HASH Algorithm Selection*/
829
830#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1
831#define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224
832#define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256
833#define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5
834
835#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH
836#define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC
837
838#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY
839#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY
840/**
841 * @}
842 */
843
844/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose
845 * @{
846 */
847#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode
848#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode
849#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode
850#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode
851#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
852#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
853#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
854#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect
855#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
856#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
857#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
858#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
859/**
860 * @}
861 */
862
863/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose
864 * @{
865 */
866#define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram
867#define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown
868#define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown
869#define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock
870#define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock
871#define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase
872#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program
873
874 /**
875 * @}
876 */
877
878/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose
879 * @{
880 */
881#define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter
882#define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter
883
884#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
885 /**
886 * @}
887 */
888
889/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
890 * @{
891 */
892#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD
893#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg
894#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown
895#define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor
896#define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg
897#define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown
898#define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor
899#define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler
900#define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD
901#define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler
902#define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback
903#define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive
904#define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive
905#define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC
906#define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC
907#define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM
908
909#define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL
910#define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING
911#define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING
912#define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING
913#define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING
914#define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING
915#define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING
916
917#define CR_OFFSET_BB PWR_CR_OFFSET_BB
918#define CSR_OFFSET_BB PWR_CSR_OFFSET_BB
919
920#define DBP_BitNumber DBP_BIT_NUMBER
921#define PVDE_BitNumber PVDE_BIT_NUMBER
922#define PMODE_BitNumber PMODE_BIT_NUMBER
923#define EWUP_BitNumber EWUP_BIT_NUMBER
924#define FPDS_BitNumber FPDS_BIT_NUMBER
925#define ODEN_BitNumber ODEN_BIT_NUMBER
926#define ODSWEN_BitNumber ODSWEN_BIT_NUMBER
927#define MRLVDS_BitNumber MRLVDS_BIT_NUMBER
928#define LPLVDS_BitNumber LPLVDS_BIT_NUMBER
929#define BRE_BitNumber BRE_BIT_NUMBER
930
931#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL
932
933 /**
934 * @}
935 */
936
937/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
938 * @{
939 */
940#define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT
941#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback
942#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback
943/**
944 * @}
945 */
946
947/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose
948 * @{
949 */
950#define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo
951/**
952 * @}
953 */
954
955/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose
956 * @{
957 */
958#define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt
959#define HAL_TIM_DMAError TIM_DMAError
960#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt
961#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
962/**
963 * @}
964 */
965
966/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose
967 * @{
968 */
969#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback
970/**
971 * @}
972 */
973
974/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose
975 * @{
976 */
977#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback
978/**
979 * @}
980 */
981
982
983 /** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose
984 * @{
985 */
986
987/**
988 * @}
989 */
990
991/* Exported macros ------------------------------------------------------------*/
992
993/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose
994 * @{
995 */
996#define AES_IT_CC CRYP_IT_CC
997#define AES_IT_ERR CRYP_IT_ERR
998#define AES_FLAG_CCF CRYP_FLAG_CCF
999/**
1000 * @}
1001 */
1002
1003/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
1004 * @{
1005 */
1006#define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE
1007#define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH
1008#define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH
1009#define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM
1010#define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC
1011#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM
1012#define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC
1013#define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI
1014#define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK
1015#define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG
1016#define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG
1017#define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE
1018#define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE
1019
1020#define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY
1021#define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48
1022#define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS
1023#define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER
1024#define CMP_PD_BitNumber CMP_PD_BIT_NUMBER
1025
1026/**
1027 * @}
1028 */
1029
1030
1031/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose
1032 * @{
1033 */
1034#define __ADC_ENABLE __HAL_ADC_ENABLE
1035#define __ADC_DISABLE __HAL_ADC_DISABLE
1036#define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS
1037#define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS
1038#define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE
1039#define __ADC_IS_ENABLED ADC_IS_ENABLE
1040#define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR
1041#define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED
1042#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED
1043#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR
1044#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED
1045#define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING
1046#define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE
1047
1048#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION
1049#define __HAL_ADC_JSQR_RK ADC_JSQR_RK
1050#define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT
1051#define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR
1052#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION
1053#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE
1054#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS
1055#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS
1056#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM
1057#define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT
1058#define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS
1059#define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN
1060#define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ
1061#define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET
1062#define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET
1063#define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL
1064#define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL
1065#define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET
1066#define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET
1067#define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD
1068
1069#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION
1070#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION
1071#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION
1072#define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER
1073#define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI
1074#define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
1075#define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
1076#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER
1077#define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER
1078#define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE
1079
1080#define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT
1081#define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT
1082#define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL
1083#define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM
1084#define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET
1085#define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE
1086#define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE
1087#define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER
1088
1089#define __HAL_ADC_SQR1 ADC_SQR1
1090#define __HAL_ADC_SMPR1 ADC_SMPR1
1091#define __HAL_ADC_SMPR2 ADC_SMPR2
1092#define __HAL_ADC_SQR3_RK ADC_SQR3_RK
1093#define __HAL_ADC_SQR2_RK ADC_SQR2_RK
1094#define __HAL_ADC_SQR1_RK ADC_SQR1_RK
1095#define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS
1096#define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS
1097#define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV
1098#define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection
1099#define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq
1100#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION
1101#define __HAL_ADC_JSQR ADC_JSQR
1102
1103#define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL
1104#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS
1105#define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF
1106#define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT
1107#define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS
1108#define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN
1109#define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR
1110#define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ
1111
1112/**
1113 * @}
1114 */
1115
1116/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
1117 * @{
1118 */
1119#define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT
1120#define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT
1121#define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT
1122#define IS_DAC_GENERATE_WAVE IS_DAC_WAVE
1123
1124/**
1125 * @}
1126 */
1127
1128/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose
1129 * @{
1130 */
1131#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1
1132#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1
1133#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2
1134#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2
1135#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3
1136#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3
1137#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4
1138#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4
1139#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5
1140#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5
1141#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6
1142#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6
1143#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7
1144#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7
1145#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8
1146#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8
1147
1148#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9
1149#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9
1150#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10
1151#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10
1152#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11
1153#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11
1154#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12
1155#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12
1156#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13
1157#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13
1158#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14
1159#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14
1160#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2
1161#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2
1162
1163
1164#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15
1165#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15
1166#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16
1167#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16
1168#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17
1169#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17
1170#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC
1171#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC
1172#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
1173#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
1174#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
1175#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
1176#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
1177#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
1178#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT
1179#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT
1180#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT
1181#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT
1182#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1
1183#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1
1184#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1
1185#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1
1186#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2
1187#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2
1188
1189/**
1190 * @}
1191 */
1192
1193/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose
1194 * @{
1195 */
1196
1197#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
1198 __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
1199#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
1200 __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
1201#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
1202 __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
1203#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
1204 __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
1205#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
1206 __HAL_COMP_COMP2_EXTI_ENABLE_IT())
1207#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
1208 __HAL_COMP_COMP2_EXTI_DISABLE_IT())
1209#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
1210 __HAL_COMP_COMP2_EXTI_GET_FLAG())
1211#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
1212 __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
1213#define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE
1214
1215/**
1216 * @}
1217 */
1218
1219/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
1220 * @{
1221 */
1222
1223#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \
1224 ((WAVE) == DAC_WAVE_NOISE)|| \
1225 ((WAVE) == DAC_WAVE_TRIANGLE))
1226
1227/**
1228 * @}
1229 */
1230
1231/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose
1232 * @{
1233 */
1234
1235#define IS_WRPAREA IS_OB_WRPAREA
1236#define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM
1237#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM
1238#define IS_TYPEERASE IS_FLASH_TYPEERASE
1239#define IS_NBSECTORS IS_FLASH_NBSECTORS
1240#define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE
1241
1242/**
1243 * @}
1244 */
1245
1246/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose
1247 * @{
1248 */
1249
1250#define __HAL_I2C_RESET_CR2 I2C_RESET_CR2
1251#define __HAL_I2C_GENERATE_START I2C_GENERATE_START
1252#define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE
1253#define __HAL_I2C_RISE_TIME I2C_RISE_TIME
1254#define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD
1255#define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST
1256#define __HAL_I2C_SPEED I2C_SPEED
1257#define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE
1258#define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ
1259#define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS
1260#define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE
1261#define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ
1262#define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB
1263#define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB
1264#define __HAL_I2C_FREQRANGE I2C_FREQRANGE
1265/**
1266 * @}
1267 */
1268
1269/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose
1270 * @{
1271 */
1272
1273#define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE
1274#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT
1275
1276/**
1277 * @}
1278 */
1279
1280/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose
1281 * @{
1282 */
1283
1284#define __IRDA_DISABLE __HAL_IRDA_DISABLE
1285#define __IRDA_ENABLE __HAL_IRDA_ENABLE
1286
1287#define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
1288#define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
1289#define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
1290#define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
1291
1292#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE
1293
1294
1295/**
1296 * @}
1297 */
1298
1299
1300/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose
1301 * @{
1302 */
1303#define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS
1304#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS
1305/**
1306 * @}
1307 */
1308
1309
1310/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose
1311 * @{
1312 */
1313
1314#define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT
1315#define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT
1316#define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE
1317
1318/**
1319 * @}
1320 */
1321
1322
1323/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose
1324 * @{
1325 */
1326#define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD
1327#define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX
1328#define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX
1329#define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX
1330#define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX
1331#define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L
1332#define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H
1333#define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM
1334#define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES
1335#define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX
1336#define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT
1337#define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION
1338#define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET
1339
1340/**
1341 * @}
1342 */
1343
1344
1345/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose
1346 * @{
1347 */
1348#define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
1349#define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
1350#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
1351#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
1352#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
1353#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
1354#define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE
1355#define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE
1356#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE
1357#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE
1358#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE
1359#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE
1360#define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine
1361#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine
1362#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig
1363#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig
1364#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE()
1365#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
1366#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
1367#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
1368#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
1369#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
1370#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
1371#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
1372#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
1373#define __HAL_PWR_PVM_DISABLE() HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4()
1374#define __HAL_PWR_PVM_ENABLE() HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4()
1375#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention
1376#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention
1377#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2
1378#define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2
1379#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE
1380#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE
1381#define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB
1382#define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB
1383
1384#if defined (STM32F4)
1385#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT()
1386#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT()
1387#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG()
1388#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG()
1389#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT()
1390#else
1391#define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG
1392#define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT
1393#define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT
1394#define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT
1395#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG
1396#endif /* STM32F4 */
1397/**
1398 * @}
1399 */
1400
1401
1402/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose
1403 * @{
1404 */
1405
1406#define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI
1407#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI
1408
1409#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
1410#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
1411
1412#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
1413#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
1414#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE
1415#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE
1416#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET
1417#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET
1418#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE
1419#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE
1420#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET
1421#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET
1422#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE
1423#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE
1424#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE
1425#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE
1426#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET
1427#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET
1428#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE
1429#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE
1430#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET
1431#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET
1432#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
1433#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
1434#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
1435#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
1436#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
1437#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
1438#define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE
1439#define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE
1440#define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE
1441#define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE
1442#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
1443#define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET
1444#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
1445#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
1446#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
1447#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
1448#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET
1449#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET
1450#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET
1451#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET
1452#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET
1453#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET
1454#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET
1455#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET
1456#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET
1457#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
1458#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
1459#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
1460#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
1461#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
1462#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
1463#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET
1464#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
1465#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
1466#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE
1467#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE
1468#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
1469#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
1470#define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
1471#define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
1472#define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
1473#define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
1474#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE
1475#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE
1476#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET
1477#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET
1478#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE
1479#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE
1480#define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE
1481#define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE
1482#define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET
1483#define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET
1484#define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE
1485#define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE
1486#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET
1487#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET
1488#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE
1489#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE
1490#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE
1491#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE
1492#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET
1493#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET
1494#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE
1495#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE
1496#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET
1497#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET
1498#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE
1499#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE
1500#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE
1501#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE
1502#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET
1503#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET
1504#define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE
1505#define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE
1506#define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET
1507#define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET
1508#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE
1509#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE
1510#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE
1511#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE
1512#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET
1513#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET
1514#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE
1515#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE
1516#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE
1517#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE
1518#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET
1519#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET
1520#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE
1521#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
1522#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE
1523#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE
1524#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET
1525#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET
1526#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE
1527#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE
1528#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET
1529#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET
1530#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE
1531#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE
1532#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE
1533#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE
1534#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE
1535#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE
1536#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE
1537#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE
1538#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE
1539#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE
1540#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET
1541#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET
1542#define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE
1543#define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE
1544#define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET
1545#define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET
1546#define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE
1547#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE
1548#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE
1549#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE
1550#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE
1551#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE
1552#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET
1553#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET
1554#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE
1555#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE
1556#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE
1557#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE
1558#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE
1559#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE
1560#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET
1561#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET
1562#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE
1563#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE
1564#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE
1565#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE
1566#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET
1567#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET
1568#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE
1569#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE
1570#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE
1571#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE
1572#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET
1573#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET
1574#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE
1575#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE
1576#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE
1577#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE
1578#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET
1579#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET
1580#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE
1581#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE
1582#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE
1583#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE
1584#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET
1585#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET
1586#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE
1587#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE
1588#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE
1589#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE
1590#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET
1591#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET
1592#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE
1593#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE
1594#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE
1595#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE
1596#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET
1597#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET
1598#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE
1599#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE
1600#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE
1601#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE
1602#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET
1603#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET
1604#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE
1605#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE
1606#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE
1607#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE
1608#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET
1609#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET
1610#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE
1611#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE
1612#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE
1613#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE
1614#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET
1615#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET
1616#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE
1617#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE
1618#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE
1619#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE
1620#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET
1621#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET
1622#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE
1623#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE
1624#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE
1625#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE
1626#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET
1627#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET
1628#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE
1629#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE
1630#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE
1631#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE
1632#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET
1633#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET
1634#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE
1635#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE
1636#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE
1637#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE
1638#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET
1639#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET
1640#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE
1641#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE
1642#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE
1643#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE
1644#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET
1645#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET
1646#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE
1647#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE
1648#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE
1649#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE
1650#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET
1651#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET
1652#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE
1653#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE
1654#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE
1655#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE
1656#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET
1657#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET
1658#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE
1659#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE
1660#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE
1661#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE
1662#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET
1663#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET
1664#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE
1665#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE
1666#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE
1667#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE
1668#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET
1669#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET
1670#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE
1671#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE
1672#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE
1673#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE
1674#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET
1675#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET
1676#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE
1677#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE
1678#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE
1679#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE
1680#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET
1681#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET
1682#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE
1683#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE
1684#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE
1685#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE
1686#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET
1687#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET
1688#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
1689#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
1690#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE
1691#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE
1692#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE
1693#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE
1694#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET
1695#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET
1696#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE
1697#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE
1698#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE
1699#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE
1700#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET
1701#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET
1702#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE
1703#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE
1704#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE
1705#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE
1706#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET
1707#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET
1708#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE
1709#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE
1710#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE
1711#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE
1712#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET
1713#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET
1714#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE
1715#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE
1716#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE
1717#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE
1718#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE
1719#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE
1720#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE
1721#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE
1722#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE
1723#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE
1724#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET
1725#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET
1726#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE
1727#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE
1728#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE
1729#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE
1730#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET
1731#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET
1732#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE
1733#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE
1734#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE
1735#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE
1736#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET
1737#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET
1738#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE
1739#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE
1740#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET
1741#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET
1742#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE
1743#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE
1744#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET
1745#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET
1746#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE
1747#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE
1748#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET
1749#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET
1750#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE
1751#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE
1752#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET
1753#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET
1754#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE
1755#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE
1756#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET
1757#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET
1758#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE
1759#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE
1760#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE
1761#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE
1762#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET
1763#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET
1764#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE
1765#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE
1766#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE
1767#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE
1768#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET
1769#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET
1770#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE
1771#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE
1772#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE
1773#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE
1774#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET
1775#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET
1776#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE
1777#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE
1778#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE
1779#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE
1780#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET
1781#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET
1782#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE
1783#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE
1784#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE
1785#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE
1786#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET
1787#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET
1788#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE
1789#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE
1790#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE
1791#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE
1792#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET
1793#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET
1794#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE
1795#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE
1796#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE
1797#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE
1798#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET
1799#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET
1800#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE
1801#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE
1802#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE
1803#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE
1804#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET
1805#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET
1806#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE
1807#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE
1808#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE
1809#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE
1810#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET
1811#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET
1812#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE
1813#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE
1814#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE
1815#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE
1816#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET
1817#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET
1818#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE
1819#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE
1820#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET
1821#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET
1822#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE
1823#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE
1824#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE
1825#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE
1826#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET
1827#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET
1828#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
1829#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
1830#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
1831#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
1832#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
1833#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
1834#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
1835#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
1836#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
1837#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
1838#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
1839#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
1840#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE
1841#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE
1842#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE
1843#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE
1844#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET
1845#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET
1846#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE
1847#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE
1848#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE
1849#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE
1850#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET
1851#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET
1852#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE
1853#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE
1854#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE
1855#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE
1856#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
1857#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
1858#define __USART4_CLK_DISABLE __HAL_RCC_USART4_CLK_DISABLE
1859#define __USART4_CLK_ENABLE __HAL_RCC_USART4_CLK_ENABLE
1860#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_USART4_CLK_SLEEP_ENABLE
1861#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_USART4_CLK_SLEEP_DISABLE
1862#define __USART4_FORCE_RESET __HAL_RCC_USART4_FORCE_RESET
1863#define __USART4_RELEASE_RESET __HAL_RCC_USART4_RELEASE_RESET
1864#define __USART5_CLK_DISABLE __HAL_RCC_USART5_CLK_DISABLE
1865#define __USART5_CLK_ENABLE __HAL_RCC_USART5_CLK_ENABLE
1866#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_USART5_CLK_SLEEP_ENABLE
1867#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_USART5_CLK_SLEEP_DISABLE
1868#define __USART5_FORCE_RESET __HAL_RCC_USART5_FORCE_RESET
1869#define __USART5_RELEASE_RESET __HAL_RCC_USART5_RELEASE_RESET
1870#define __USART7_CLK_DISABLE __HAL_RCC_USART7_CLK_DISABLE
1871#define __USART7_CLK_ENABLE __HAL_RCC_USART7_CLK_ENABLE
1872#define __USART7_FORCE_RESET __HAL_RCC_USART7_FORCE_RESET
1873#define __USART7_RELEASE_RESET __HAL_RCC_USART7_RELEASE_RESET
1874#define __USART8_CLK_DISABLE __HAL_RCC_USART8_CLK_DISABLE
1875#define __USART8_CLK_ENABLE __HAL_RCC_USART8_CLK_ENABLE
1876#define __USART8_FORCE_RESET __HAL_RCC_USART8_FORCE_RESET
1877#define __USART8_RELEASE_RESET __HAL_RCC_USART8_RELEASE_RESET
1878#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE
1879#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE
1880#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET
1881#define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE
1882#define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE
1883#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE
1884#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE
1885#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET
1886#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
1887#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE
1888#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE
1889#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE
1890#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET
1891#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET
1892#define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE
1893#define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE
1894#define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET
1895#define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET
1896#define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE
1897#define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE
1898#define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE
1899#define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE
1900#define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET
1901#define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET
1902#define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE
1903#define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE
1904#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE
1905#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE
1906#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE
1907#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE
1908#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET
1909#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET
1910#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE
1911#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE
1912
1913#define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
1914#define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
1915#define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE
1916#define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE
1917#define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE
1918#define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE
1919#define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE
1920#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE
1921#define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE
1922#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE
1923#define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE
1924#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE
1925#define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE
1926#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE
1927#define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE
1928#define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE
1929#define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE
1930#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE
1931#define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE
1932#define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET
1933#define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET
1934#define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE
1935#define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE
1936#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE
1937#define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE
1938#define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE
1939#define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET
1940#define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET
1941#define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE
1942#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE
1943#define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE
1944#define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE
1945#define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET
1946#define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET
1947#define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE
1948#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE
1949#define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE
1950#define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE
1951#define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET
1952#define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET
1953#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE
1954#define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE
1955#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE
1956#define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE
1957#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE
1958#define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE
1959#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE
1960#define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE
1961#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE
1962#define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE
1963#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE
1964#define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE
1965#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE
1966#define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE
1967#define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE
1968#define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE
1969#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE
1970#define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE
1971#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE
1972#define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE
1973#define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE
1974#define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET
1975#define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET
1976#define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE
1977#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE
1978#define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE
1979#define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE
1980#define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET
1981#define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET
1982#define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE
1983#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE
1984#define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE
1985#define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE
1986#define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET
1987#define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET
1988#define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE
1989#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE
1990#define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE
1991#define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE
1992#define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET
1993#define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET
1994#define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE
1995#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE
1996#define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE
1997#define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE
1998#define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET
1999#define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE
2000#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE
2001#define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE
2002#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE
2003#define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE
2004#define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE
2005#define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET
2006#define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET
2007#define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE
2008#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE
2009#define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE
2010#define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
2011#define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET
2012#define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET
2013#define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE
2014#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE
2015#define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE
2016#define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE
2017#define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET
2018#define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
2019#define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE
2020#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE
2021#define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
2022#define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
2023#define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
2024#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
2025#define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
2026#define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
2027#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
2028#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
2029#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED
2030#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED
2031#define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
2032#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
2033#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
2034#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
2035#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED
2036#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED
2037#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
2038#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE
2039#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
2040#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE
2041#define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE
2042#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE
2043#define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE
2044#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE
2045#define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE
2046#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE
2047#define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET
2048#define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET
2049#define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE
2050#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE
2051#define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
2052#define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
2053#define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
2054#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
2055#define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE
2056#define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE
2057#define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET
2058#define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET
2059#define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE
2060#define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE
2061
2062/* alias define maintained for legacy */
2063#define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
2064#define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
2065
2066#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
2067#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
2068#define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE
2069#define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE
2070#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
2071#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
2072#define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE
2073#define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE
2074#define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE
2075#define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE
2076#define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE
2077#define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE
2078#define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE
2079#define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE
2080#define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE
2081#define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE
2082#define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE
2083#define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE
2084#define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE
2085#define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE
2086#define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE
2087#define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE
2088
2089#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
2090#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
2091#define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET
2092#define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET
2093#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
2094#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
2095#define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET
2096#define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET
2097#define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET
2098#define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET
2099#define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET
2100#define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET
2101#define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET
2102#define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET
2103#define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET
2104#define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET
2105#define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET
2106#define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET
2107#define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET
2108#define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET
2109#define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET
2110#define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET
2111
2112#define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED
2113#define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED
2114#define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
2115#define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED
2116#define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED
2117#define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED
2118#define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED
2119#define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED
2120#define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED
2121#define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED
2122#define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED
2123#define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED
2124#define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED
2125#define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED
2126#define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED
2127#define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED
2128#define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED
2129#define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED
2130#define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED
2131#define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED
2132#define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED
2133#define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED
2134#define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED
2135#define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED
2136#define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED
2137#define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED
2138#define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED
2139#define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED
2140#define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED
2141#define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED
2142#define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED
2143#define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED
2144#define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED
2145#define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED
2146#define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED
2147#define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED
2148#define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED
2149#define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED
2150#define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED
2151#define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED
2152#define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED
2153#define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED
2154#define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED
2155#define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED
2156#define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED
2157#define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED
2158#define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED
2159#define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED
2160#define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED
2161#define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED
2162#define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED
2163#define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED
2164#define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED
2165#define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED
2166#define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED
2167#define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED
2168#define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED
2169#define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED
2170#define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED
2171#define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED
2172#define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED
2173#define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED
2174#define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED
2175#define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED
2176#define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED
2177#define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED
2178#define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED
2179#define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED
2180#define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED
2181#define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED
2182#define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED
2183#define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED
2184#define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED
2185#define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED
2186#define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED
2187#define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED
2188#define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED
2189#define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED
2190#define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED
2191#define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED
2192#define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED
2193#define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED
2194#define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED
2195#define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED
2196#define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED
2197#define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED
2198#define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED
2199#define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED
2200#define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED
2201#define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED
2202#define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED
2203#define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED
2204#define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED
2205#define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED
2206#define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED
2207#define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED
2208#define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED
2209#define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED
2210#define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED
2211#define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED
2212#define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED
2213#define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED
2214#define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED
2215#define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED
2216#define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED
2217#define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED
2218#define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED
2219#define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED
2220#define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED
2221#define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED
2222#define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED
2223#define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED
2224#define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED
2225#define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED
2226#define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED
2227#define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED
2228
2229#if defined(STM32F4)
2230#define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
2231#define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
2232#define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
2233#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
2234#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
2235#define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
2236#define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
2237#define Sdmmc1ClockSelection SdioClockSelection
2238#define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO
2239#define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48
2240#define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK
2241#define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG
2242#define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE
2243#endif
2244
2245#if defined(STM32F7) || defined(STM32L4)
2246#define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE
2247#define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET
2248#define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET
2249#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE
2250#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE
2251#define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE
2252#define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE
2253#define SdioClockSelection Sdmmc1ClockSelection
2254#define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1
2255#define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG
2256#define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE
2257#endif
2258
2259#if defined(STM32F7)
2260#define RCC_SDIOCLKSOURCE_CK48 RCC_SDMMC1CLKSOURCE_CLK48
2261#define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK
2262#endif
2263
2264#define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG
2265#define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG
2266
2267#define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE
2268
2269#define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE
2270#define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE
2271#define IS_RCC_SYSCLK_DIV IS_RCC_HCLK
2272#define IS_RCC_HCLK_DIV IS_RCC_PCLK
2273
2274#define RCC_IT_HSI14 RCC_IT_HSI14RDY
2275
2276#define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE
2277#define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG
2278#define RCC_MCO_NODIV RCC_MCODIV_1
2279#define RCC_MCO_DIV1 RCC_MCODIV_1
2280#define RCC_MCO_DIV2 RCC_MCODIV_2
2281#define RCC_MCO_DIV4 RCC_MCODIV_4
2282#define RCC_MCO_DIV8 RCC_MCODIV_8
2283#define RCC_MCO_DIV16 RCC_MCODIV_16
2284#define RCC_MCO_DIV32 RCC_MCODIV_32
2285#define RCC_MCO_DIV64 RCC_MCODIV_64
2286#define RCC_MCO_DIV128 RCC_MCODIV_128
2287#define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK
2288#define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI
2289#define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE
2290#define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK
2291#define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI
2292#define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14
2293#define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48
2294#define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE
2295#define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK
2296#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
2297#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
2298
2299#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
2300
2301#define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1
2302#define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL
2303#define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI
2304#define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL
2305#define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL
2306#define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5
2307#define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2
2308#define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3
2309
2310#define HSION_BitNumber RCC_HSION_BIT_NUMBER
2311#define HSION_BITNUMBER RCC_HSION_BIT_NUMBER
2312#define HSEON_BitNumber RCC_HSEON_BIT_NUMBER
2313#define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER
2314#define MSION_BITNUMBER RCC_MSION_BIT_NUMBER
2315#define CSSON_BitNumber RCC_CSSON_BIT_NUMBER
2316#define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER
2317#define PLLON_BitNumber RCC_PLLON_BIT_NUMBER
2318#define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER
2319#define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER
2320#define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER
2321#define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER
2322#define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER
2323#define BDRST_BitNumber RCC_BDRST_BIT_NUMBER
2324#define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER
2325#define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER
2326#define LSION_BitNumber RCC_LSION_BIT_NUMBER
2327#define LSION_BITNUMBER RCC_LSION_BIT_NUMBER
2328#define LSEON_BitNumber RCC_LSEON_BIT_NUMBER
2329#define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER
2330#define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER
2331#define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER
2332#define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER
2333#define RMVF_BitNumber RCC_RMVF_BIT_NUMBER
2334#define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER
2335#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER
2336#define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS
2337#define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS
2338#define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS
2339#define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS
2340#define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE
2341#define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE
2342
2343#define CR_HSION_BB RCC_CR_HSION_BB
2344#define CR_CSSON_BB RCC_CR_CSSON_BB
2345#define CR_PLLON_BB RCC_CR_PLLON_BB
2346#define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB
2347#define CR_MSION_BB RCC_CR_MSION_BB
2348#define CSR_LSION_BB RCC_CSR_LSION_BB
2349#define CSR_LSEON_BB RCC_CSR_LSEON_BB
2350#define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB
2351#define CSR_RTCEN_BB RCC_CSR_RTCEN_BB
2352#define CSR_RTCRST_BB RCC_CSR_RTCRST_BB
2353#define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB
2354#define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB
2355#define BDCR_BDRST_BB RCC_BDCR_BDRST_BB
2356#define CR_HSEON_BB RCC_CR_HSEON_BB
2357#define CSR_RMVF_BB RCC_CSR_RMVF_BB
2358#define CR_PLLSAION_BB RCC_CR_PLLSAION_BB
2359#define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB
2360
2361/**
2362 * @}
2363 */
2364
2365/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose
2366 * @{
2367 */
2368#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit)
2369
2370/**
2371 * @}
2372 */
2373
2374/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
2375 * @{
2376 */
2377
2378#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
2379#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT
2380#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT
2381
2382#if defined (STM32F1)
2383#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()
2384
2385#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT()
2386
2387#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT()
2388
2389#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG()
2390
2391#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()
2392#else
2393#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \
2394 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \
2395 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
2396#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \
2397 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
2398 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
2399#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \
2400 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
2401 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
2402#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \
2403 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
2404 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
2405#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \
2406 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \
2407 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
2408#endif /* STM32F1 */
2409
2410#define IS_ALARM IS_RTC_ALARM
2411#define IS_ALARM_MASK IS_RTC_ALARM_MASK
2412#define IS_TAMPER IS_RTC_TAMPER
2413#define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE
2414#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER
2415#define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT
2416#define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE
2417#define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION
2418#define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE
2419#define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ
2420#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION
2421#define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER
2422#define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK
2423#define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER
2424
2425#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE
2426#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE
2427
2428/**
2429 * @}
2430 */
2431
2432/** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose
2433 * @{
2434 */
2435
2436#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE
2437#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS
2438
2439#if defined(STM32F4)
2440#define SD_SDMMC_DISABLED SD_SDIO_DISABLED
2441#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY
2442#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED
2443#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION
2444#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND
2445#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT
2446#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED
2447#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE
2448#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE
2449#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE
2450#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL
2451#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT
2452#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT
2453#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG
2454#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG
2455#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT
2456#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT
2457#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS
2458#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT
2459#define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND
2460/* alias CMSIS */
2461#define SDMMC1_IRQn SDIO_IRQn
2462#define SDMMC1_IRQHandler SDIO_IRQHandler
2463#endif
2464
2465#if defined(STM32F7) || defined(STM32L4)
2466#define SD_SDIO_DISABLED SD_SDMMC_DISABLED
2467#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY
2468#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED
2469#define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION
2470#define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND
2471#define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT
2472#define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED
2473#define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE
2474#define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE
2475#define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE
2476#define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE
2477#define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT
2478#define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT
2479#define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG
2480#define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG
2481#define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT
2482#define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT
2483#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS
2484#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT
2485#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND
2486/* alias CMSIS for compatibilities */
2487#define SDIO_IRQn SDMMC1_IRQn
2488#define SDIO_IRQHandler SDMMC1_IRQHandler
2489#endif
2490/**
2491 * @}
2492 */
2493
2494/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose
2495 * @{
2496 */
2497
2498#define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT
2499#define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT
2500#define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE
2501#define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE
2502#define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE
2503#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE
2504
2505#define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
2506#define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
2507
2508#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE
2509
2510/**
2511 * @}
2512 */
2513
2514/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose
2515 * @{
2516 */
2517#define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1
2518#define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2
2519#define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START
2520#define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH
2521#define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR
2522#define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE
2523#define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE
2524#define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED
2525/**
2526 * @}
2527 */
2528
2529/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose
2530 * @{
2531 */
2532
2533#define __HAL_SPI_1LINE_TX SPI_1LINE_TX
2534#define __HAL_SPI_1LINE_RX SPI_1LINE_RX
2535#define __HAL_SPI_RESET_CRC SPI_RESET_CRC
2536
2537/**
2538 * @}
2539 */
2540
2541/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose
2542 * @{
2543 */
2544
2545#define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
2546#define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION
2547#define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
2548#define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION
2549
2550#define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD
2551
2552#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE
2553#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE
2554
2555/**
2556 * @}
2557 */
2558
2559
2560/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose
2561 * @{
2562 */
2563
2564#define __USART_ENABLE_IT __HAL_USART_ENABLE_IT
2565#define __USART_DISABLE_IT __HAL_USART_DISABLE_IT
2566#define __USART_ENABLE __HAL_USART_ENABLE
2567#define __USART_DISABLE __HAL_USART_DISABLE
2568
2569#define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
2570#define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
2571
2572/**
2573 * @}
2574 */
2575
2576/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose
2577 * @{
2578 */
2579#define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE
2580
2581#define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE
2582#define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE
2583#define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE
2584#define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE
2585
2586#define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE
2587#define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE
2588#define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE
2589#define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE
2590
2591#define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT
2592#define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT
2593#define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG
2594#define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG
2595#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE
2596#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE
2597#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
2598
2599#define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT
2600#define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT
2601#define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG
2602#define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG
2603#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE
2604#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
2605#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
2606#define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT
2607
2608#define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT
2609#define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT
2610#define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG
2611#define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG
2612#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE
2613#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
2614#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
2615#define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT
2616
2617#define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup
2618#define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup
2619
2620#define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo
2621#define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo
2622/**
2623 * @}
2624 */
2625
2626/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose
2627 * @{
2628 */
2629#define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE
2630#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE
2631
2632#define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
2633#define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT
2634
2635#define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
2636
2637#define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN
2638#define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER
2639#define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER
2640#define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER
2641#define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD
2642#define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD
2643#define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION
2644#define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION
2645#define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER
2646#define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER
2647#define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE
2648#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE
2649
2650#define TIM_TS_ITR0 ((uint32_t)0x0000)
2651#define TIM_TS_ITR1 ((uint32_t)0x0010)
2652#define TIM_TS_ITR2 ((uint32_t)0x0020)
2653#define TIM_TS_ITR3 ((uint32_t)0x0030)
2654#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
2655 ((SELECTION) == TIM_TS_ITR1) || \
2656 ((SELECTION) == TIM_TS_ITR2) || \
2657 ((SELECTION) == TIM_TS_ITR3))
2658
2659#define TIM_CHANNEL_1 ((uint32_t)0x0000)
2660#define TIM_CHANNEL_2 ((uint32_t)0x0004)
2661#define IS_TIM_PWMI_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
2662 ((CHANNEL) == TIM_CHANNEL_2))
2663
2664#define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000)
2665#define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE)
2666
2667#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OUTPUTNSTATE_DISABLE) || \
2668 ((STATE) == TIM_OUTPUTNSTATE_ENABLE))
2669
2670#define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000)
2671#define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E)
2672
2673#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OUTPUTSTATE_DISABLE) || \
2674 ((STATE) == TIM_OUTPUTSTATE_ENABLE))
2675/**
2676 * @}
2677 */
2678
2679/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose
2680 * @{
2681 */
2682
2683#define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT
2684#define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT
2685#define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG
2686#define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG
2687#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER
2688#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER
2689#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER
2690
2691#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE
2692#define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE
2693#define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE
2694/**
2695 * @}
2696 */
2697
2698/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose
2699 * @{
2700 */
2701#define __HAL_LTDC_LAYER LTDC_LAYER
2702/**
2703 * @}
2704 */
2705
2706/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose
2707 * @{
2708 */
2709#define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE
2710#define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE
2711#define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE
2712#define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE
2713#define SAI_STREOMODE SAI_STEREOMODE
2714#define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY
2715#define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL
2716#define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL
2717#define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL
2718#define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL
2719#define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL
2720#define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE
2721
2722/**
2723 * @}
2724 */
2725
2726
2727/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
2728 * @{
2729 */
2730
2731/**
2732 * @}
2733 */
2734
2735#ifdef __cplusplus
2736}
2737#endif
2738
2739#endif /* ___STM32_HAL_LEGACY */
2740
2741/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
2742
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