source: asp3_wo_tecs/trunk/arch/arm_m_gcc/stm32f4xx_stm32cube/CMSIS/Include/core_cm4.h@ 303

Last change on this file since 303 was 303, checked in by ertl-honda, 7 years ago

nucleo_f401re依存部の追加
File size: 109.9 KB
Line 
1/**************************************************************************//**
2 * @file core_cm4.h
3 * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
4 * @version V4.10
5 * @date 18. March 2015
6 *
7 * @note
8 *
9 ******************************************************************************/
10/* Copyright (c) 2009 - 2015 ARM LIMITED
11
12 All rights reserved.
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 - Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 - Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 - Neither the name of ARM nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23 *
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ---------------------------------------------------------------------------*/
36
37
38#if defined ( __ICCARM__ )
39 #pragma system_include /* treat file as system include file for MISRA check */
40#endif
41
42#ifndef __CORE_CM4_H_GENERIC
43#define __CORE_CM4_H_GENERIC
44
45#ifdef __cplusplus
46 extern "C" {
47#endif
48
49/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
50 CMSIS violates the following MISRA-C:2004 rules:
51
52 \li Required Rule 8.5, object/function definition in header file.<br>
53 Function definitions in header files are used to allow 'inlining'.
54
55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
56 Unions are used for effective representation of core registers.
57
58 \li Advisory Rule 19.7, Function-like macro defined.<br>
59 Function-like macros are used to allow more efficient code.
60 */
61
62
63/*******************************************************************************
64 * CMSIS definitions
65 ******************************************************************************/
66/** \ingroup Cortex_M4
67 @{
68 */
69
70/* CMSIS CM4 definitions */
71#define __CM4_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
72#define __CM4_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
73#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \
74 __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
75
76#define __CORTEX_M (0x04) /*!< Cortex-M Core */
77
78
79#if defined ( __CC_ARM )
80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
82 #define __STATIC_INLINE static __inline
83
84#elif defined ( __GNUC__ )
85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
87 #define __STATIC_INLINE static inline
88
89#elif defined ( __ICCARM__ )
90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
92 #define __STATIC_INLINE static inline
93
94#elif defined ( __TMS470__ )
95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
96 #define __STATIC_INLINE static inline
97
98#elif defined ( __TASKING__ )
99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
101 #define __STATIC_INLINE static inline
102
103#elif defined ( __CSMC__ )
104 #define __packed
105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
107 #define __STATIC_INLINE static inline
108
109#endif
110
111/** __FPU_USED indicates whether an FPU is used or not.
112 For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
113*/
114#if defined ( __CC_ARM )
115 #if defined __TARGET_FPU_VFP
116 #if (__FPU_PRESENT == 1)
117 #define __FPU_USED 1
118 #else
119 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
120 #define __FPU_USED 0
121 #endif
122 #else
123 #define __FPU_USED 0
124 #endif
125
126#elif defined ( __GNUC__ )
127 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
128 #if (__FPU_PRESENT == 1)
129 #define __FPU_USED 1
130 #else
131 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
132 #define __FPU_USED 0
133 #endif
134 #else
135 #define __FPU_USED 0
136 #endif
137
138#elif defined ( __ICCARM__ )
139 #if defined __ARMVFP__
140 #if (__FPU_PRESENT == 1)
141 #define __FPU_USED 1
142 #else
143 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
144 #define __FPU_USED 0
145 #endif
146 #else
147 #define __FPU_USED 0
148 #endif
149
150#elif defined ( __TMS470__ )
151 #if defined __TI_VFP_SUPPORT__
152 #if (__FPU_PRESENT == 1)
153 #define __FPU_USED 1
154 #else
155 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
156 #define __FPU_USED 0
157 #endif
158 #else
159 #define __FPU_USED 0
160 #endif
161
162#elif defined ( __TASKING__ )
163 #if defined __FPU_VFP__
164 #if (__FPU_PRESENT == 1)
165 #define __FPU_USED 1
166 #else
167 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
168 #define __FPU_USED 0
169 #endif
170 #else
171 #define __FPU_USED 0
172 #endif
173
174#elif defined ( __CSMC__ ) /* Cosmic */
175 #if ( __CSMC__ & 0x400) // FPU present for parser
176 #if (__FPU_PRESENT == 1)
177 #define __FPU_USED 1
178 #else
179 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
180 #define __FPU_USED 0
181 #endif
182 #else
183 #define __FPU_USED 0
184 #endif
185#endif
186
187#include <stdint.h> /* standard types definitions */
188#include <core_cmInstr.h> /* Core Instruction Access */
189#include <core_cmFunc.h> /* Core Function Access */
190#include <core_cmSimd.h> /* Compiler specific SIMD Intrinsics */
191
192#ifdef __cplusplus
193}
194#endif
195
196#endif /* __CORE_CM4_H_GENERIC */
197
198#ifndef __CMSIS_GENERIC
199
200#ifndef __CORE_CM4_H_DEPENDANT
201#define __CORE_CM4_H_DEPENDANT
202
203#ifdef __cplusplus
204 extern "C" {
205#endif
206
207/* check device defines and use defaults */
208#if defined __CHECK_DEVICE_DEFINES
209 #ifndef __CM4_REV
210 #define __CM4_REV 0x0000
211 #warning "__CM4_REV not defined in device header file; using default!"
212 #endif
213
214 #ifndef __FPU_PRESENT
215 #define __FPU_PRESENT 0
216 #warning "__FPU_PRESENT not defined in device header file; using default!"
217 #endif
218
219 #ifndef __MPU_PRESENT
220 #define __MPU_PRESENT 0
221 #warning "__MPU_PRESENT not defined in device header file; using default!"
222 #endif
223
224 #ifndef __NVIC_PRIO_BITS
225 #define __NVIC_PRIO_BITS 4
226 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
227 #endif
228
229 #ifndef __Vendor_SysTickConfig
230 #define __Vendor_SysTickConfig 0
231 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
232 #endif
233#endif
234
235/* IO definitions (access restrictions to peripheral registers) */
236/**
237 \defgroup CMSIS_glob_defs CMSIS Global Defines
238
239 <strong>IO Type Qualifiers</strong> are used
240 \li to specify the access to peripheral variables.
241 \li for automatic generation of peripheral register debug information.
242*/
243#ifdef __cplusplus
244 #define __I volatile /*!< Defines 'read only' permissions */
245#else
246 #define __I volatile const /*!< Defines 'read only' permissions */
247#endif
248#define __O volatile /*!< Defines 'write only' permissions */
249#define __IO volatile /*!< Defines 'read / write' permissions */
250
251/*@} end of group Cortex_M4 */
252
253
254
255/*******************************************************************************
256 * Register Abstraction
257 Core Register contain:
258 - Core Register
259 - Core NVIC Register
260 - Core SCB Register
261 - Core SysTick Register
262 - Core Debug Register
263 - Core MPU Register
264 - Core FPU Register
265 ******************************************************************************/
266/** \defgroup CMSIS_core_register Defines and Type Definitions
267 \brief Type definitions and defines for Cortex-M processor based devices.
268*/
269
270/** \ingroup CMSIS_core_register
271 \defgroup CMSIS_CORE Status and Control Registers
272 \brief Core Register type definitions.
273 @{
274 */
275
276/** \brief Union type to access the Application Program Status Register (APSR).
277 */
278typedef union
279{
280 struct
281 {
282 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
283 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
284 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
285 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
286 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
287 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
288 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
289 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
290 } b; /*!< Structure used for bit access */
291 uint32_t w; /*!< Type used for word access */
292} APSR_Type;
293
294/* APSR Register Definitions */
295#define APSR_N_Pos 31 /*!< APSR: N Position */
296#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
297
298#define APSR_Z_Pos 30 /*!< APSR: Z Position */
299#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
300
301#define APSR_C_Pos 29 /*!< APSR: C Position */
302#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
303
304#define APSR_V_Pos 28 /*!< APSR: V Position */
305#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
306
307#define APSR_Q_Pos 27 /*!< APSR: Q Position */
308#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
309
310#define APSR_GE_Pos 16 /*!< APSR: GE Position */
311#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
312
313
314/** \brief Union type to access the Interrupt Program Status Register (IPSR).
315 */
316typedef union
317{
318 struct
319 {
320 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
321 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
322 } b; /*!< Structure used for bit access */
323 uint32_t w; /*!< Type used for word access */
324} IPSR_Type;
325
326/* IPSR Register Definitions */
327#define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
328#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
329
330
331/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
332 */
333typedef union
334{
335 struct
336 {
337 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
338 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
339 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
340 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
341 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
342 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
343 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
344 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
345 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
346 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
347 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
348 } b; /*!< Structure used for bit access */
349 uint32_t w; /*!< Type used for word access */
350} xPSR_Type;
351
352/* xPSR Register Definitions */
353#define xPSR_N_Pos 31 /*!< xPSR: N Position */
354#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
355
356#define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
357#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
358
359#define xPSR_C_Pos 29 /*!< xPSR: C Position */
360#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
361
362#define xPSR_V_Pos 28 /*!< xPSR: V Position */
363#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
364
365#define xPSR_Q_Pos 27 /*!< xPSR: Q Position */
366#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
367
368#define xPSR_IT_Pos 25 /*!< xPSR: IT Position */
369#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
370
371#define xPSR_T_Pos 24 /*!< xPSR: T Position */
372#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
373
374#define xPSR_GE_Pos 16 /*!< xPSR: GE Position */
375#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
376
377#define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
378#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
379
380
381/** \brief Union type to access the Control Registers (CONTROL).
382 */
383typedef union
384{
385 struct
386 {
387 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
388 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
389 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
390 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
391 } b; /*!< Structure used for bit access */
392 uint32_t w; /*!< Type used for word access */
393} CONTROL_Type;
394
395/* CONTROL Register Definitions */
396#define CONTROL_FPCA_Pos 2 /*!< CONTROL: FPCA Position */
397#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
398
399#define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
400#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
401
402#define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
403#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
404
405/*@} end of group CMSIS_CORE */
406
407
408/** \ingroup CMSIS_core_register
409 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
410 \brief Type definitions for the NVIC Registers
411 @{
412 */
413
414/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
415 */
416typedef struct
417{
418 __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
419 uint32_t RESERVED0[24];
420 __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
421 uint32_t RSERVED1[24];
422 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
423 uint32_t RESERVED2[24];
424 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
425 uint32_t RESERVED3[24];
426 __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
427 uint32_t RESERVED4[56];
428 __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
429 uint32_t RESERVED5[644];
430 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
431} NVIC_Type;
432
433/* Software Triggered Interrupt Register Definitions */
434#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
435#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
436
437/*@} end of group CMSIS_NVIC */
438
439
440/** \ingroup CMSIS_core_register
441 \defgroup CMSIS_SCB System Control Block (SCB)
442 \brief Type definitions for the System Control Block Registers
443 @{
444 */
445
446/** \brief Structure type to access the System Control Block (SCB).
447 */
448typedef struct
449{
450 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
451 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
452 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
453 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
454 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
455 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
456 __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
457 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
458 __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
459 __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
460 __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
461 __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
462 __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
463 __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
464 __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
465 __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
466 __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
467 __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
468 __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
469 uint32_t RESERVED0[5];
470 __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
471} SCB_Type;
472
473/* SCB CPUID Register Definitions */
474#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
475#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
476
477#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
478#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
479
480#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
481#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
482
483#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
484#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
485
486#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
487#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
488
489/* SCB Interrupt Control State Register Definitions */
490#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
491#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
492
493#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
494#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
495
496#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
497#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
498
499#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
500#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
501
502#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
503#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
504
505#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
506#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
507
508#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
509#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
510
511#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
512#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
513
514#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
515#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
516
517#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
518#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
519
520/* SCB Vector Table Offset Register Definitions */
521#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
522#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
523
524/* SCB Application Interrupt and Reset Control Register Definitions */
525#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
526#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
527
528#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
529#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
530
531#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
532#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
533
534#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
535#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
536
537#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
538#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
539
540#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
541#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
542
543#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
544#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
545
546/* SCB System Control Register Definitions */
547#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
548#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
549
550#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
551#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
552
553#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
554#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
555
556/* SCB Configuration Control Register Definitions */
557#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
558#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
559
560#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
561#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
562
563#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
564#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
565
566#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
567#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
568
569#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
570#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
571
572#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
573#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
574
575/* SCB System Handler Control and State Register Definitions */
576#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
577#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
578
579#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
580#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
581
582#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
583#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
584
585#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
586#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
587
588#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
589#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
590
591#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
592#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
593
594#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
595#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
596
597#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
598#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
599
600#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
601#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
602
603#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
604#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
605
606#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
607#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
608
609#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
610#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
611
612#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
613#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
614
615#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
616#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
617
618/* SCB Configurable Fault Status Registers Definitions */
619#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
620#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
621
622#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
623#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
624
625#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
626#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
627
628/* SCB Hard Fault Status Registers Definitions */
629#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
630#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
631
632#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
633#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
634
635#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
636#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
637
638/* SCB Debug Fault Status Register Definitions */
639#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
640#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
641
642#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
643#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
644
645#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
646#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
647
648#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
649#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
650
651#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
652#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
653
654/*@} end of group CMSIS_SCB */
655
656
657/** \ingroup CMSIS_core_register
658 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
659 \brief Type definitions for the System Control and ID Register not in the SCB
660 @{
661 */
662
663/** \brief Structure type to access the System Control and ID Register not in the SCB.
664 */
665typedef struct
666{
667 uint32_t RESERVED0[1];
668 __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
669 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
670} SCnSCB_Type;
671
672/* Interrupt Controller Type Register Definitions */
673#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
674#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
675
676/* Auxiliary Control Register Definitions */
677#define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */
678#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
679
680#define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */
681#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
682
683#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
684#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
685
686#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
687#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
688
689#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
690#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
691
692/*@} end of group CMSIS_SCnotSCB */
693
694
695/** \ingroup CMSIS_core_register
696 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
697 \brief Type definitions for the System Timer Registers.
698 @{
699 */
700
701/** \brief Structure type to access the System Timer (SysTick).
702 */
703typedef struct
704{
705 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
706 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
707 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
708 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
709} SysTick_Type;
710
711/* SysTick Control / Status Register Definitions */
712#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
713#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
714
715#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
716#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
717
718#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
719#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
720
721#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
722#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
723
724/* SysTick Reload Register Definitions */
725#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
726#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
727
728/* SysTick Current Register Definitions */
729#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
730#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
731
732/* SysTick Calibration Register Definitions */
733#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
734#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
735
736#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
737#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
738
739#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
740#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
741
742/*@} end of group CMSIS_SysTick */
743
744
745/** \ingroup CMSIS_core_register
746 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
747 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
748 @{
749 */
750
751/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
752 */
753typedef struct
754{
755 __O union
756 {
757 __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
758 __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
759 __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
760 } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
761 uint32_t RESERVED0[864];
762 __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
763 uint32_t RESERVED1[15];
764 __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
765 uint32_t RESERVED2[15];
766 __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
767 uint32_t RESERVED3[29];
768 __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
769 __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
770 __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
771 uint32_t RESERVED4[43];
772 __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
773 __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
774 uint32_t RESERVED5[6];
775 __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
776 __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
777 __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
778 __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
779 __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
780 __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
781 __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
782 __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
783 __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
784 __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
785 __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
786 __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
787} ITM_Type;
788
789/* ITM Trace Privilege Register Definitions */
790#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
791#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
792
793/* ITM Trace Control Register Definitions */
794#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
795#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
796
797#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
798#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
799
800#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
801#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
802
803#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
804#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
805
806#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
807#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
808
809#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
810#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
811
812#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
813#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
814
815#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
816#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
817
818#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
819#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
820
821/* ITM Integration Write Register Definitions */
822#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
823#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
824
825/* ITM Integration Read Register Definitions */
826#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
827#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
828
829/* ITM Integration Mode Control Register Definitions */
830#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
831#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
832
833/* ITM Lock Status Register Definitions */
834#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
835#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
836
837#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
838#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
839
840#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
841#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
842
843/*@}*/ /* end of group CMSIS_ITM */
844
845
846/** \ingroup CMSIS_core_register
847 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
848 \brief Type definitions for the Data Watchpoint and Trace (DWT)
849 @{
850 */
851
852/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
853 */
854typedef struct
855{
856 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
857 __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
858 __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
859 __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
860 __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
861 __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
862 __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
863 __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
864 __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
865 __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
866 __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
867 uint32_t RESERVED0[1];
868 __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
869 __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
870 __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
871 uint32_t RESERVED1[1];
872 __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
873 __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
874 __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
875 uint32_t RESERVED2[1];
876 __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
877 __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
878 __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
879} DWT_Type;
880
881/* DWT Control Register Definitions */
882#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
883#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
884
885#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
886#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
887
888#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
889#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
890
891#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
892#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
893
894#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
895#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
896
897#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
898#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
899
900#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
901#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
902
903#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
904#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
905
906#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
907#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
908
909#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
910#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
911
912#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
913#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
914
915#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
916#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
917
918#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
919#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
920
921#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
922#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
923
924#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
925#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
926
927#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
928#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
929
930#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
931#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
932
933#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
934#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
935
936/* DWT CPI Count Register Definitions */
937#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
938#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
939
940/* DWT Exception Overhead Count Register Definitions */
941#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
942#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
943
944/* DWT Sleep Count Register Definitions */
945#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
946#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
947
948/* DWT LSU Count Register Definitions */
949#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
950#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
951
952/* DWT Folded-instruction Count Register Definitions */
953#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
954#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
955
956/* DWT Comparator Mask Register Definitions */
957#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
958#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
959
960/* DWT Comparator Function Register Definitions */
961#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
962#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
963
964#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
965#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
966
967#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
968#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
969
970#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
971#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
972
973#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
974#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
975
976#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
977#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
978
979#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
980#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
981
982#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
983#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
984
985#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
986#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
987
988/*@}*/ /* end of group CMSIS_DWT */
989
990
991/** \ingroup CMSIS_core_register
992 \defgroup CMSIS_TPI Trace Port Interface (TPI)
993 \brief Type definitions for the Trace Port Interface (TPI)
994 @{
995 */
996
997/** \brief Structure type to access the Trace Port Interface Register (TPI).
998 */
999typedef struct
1000{
1001 __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
1002 __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
1003 uint32_t RESERVED0[2];
1004 __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
1005 uint32_t RESERVED1[55];
1006 __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
1007 uint32_t RESERVED2[131];
1008 __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
1009 __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
1010 __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
1011 uint32_t RESERVED3[759];
1012 __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
1013 __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
1014 __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
1015 uint32_t RESERVED4[1];
1016 __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
1017 __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
1018 __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
1019 uint32_t RESERVED5[39];
1020 __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
1021 __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
1022 uint32_t RESERVED7[8];
1023 __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
1024 __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
1025} TPI_Type;
1026
1027/* TPI Asynchronous Clock Prescaler Register Definitions */
1028#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
1029#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
1030
1031/* TPI Selected Pin Protocol Register Definitions */
1032#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
1033#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
1034
1035/* TPI Formatter and Flush Status Register Definitions */
1036#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
1037#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
1038
1039#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
1040#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
1041
1042#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
1043#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
1044
1045#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
1046#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
1047
1048/* TPI Formatter and Flush Control Register Definitions */
1049#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
1050#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
1051
1052#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
1053#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
1054
1055/* TPI TRIGGER Register Definitions */
1056#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
1057#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
1058
1059/* TPI Integration ETM Data Register Definitions (FIFO0) */
1060#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
1061#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
1062
1063#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
1064#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
1065
1066#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
1067#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
1068
1069#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
1070#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
1071
1072#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
1073#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
1074
1075#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
1076#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
1077
1078#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
1079#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
1080
1081/* TPI ITATBCTR2 Register Definitions */
1082#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
1083#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
1084
1085/* TPI Integration ITM Data Register Definitions (FIFO1) */
1086#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
1087#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
1088
1089#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
1090#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
1091
1092#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
1093#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
1094
1095#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
1096#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
1097
1098#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
1099#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
1100
1101#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
1102#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
1103
1104#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
1105#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
1106
1107/* TPI ITATBCTR0 Register Definitions */
1108#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
1109#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
1110
1111/* TPI Integration Mode Control Register Definitions */
1112#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
1113#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
1114
1115/* TPI DEVID Register Definitions */
1116#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
1117#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
1118
1119#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
1120#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
1121
1122#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
1123#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
1124
1125#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
1126#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
1127
1128#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
1129#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
1130
1131#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
1132#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
1133
1134/* TPI DEVTYPE Register Definitions */
1135#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
1136#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
1137
1138#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
1139#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
1140
1141/*@}*/ /* end of group CMSIS_TPI */
1142
1143
1144#if (__MPU_PRESENT == 1)
1145/** \ingroup CMSIS_core_register
1146 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
1147 \brief Type definitions for the Memory Protection Unit (MPU)
1148 @{
1149 */
1150
1151/** \brief Structure type to access the Memory Protection Unit (MPU).
1152 */
1153typedef struct
1154{
1155 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
1156 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
1157 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
1158 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
1159 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
1160 __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
1161 __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
1162 __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
1163 __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
1164 __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
1165 __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
1166} MPU_Type;
1167
1168/* MPU Type Register */
1169#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
1170#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
1171
1172#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
1173#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
1174
1175#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
1176#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
1177
1178/* MPU Control Register */
1179#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
1180#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
1181
1182#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
1183#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
1184
1185#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
1186#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
1187
1188/* MPU Region Number Register */
1189#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
1190#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
1191
1192/* MPU Region Base Address Register */
1193#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
1194#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
1195
1196#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
1197#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
1198
1199#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
1200#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
1201
1202/* MPU Region Attribute and Size Register */
1203#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
1204#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
1205
1206#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
1207#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
1208
1209#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
1210#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
1211
1212#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
1213#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
1214
1215#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
1216#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
1217
1218#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
1219#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
1220
1221#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
1222#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
1223
1224#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
1225#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
1226
1227#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
1228#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
1229
1230#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
1231#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
1232
1233/*@} end of group CMSIS_MPU */
1234#endif
1235
1236
1237#if (__FPU_PRESENT == 1)
1238/** \ingroup CMSIS_core_register
1239 \defgroup CMSIS_FPU Floating Point Unit (FPU)
1240 \brief Type definitions for the Floating Point Unit (FPU)
1241 @{
1242 */
1243
1244/** \brief Structure type to access the Floating Point Unit (FPU).
1245 */
1246typedef struct
1247{
1248 uint32_t RESERVED0[1];
1249 __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
1250 __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
1251 __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
1252 __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
1253 __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
1254} FPU_Type;
1255
1256/* Floating-Point Context Control Register */
1257#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */
1258#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
1259
1260#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */
1261#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
1262
1263#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */
1264#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
1265
1266#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */
1267#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
1268
1269#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */
1270#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
1271
1272#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */
1273#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
1274
1275#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */
1276#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
1277
1278#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */
1279#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
1280
1281#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */
1282#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
1283
1284/* Floating-Point Context Address Register */
1285#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */
1286#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
1287
1288/* Floating-Point Default Status Control Register */
1289#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */
1290#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
1291
1292#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */
1293#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
1294
1295#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */
1296#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
1297
1298#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */
1299#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
1300
1301/* Media and FP Feature Register 0 */
1302#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */
1303#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
1304
1305#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */
1306#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
1307
1308#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */
1309#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
1310
1311#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */
1312#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
1313
1314#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */
1315#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
1316
1317#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */
1318#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
1319
1320#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */
1321#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
1322
1323#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */
1324#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
1325
1326/* Media and FP Feature Register 1 */
1327#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */
1328#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
1329
1330#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */
1331#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
1332
1333#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */
1334#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
1335
1336#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */
1337#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
1338
1339/*@} end of group CMSIS_FPU */
1340#endif
1341
1342
1343/** \ingroup CMSIS_core_register
1344 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
1345 \brief Type definitions for the Core Debug Registers
1346 @{
1347 */
1348
1349/** \brief Structure type to access the Core Debug Register (CoreDebug).
1350 */
1351typedef struct
1352{
1353 __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
1354 __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
1355 __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
1356 __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
1357} CoreDebug_Type;
1358
1359/* Debug Halting Control and Status Register */
1360#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
1361#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
1362
1363#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
1364#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
1365
1366#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
1367#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
1368
1369#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
1370#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
1371
1372#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
1373#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
1374
1375#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
1376#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
1377
1378#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
1379#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
1380
1381#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
1382#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
1383
1384#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
1385#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
1386
1387#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
1388#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
1389
1390#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
1391#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
1392
1393#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
1394#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
1395
1396/* Debug Core Register Selector Register */
1397#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
1398#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
1399
1400#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
1401#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
1402
1403/* Debug Exception and Monitor Control Register */
1404#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
1405#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
1406
1407#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
1408#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
1409
1410#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
1411#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
1412
1413#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
1414#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
1415
1416#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
1417#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
1418
1419#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
1420#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
1421
1422#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
1423#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
1424
1425#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
1426#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
1427
1428#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
1429#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
1430
1431#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
1432#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
1433
1434#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
1435#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
1436
1437#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
1438#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
1439
1440#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
1441#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
1442
1443/*@} end of group CMSIS_CoreDebug */
1444
1445
1446/** \ingroup CMSIS_core_register
1447 \defgroup CMSIS_core_base Core Definitions
1448 \brief Definitions for base addresses, unions, and structures.
1449 @{
1450 */
1451
1452/* Memory mapping of Cortex-M4 Hardware */
1453#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
1454#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
1455#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
1456#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
1457#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
1458#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
1459#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
1460#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
1461
1462#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
1463#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
1464#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
1465#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
1466#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
1467#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
1468#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
1469#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
1470
1471#if (__MPU_PRESENT == 1)
1472 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
1473 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
1474#endif
1475
1476#if (__FPU_PRESENT == 1)
1477 #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
1478 #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
1479#endif
1480
1481/*@} */
1482
1483
1484
1485/*******************************************************************************
1486 * Hardware Abstraction Layer
1487 Core Function Interface contains:
1488 - Core NVIC Functions
1489 - Core SysTick Functions
1490 - Core Debug Functions
1491 - Core Register Access Functions
1492 ******************************************************************************/
1493/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
1494*/
1495
1496
1497
1498/* ########################## NVIC functions #################################### */
1499/** \ingroup CMSIS_Core_FunctionInterface
1500 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
1501 \brief Functions that manage interrupts and exceptions via the NVIC.
1502 @{
1503 */
1504
1505/** \brief Set Priority Grouping
1506
1507 The function sets the priority grouping field using the required unlock sequence.
1508 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
1509 Only values from 0..7 are used.
1510 In case of a conflict between priority grouping and available
1511 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
1512
1513 \param [in] PriorityGroup Priority grouping field.
1514 */
1515__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
1516{
1517 uint32_t reg_value;
1518 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1519
1520 reg_value = SCB->AIRCR; /* read old register configuration */
1521 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
1522 reg_value = (reg_value |
1523 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
1524 (PriorityGroupTmp << 8) ); /* Insert write key and priorty group */
1525 SCB->AIRCR = reg_value;
1526}
1527
1528
1529/** \brief Get Priority Grouping
1530
1531 The function reads the priority grouping field from the NVIC Interrupt Controller.
1532
1533 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
1534 */
1535__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
1536{
1537 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
1538}
1539
1540
1541/** \brief Enable External Interrupt
1542
1543 The function enables a device-specific interrupt in the NVIC interrupt controller.
1544
1545 \param [in] IRQn External interrupt number. Value cannot be negative.
1546 */
1547__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
1548{
1549 NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
1550}
1551
1552
1553/** \brief Disable External Interrupt
1554
1555 The function disables a device-specific interrupt in the NVIC interrupt controller.
1556
1557 \param [in] IRQn External interrupt number. Value cannot be negative.
1558 */
1559__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
1560{
1561 NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
1562}
1563
1564
1565/** \brief Get Pending Interrupt
1566
1567 The function reads the pending register in the NVIC and returns the pending bit
1568 for the specified interrupt.
1569
1570 \param [in] IRQn Interrupt number.
1571
1572 \return 0 Interrupt status is not pending.
1573 \return 1 Interrupt status is pending.
1574 */
1575__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
1576{
1577 return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1578}
1579
1580
1581/** \brief Set Pending Interrupt
1582
1583 The function sets the pending bit of an external interrupt.
1584
1585 \param [in] IRQn Interrupt number. Value cannot be negative.
1586 */
1587__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
1588{
1589 NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
1590}
1591
1592
1593/** \brief Clear Pending Interrupt
1594
1595 The function clears the pending bit of an external interrupt.
1596
1597 \param [in] IRQn External interrupt number. Value cannot be negative.
1598 */
1599__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
1600{
1601 NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
1602}
1603
1604
1605/** \brief Get Active Interrupt
1606
1607 The function reads the active register in NVIC and returns the active bit.
1608
1609 \param [in] IRQn Interrupt number.
1610
1611 \return 0 Interrupt status is not active.
1612 \return 1 Interrupt status is active.
1613 */
1614__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
1615{
1616 return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1617}
1618
1619
1620/** \brief Set Interrupt Priority
1621
1622 The function sets the priority of an interrupt.
1623
1624 \note The priority cannot be set for every core interrupt.
1625
1626 \param [in] IRQn Interrupt number.
1627 \param [in] priority Priority to set.
1628 */
1629__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
1630{
1631 if((int32_t)IRQn < 0) {
1632 SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
1633 }
1634 else {
1635 NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
1636 }
1637}
1638
1639
1640/** \brief Get Interrupt Priority
1641
1642 The function reads the priority of an interrupt. The interrupt
1643 number can be positive to specify an external (device specific)
1644 interrupt, or negative to specify an internal (core) interrupt.
1645
1646
1647 \param [in] IRQn Interrupt number.
1648 \return Interrupt Priority. Value is aligned automatically to the implemented
1649 priority bits of the microcontroller.
1650 */
1651__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
1652{
1653
1654 if((int32_t)IRQn < 0) {
1655 return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
1656 }
1657 else {
1658 return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS)));
1659 }
1660}
1661
1662
1663/** \brief Encode Priority
1664
1665 The function encodes the priority for an interrupt with the given priority group,
1666 preemptive priority value, and subpriority value.
1667 In case of a conflict between priority grouping and available
1668 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
1669
1670 \param [in] PriorityGroup Used priority group.
1671 \param [in] PreemptPriority Preemptive priority value (starting from 0).
1672 \param [in] SubPriority Subpriority value (starting from 0).
1673 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
1674 */
1675__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
1676{
1677 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1678 uint32_t PreemptPriorityBits;
1679 uint32_t SubPriorityBits;
1680
1681 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
1682 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
1683
1684 return (
1685 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
1686 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
1687 );
1688}
1689
1690
1691/** \brief Decode Priority
1692
1693 The function decodes an interrupt priority value with a given priority group to
1694 preemptive priority value and subpriority value.
1695 In case of a conflict between priority grouping and available
1696 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
1697
1698 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
1699 \param [in] PriorityGroup Used priority group.
1700 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
1701 \param [out] pSubPriority Subpriority value (starting from 0).
1702 */
1703__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
1704{
1705 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1706 uint32_t PreemptPriorityBits;
1707 uint32_t SubPriorityBits;
1708
1709 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
1710 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
1711
1712 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
1713 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
1714}
1715
1716
1717/** \brief System Reset
1718
1719 The function initiates a system reset request to reset the MCU.
1720 */
1721__STATIC_INLINE void NVIC_SystemReset(void)
1722{
1723 __DSB(); /* Ensure all outstanding memory accesses included
1724 buffered write are completed before reset */
1725 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
1726 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
1727 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
1728 __DSB(); /* Ensure completion of memory access */
1729 while(1) { __NOP(); } /* wait until reset */
1730}
1731
1732/*@} end of CMSIS_Core_NVICFunctions */
1733
1734
1735
1736/* ################################## SysTick function ############################################ */
1737/** \ingroup CMSIS_Core_FunctionInterface
1738 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
1739 \brief Functions that configure the System.
1740 @{
1741 */
1742
1743#if (__Vendor_SysTickConfig == 0)
1744
1745/** \brief System Tick Configuration
1746
1747 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
1748 Counter is in free running mode to generate periodic interrupts.
1749
1750 \param [in] ticks Number of ticks between two interrupts.
1751
1752 \return 0 Function succeeded.
1753 \return 1 Function failed.
1754
1755 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
1756 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
1757 must contain a vendor-specific implementation of this function.
1758
1759 */
1760__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
1761{
1762 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
1763
1764 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
1765 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
1766 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
1767 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
1768 SysTick_CTRL_TICKINT_Msk |
1769 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
1770 return (0UL); /* Function successful */
1771}
1772
1773#endif
1774
1775/*@} end of CMSIS_Core_SysTickFunctions */
1776
1777
1778
1779/* ##################################### Debug In/Output function ########################################### */
1780/** \ingroup CMSIS_Core_FunctionInterface
1781 \defgroup CMSIS_core_DebugFunctions ITM Functions
1782 \brief Functions that access the ITM debug interface.
1783 @{
1784 */
1785
1786extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
1787#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
1788
1789
1790/** \brief ITM Send Character
1791
1792 The function transmits a character via the ITM channel 0, and
1793 \li Just returns when no debugger is connected that has booked the output.
1794 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
1795
1796 \param [in] ch Character to transmit.
1797
1798 \returns Character to transmit.
1799 */
1800__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
1801{
1802 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
1803 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
1804 {
1805 while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
1806 ITM->PORT[0].u8 = (uint8_t)ch;
1807 }
1808 return (ch);
1809}
1810
1811
1812/** \brief ITM Receive Character
1813
1814 The function inputs a character via the external variable \ref ITM_RxBuffer.
1815
1816 \return Received character.
1817 \return -1 No character pending.
1818 */
1819__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
1820 int32_t ch = -1; /* no character available */
1821
1822 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
1823 ch = ITM_RxBuffer;
1824 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
1825 }
1826
1827 return (ch);
1828}
1829
1830
1831/** \brief ITM Check Character
1832
1833 The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
1834
1835 \return 0 No character available.
1836 \return 1 Character available.
1837 */
1838__STATIC_INLINE int32_t ITM_CheckChar (void) {
1839
1840 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
1841 return (0); /* no character available */
1842 } else {
1843 return (1); /* character available */
1844 }
1845}
1846
1847/*@} end of CMSIS_core_DebugFunctions */
1848
1849
1850
1851
1852#ifdef __cplusplus
1853}
1854#endif
1855
1856#endif /* __CORE_CM4_H_DEPENDANT */
1857
1858#endif /* __CMSIS_GENERIC */
Note: See TracBrowser for help on using the repository browser.