[307] | 1 | /*
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| 2 | * TOPPERS/ASP Kernel
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| 3 | * Toyohashi Open Platform for Embedded Real-Time Systems/
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| 4 | * Advanced Standard Profile Kernel
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| 5 | *
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| 6 | * Copyright (C) 2006-2016 by Embedded and Real-Time Systems Laboratory
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| 7 | * Graduate School of Information Science, Nagoya Univ., JAPAN
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| 8 | * Copyright (C) 2001-2011 by Industrial Technology Institute,
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| 9 | * Miyagi Prefectural Government, JAPAN
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| 10 | *
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| 11 | * ä¸è¨èä½æ¨©è
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| 12 | ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
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| 13 | * ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ã使ç¨ã»è¤è£½ã»æ¹
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| 14 | * å¤ã»åé
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| 15 | å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
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| 16 | * (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
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| 17 | * 権表示ï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
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| 18 | * ã¹ã³ã¼ãä¸ã«å«ã¾ãã¦ãããã¨ï¼
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| 19 | * (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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| 20 | * ç¨ã§ããå½¢ã§åé
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| 21 | å¸ããå ´åã«ã¯ï¼åé
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| 22 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨
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| 23 | * è
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| 24 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
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| 25 | * ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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| 26 | * (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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| 27 | * ç¨ã§ããªãå½¢ã§åé
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| 28 | å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
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| 29 | * ã¨ï¼
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| 30 | * (a) åé
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| 31 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨è
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| 32 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
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| 33 | * ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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| 34 | * (b) åé
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| 35 | å¸ã®å½¢æ
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| 36 | ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSããã¸ã§ã¯ãã«
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| 37 | * å ±åãããã¨ï¼
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| 38 | * (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
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| 39 | * 害ãããï¼ä¸è¨èä½æ¨©è
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| 40 | ããã³TOPPERSããã¸ã§ã¯ããå
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| 41 | 責ãããã¨ï¼
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| 42 | * ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
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| 43 | * ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
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| 44 | ããã³TOPPERSããã¸ã§ã¯ãã
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| 45 | * å
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| 46 | 責ãããã¨ï¼
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| 47 | *
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| 48 | * æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
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| 49 | ã
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| 50 | * ãã³TOPPERSããã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
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| 51 | * ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
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| 52 | * ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ害ã«é¢ãã¦ãï¼ã
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| 53 | * ã®è²¬ä»»ãè² ããªãï¼
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| 54 | *
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| 55 | * @(#) $Id: scif.c 2758 2016-03-10 15:15:26Z ertl-honda $
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| 56 | */
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| 57 |
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| 58 | /*
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| 59 | * RZ/A1ç¨ ç°¡æSIOãã©ã¤ã
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| 60 | */
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| 61 | #include <sil.h>
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| 62 | #include "target_syssvc.h"
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| 63 | #include "rza1.h"
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| 64 | #include "scif.h"
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| 65 |
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| 66 | /*
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| 67 | * åã¬ã¸ã¹ã¿ã®ãªãã»ãã
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| 68 | */
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| 69 | #define REG_SCSMR 0x00 /* ã·ãªã¢ã«ã¢ã¼ãã¬ã¸ã¹ã¿, 16bit */
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| 70 | #define REG_SCBRR 0x04 /* ãããã¬ã¼ãã¬ã¸ã¹ã¿, 8bit */
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| 71 | #define REG_SCSCR 0x08 /* ã·ãªã¢ã«ã³ã³ããã¼ã«ã¬ã¸ã¹ã¿, 16bit */
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| 72 | #define REG_SCFTDR 0x0C /* éä¿¡FIFOãã¼ã¿ã¬ã¸ã¹ã¿, 8bit */
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| 73 | #define REG_SCFSR 0x10 /* ã·ãªã¢ã«ã¹ãã¼ã¿ã¹ã¬ã¸ã¹ã¿, 16bit */
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| 74 | #define REG_SCFRDR 0x14 /* åä¿¡FIFOãã¼ã¿ã¬ã¸ã¹ã¿, 8bit */
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| 75 | #define REG_SCFCR 0x18 /* FIFOã³ã³ããã¼ã«ã¬ã¸ã¹ã¿, 16bit */
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| 76 | #define REG_SCFDR 0x1C /* FIFOãã¼ã¿ã«ã¦ã³ãã¬ã¸ã¹ã¿, 16bit */
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| 77 | #define REG_SCSPTR 0x20 /* ã·ãªã¢ã«ãã¼ãã¬ã¸ã¹ã¿, 16bit */
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| 78 | #define REG_SCLSR 0x24 /* ã©ã¤ã³ã¹ãã¼ã¿ã¹ã¬ã¸ã¹ã¿, 16bit */
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| 79 | #define REG_SCEMR 0x28 /* ã·ãªã¢ã«æ¡å¼µã¢ã¼ãã¬ã¸ã¹ã¿, 16bit */
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| 80 |
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| 81 | /*
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| 82 | * åã¬ã¸ã¹ã¿ã®è¨å®å¤
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| 83 | */
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| 84 | #define SCSMR_SYNC 0x0080 /* 1:ã¯ããã¯åæå¼ã¢ã¼ã */
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| 85 | #define SCSMR_7BIT 0x0040 /* 1:ï¼ããããã¼ã¿ */
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| 86 | #define SCSMR_PARITY 0x0020 /* 1:ããªãã£ä»å */
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| 87 | #define SCSMR_ODD 0x0010 /* 1:å¥æ°ããªã㣠*/
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| 88 | #define SCSMR_2STOP 0x0008 /* 1:ï¼ã¹ãããããã */
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| 89 | #define SCSMR_CKS1 0x0000 /* 00:P1clock / 1 */
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| 90 | #define SCSMR_CKS4 0x0001 /* 01:P1clock / 4 */
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| 91 | #define SCSMR_CKS16 0x0002 /* 10:P1clock / 16 */
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| 92 | #define SCSMR_CKS64 0x0003 /* 11:P1clock / 64 */
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| 93 |
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| 94 | #define SCSCR_TIE 0x0080 /* 1:éä¿¡å²ãè¾¼ã¿è¨±å¯ */
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| 95 | #define SCSCR_RIE 0x0040 /* 1:åä¿¡å²ãè¾¼ã¿,åä¿¡ã¨ã©ã¼å²ãè¾¼ã¿,ãã¬ã¼ã¯å²ãè¾¼ã¿è¨±å¯ */
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| 96 | #define SCSCR_TE 0x0020 /* 1:éä¿¡è¨±å¯ */
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| 97 | #define SCSCR_RE 0x0010 /* 1:åä¿¡è¨±å¯ */
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| 98 | #define SCSCR_REIE 0x0008 /* 1:åä¿¡ã¨ã©ã¼å²ãè¾¼ã¿,ãã¬ã¼ã¯å²ãè¾¼ã¿è¨±å¯ */
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| 99 | #define SCSCR_INTCLK 0x0000 /* 00:å
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| 100 | é¨ã¯ããã¯,CKS端åã¯ç¡è¦ï¼èª¿æ©åæå¼ã®å ´åï¼ */
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| 101 |
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| 102 | #define SCFSR_PER_MASK 0xF000 /* ããªãã£ã¨ã©ã¼æ°æ½åºãã¹ã¯ */
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| 103 | #define SCFSR_PER_SHIFT 12 /* ããªãã£ã¨ã©ã¼æ°æ½åºå³ã·ããæ° */
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| 104 | #define SCFSR_FER_MASK 0x0F00 /* ãã¬ã¼ãã³ã°ã¨ã©ã¼æ°æ½åºãã¹ã¯ */
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| 105 | #define SCFSR_FER_SHIFT 8 /* ãã¬ã¼ãã³ã°ã¨ã©ã¼æ°æ½åºå³ã·ããæ° */
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| 106 | #define SCFSR_ER 0x0080 /* 1:åä¿¡ã¨ã©ã¼ */
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| 107 | #define SCFSR_TEND 0x0040 /* 1:éä¿¡å®äº */
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| 108 | #define SCFSR_TDFE 0x0020 /* 1:éä¿¡FIFOãã¼ã¿ã¨ã³ãã㣠*/
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| 109 | #define SCFSR_BRK 0x0010 /* 1:ãã¬ã¼ã¯æ¤åº */
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| 110 | #define SCFSR_FER 0x0008 /* 1:ãã¬ã¼ãã³ã°ã¨ã©ã¼æ¤åº */
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| 111 | #define SCFSR_PER 0x0004 /* 1:ããªãã£ã¨ã©ã¼æ¤åº */
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| 112 | #define SCFSR_RDF 0x0002 /* 1:åä¿¡FIFOãã¼ã¿ãã« */
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| 113 | #define SCFSR_DR 0x0001 /* 1:åä¿¡ãã¼ã¿ã¬ã㣠*/
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| 114 |
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| 115 | #define SCFCR_RSTRG_15 0x0000 /* RTS#åºåã¢ã¯ãã£ãããªã¬:15 */
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| 116 | #define SCFCR_RSTRG_1 0x0100 /* RTS#åºåã¢ã¯ãã£ãããªã¬:1 */
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| 117 | #define SCFCR_RSTRG_4 0x0200 /* RTS#åºåã¢ã¯ãã£ãããªã¬:4 */
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| 118 | #define SCFCR_RSTRG_6 0x0300 /* RTS#åºåã¢ã¯ãã£ãããªã¬:6 */
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| 119 | #define SCFCR_RSTRG_8 0x0400 /* RTS#åºåã¢ã¯ãã£ãããªã¬:8 */
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| 120 | #define SCFCR_RSTRG_10 0x0500 /* RTS#åºåã¢ã¯ãã£ãããªã¬:10 */
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| 121 | #define SCFCR_RSTRG_12 0x0600 /* RTS#åºåã¢ã¯ãã£ãããªã¬:12 */
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| 122 | #define SCFCR_RSTRG_14 0x0700 /* RTS#åºåã¢ã¯ãã£ãããªã¬:14 */
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| 123 | #define SCFCR_RTRG_1 0x0000 /* åä¿¡FIFOãã¼ã¿æ°ããªã¬:1ï¼èª¿æ©åæå¼ã®å ´åï¼ */
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| 124 | #define SCFCR_RTRG_4 0x0040 /* åä¿¡FIFOãã¼ã¿æ°ããªã¬:4ï¼èª¿æ©åæå¼ã®å ´åï¼ */
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| 125 | #define SCFCR_RTRG_8 0x0080 /* åä¿¡FIFOãã¼ã¿æ°ããªã¬:8ï¼èª¿æ©åæå¼ã®å ´åï¼ */
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| 126 | #define SCFCR_RTRG_14 0x00C0 /* åä¿¡FIFOãã¼ã¿æ°ããªã¬:14ï¼èª¿æ©åæå¼ã®å ´åï¼ */
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| 127 | #define SCFCR_TTRG_8 0x0000 /* éä¿¡FIFOãã¼ã¿æ°ããªã¬:8ï¼èª¿æ©åæå¼ã®å ´åï¼ */
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| 128 | #define SCFCR_TTRG_4 0x0010 /* éä¿¡FIFOãã¼ã¿æ°ããªã¬:4ï¼èª¿æ©åæå¼ã®å ´åï¼ */
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| 129 | #define SCFCR_TTRG_2 0x0020 /* éä¿¡FIFOãã¼ã¿æ°ããªã¬:2ï¼èª¿æ©åæå¼ã®å ´åï¼ */
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| 130 | #define SCFCR_TTRG_0 0x0030 /* éä¿¡FIFOãã¼ã¿æ°ããªã¬:0ï¼èª¿æ©åæå¼ã®å ´åï¼ */
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| 131 | #define SCFCR_MCE 0x0008 /* CTS#,RTS#è¨±å¯ */
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| 132 | #define SCFCR_TFRST 0x0004 /* 1:éä¿¡FIFOãã¼ã¿ã¬ã¸ã¹ã¿ãªã»ãã */
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| 133 | #define SCFCR_RFRST 0x0002 /* 1:åä¿¡FIFOãã¼ã¿ã¬ã¸ã¹ã¿ãªã»ãã */
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| 134 | #define SCFCR_LOOP 0x0001 /* 1:ã«ã¼ãããã¯ãã¹ã */
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| 135 |
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| 136 | #define SCFDR_T_MASK 0x1F00 /* æªéä¿¡ãã¼ã¿æ°æ½åºãã¹ã¯ */
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| 137 | #define SCFDR_T_SHIFT 8 /* æªéä¿¡ãã¼ã¿æ°æ½åºå³ã·ããæ° */
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| 138 | #define SCFDR_R_MASK 0x001F /* åä¿¡ãã¼ã¿æ°æ½åºãã¹ã¯ */
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| 139 | #define SCFDR_R_SHIFT 0 /* åä¿¡ãã¼ã¿æ°æ½åºå³ã·ããæ° */
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| 140 |
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| 141 | #define SCLSR_ORER 0x0001 /* 1:ãªã¼ãã¼ã©ã³ã¨ã©ã¼ */
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| 142 |
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| 143 | #define SCEMR_BGDM 0x0080 /* 1:ãã¼ã¬ã¼ãã¸ã§ãã¬ã¼ã¿åéã¢ã¼ã */
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| 144 | #define SCEMR_ABCS16 0x0000 /* ãããã¬ã¼ãã®16åã®åºæ¬ã¯ããã¯ã§åä½ */
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| 145 | #define SCEMR_ABCS8 0x0001 /* ãããã¬ã¼ãã®8åã®åºæ¬ã¯ããã¯ã§åä½ */
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| 146 |
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| 147 | /*
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| 148 | * ã·ãªã¢ã«I/Oãã¼ãåæåãããã¯ã®å®ç¾©
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| 149 | */
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| 150 | typedef struct sio_port_initialization_block {
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| 151 | uint16_t *port; /* ã·ãªã¢ã«ãã¼ãã®ãã¼ã¹ã¬ã¸ã¹ã¿ */
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| 152 | uint32_t bps_setting; /* ãã¼ã¬ã¼ãã®è¨å®å¤ */
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| 153 | } SIOPINIB;
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| 154 |
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| 155 | /*
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| 156 | * ã·ãªã¢ã«I/Oãã¼ã管çãããã¯ã®å®ç¾©
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| 157 | */
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| 158 | struct sio_port_control_block {
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| 159 | const SIOPINIB *p_siopinib; /* ã·ãªã¢ã«I/Oãã¼ãåæåããã㯠*/
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| 160 | intptr_t exinf; /* æ¡å¼µæ
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| 161 | å ± */
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| 162 | bool_t openflag; /* ãªã¼ãã³æ¸ã¿ãã©ã° */
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| 163 | bool_t sendflag; /* éä¿¡å²è¾¼ã¿ã¤ãã¼ãã«ãã©ã° */
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| 164 | bool_t getready; /* æåãåä¿¡ããç¶æ
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| 165 | */
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| 166 | bool_t putready; /* æåãéä¿¡ã§ããç¶æ
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| 167 | */
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| 168 | bool_t is_initialized; /* ããã¤ã¹åæåæ¸ã¿ãã©ã° */
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| 169 | };
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| 170 |
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| 171 | /*
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| 172 | * ã·ãªã¢ã«I/Oãã¼ãåæåãããã¯
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| 173 | */
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| 174 | static const SIOPINIB siopinib_table[TNUM_SIOP] = {
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| 175 | {
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| 176 | (uint16_t *)(SCIF0_BASE),
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| 177 | UART1_BPS_SETTING,
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| 178 | },
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| 179 | #if TNUM_SIOP > 1
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| 180 | {
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| 181 | (uint16_t *)(SCIF1_BASE),
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| 182 | UART2_BPS_SETTING,
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| 183 | },
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| 184 | #endif /* TNUM_SIOP > 1 */
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| 185 | #if TNUM_SIOP > 2
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| 186 | {
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| 187 | (uint16_t *)(SCIF2_BASE),
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| 188 | UART3_BPS_SETTING,
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| 189 | },
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| 190 | #endif /* TNUM_SIOP > 2 */
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| 191 | #if TNUM_SIOP > 3
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| 192 | {
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| 193 | (uint16_t *)(SCIF3_BASE),
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| 194 | UART4_BPS_SETTING,
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| 195 | },
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| 196 | #endif /* TNUM_SIOP > 3*/
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| 197 | #if TNUM_SIOP > 4
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| 198 | {
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| 199 | (uint16_t *)(SCIF4_BASE),
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| 200 | UART5_BPS_SETTING,
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| 201 | },
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| 202 | #endif /* TNUM_SIOP > 4*/
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| 203 | #if TNUM_SIOP > 5
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| 204 | {
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| 205 | (uint16_t *)(SCIF5_BASE),
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| 206 | UART6_BPS_SETTING,
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| 207 | },
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| 208 | #endif /* TNUM_SIOP > 5*/
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| 209 | #if TNUM_SIOP > 6
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| 210 | {
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| 211 | (uint16_t *)(SCIF6_BASE),
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| 212 | UART7_BPS_SETTING,
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| 213 | },
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| 214 | #endif /* TNUM_SIOP > 6*/
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| 215 | #if TNUM_SIOP > 7
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| 216 | {
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| 217 | (uint16_t *)(SCIF7_BASE),
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| 218 | UART8_BPS_SETTING,
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| 219 | },
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| 220 | #endif /* TNUM_SIOP > 7*/
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| 221 | };
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| 222 |
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| 223 | /*
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| 224 | * ã·ãªã¢ã«I/Oãã¼ã管çãããã¯ã®ã¨ãªã¢
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| 225 | */
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| 226 | static SIOPCB siopcb_table[TNUM_SIOP];
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| 227 |
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| 228 | /*
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| 229 | * ã·ãªã¢ã«I/Oãã¼ãIDãã管çãããã¯ãåãåºãããã®ãã¯ã
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| 230 | */
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| 231 | #define INDEX_SIOP(siopid) ((uint_t)((siopid) - 1))
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| 232 | #define get_siopcb(siopid) (&(siopcb_table[INDEX_SIOP(siopid)]))
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| 233 | #define get_siopinib(siopid) (&(siopinib_table[INDEX_SIOP(siopid)]))
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| 234 |
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| 235 | /*
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| 236 | * 管çãããã¯ã¸ã®ãã¤ã³ã¿ããã·ãªã¢ã«I/Oãã¼ãIDãåãåºãããã®ãã¯ã
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| 237 | */
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| 238 | #define SIOPID(p_siopcb) ((ID)((p_siopcb) - siopcb_table))
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| 239 |
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| 240 | /*
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| 241 | * æåãåä¿¡ãããï¼
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| 242 | */
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| 243 | Inline bool_t scif_getready(SIOPCB *p_siopcb)
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| 244 | {
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| 245 | uint16_t fsrval;
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| 246 | uint16_t lsrval;
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| 247 |
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| 248 | fsrval = sil_reh_mem((uint16_t *)((uint8_t *)p_siopcb->p_siopinib->port + REG_SCFSR));
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| 249 | lsrval = sil_reh_mem((uint16_t *)((uint8_t *)p_siopcb->p_siopinib->port + REG_SCLSR));
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| 250 | if (fsrval & (SCFSR_ER | SCFSR_BRK)) {
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| 251 | fsrval = fsrval & ~(SCFSR_ER | SCFSR_BRK);
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| 252 | sil_wrh_mem((uint16_t *)((uint8_t *)p_siopcb->p_siopinib->port + REG_SCFSR), fsrval);
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| 253 | }
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| 254 | if (lsrval & SCLSR_ORER) {
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| 255 | lsrval = lsrval & ~SCLSR_ORER;
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| 256 | sil_wrh_mem((uint16_t *)((uint8_t *)p_siopcb->p_siopinib->port + REG_SCLSR), lsrval);
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| 257 | }
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| 258 | if (fsrval & SCFSR_RDF) {
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| 259 | return true;
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| 260 | }
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| 261 | return false;
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| 262 | }
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| 263 |
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| 264 | /*
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| 265 | * æåãéä¿¡ã§ãããï¼
|
---|
| 266 | */
|
---|
| 267 | Inline bool_t scif_putready(SIOPCB *p_siopcb)
|
---|
| 268 | {
|
---|
| 269 | uint16_t fsrval;
|
---|
| 270 |
|
---|
| 271 | fsrval = sil_reh_mem((uint16_t *)((uint8_t *)p_siopcb->p_siopinib->port + REG_SCFSR));
|
---|
| 272 | if (fsrval & SCFSR_TDFE) {
|
---|
| 273 | return true;
|
---|
| 274 | }
|
---|
| 275 | return false;
|
---|
| 276 | }
|
---|
| 277 |
|
---|
| 278 | /*
|
---|
| 279 | * åä¿¡ããæåã®ååºã
|
---|
| 280 | */
|
---|
| 281 | Inline bool_t scif_getchar(SIOPCB *p_siopcb, char *rxdata)
|
---|
| 282 | {
|
---|
| 283 | uint16_t fsrval;
|
---|
| 284 | uint16_t lsrval;
|
---|
| 285 | uint8_t read_data;
|
---|
| 286 |
|
---|
| 287 | fsrval = sil_reh_mem((uint16_t *)((uint8_t *)p_siopcb->p_siopinib->port + REG_SCFSR));
|
---|
| 288 | lsrval = sil_reh_mem((uint16_t *)((uint8_t *)p_siopcb->p_siopinib->port + REG_SCLSR));
|
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| 289 | if (fsrval & (SCFSR_ER | SCFSR_BRK)) {
|
---|
| 290 | fsrval = fsrval & ~(SCFSR_ER | SCFSR_BRK);
|
---|
| 291 | sil_wrh_mem((uint16_t *)((uint8_t *)p_siopcb->p_siopinib->port + REG_SCFSR), fsrval);
|
---|
| 292 | }
|
---|
| 293 | if (lsrval & SCLSR_ORER) {
|
---|
| 294 | lsrval = lsrval & ~SCLSR_ORER;
|
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| 295 | sil_wrh_mem((uint16_t *)((uint8_t *)p_siopcb->p_siopinib->port + REG_SCLSR), lsrval);
|
---|
| 296 | }
|
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| 297 | if (fsrval & SCFSR_RDF) {
|
---|
| 298 | read_data = sil_reb_mem((uint8_t *)p_siopcb->p_siopinib->port + REG_SCFRDR);
|
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| 299 | fsrval = fsrval & ~SCFSR_RDF;
|
---|
| 300 | sil_wrh_mem((uint16_t *)((uint8_t *)p_siopcb->p_siopinib->port + REG_SCFSR), fsrval);
|
---|
| 301 | *rxdata = (char)read_data;
|
---|
| 302 | return true;
|
---|
| 303 | }
|
---|
| 304 | return false;
|
---|
| 305 | }
|
---|
| 306 |
|
---|
| 307 | /*
|
---|
| 308 | * éä¿¡ããæåã®æ¸è¾¼ã¿
|
---|
| 309 | */
|
---|
| 310 | Inline void scif_putchar(SIOPCB *p_siopcb, char c)
|
---|
| 311 | {
|
---|
| 312 | sil_wrb_mem((uint8_t *)p_siopcb->p_siopinib->port + REG_SCFTDR, c);
|
---|
| 313 | sil_wrh_mem((uint16_t *)((uint8_t *)p_siopcb->p_siopinib->port + REG_SCFSR), ~(SCFSR_TEND | SCFSR_TDFE));
|
---|
| 314 | }
|
---|
| 315 |
|
---|
| 316 | /*
|
---|
| 317 | * éä¿¡å²è¾¼ã¿è¨±å¯
|
---|
| 318 | */
|
---|
| 319 | Inline void scif_enable_send(SIOPCB *p_siopcb)
|
---|
| 320 | {
|
---|
| 321 | uint16_t scrval;
|
---|
| 322 |
|
---|
| 323 | scrval = sil_reh_mem((uint16_t *)((uint8_t *)p_siopcb->p_siopinib->port + REG_SCSCR));
|
---|
| 324 | scrval |= SCSCR_TIE;
|
---|
| 325 | sil_wrh_mem((uint16_t *)((uint8_t *)p_siopcb->p_siopinib->port + REG_SCSCR), scrval);
|
---|
| 326 | }
|
---|
| 327 |
|
---|
| 328 | /*
|
---|
| 329 | * éä¿¡å²è¾¼ã¿ç¦æ¢
|
---|
| 330 | */
|
---|
| 331 | Inline void scif_disable_send(SIOPCB *p_siopcb)
|
---|
| 332 | {
|
---|
| 333 | uint16_t scrval;
|
---|
| 334 |
|
---|
| 335 | scrval = sil_reh_mem((uint16_t *)((uint8_t *)p_siopcb->p_siopinib->port + REG_SCSCR));
|
---|
| 336 | scrval = scrval & ~SCSCR_TIE;
|
---|
| 337 | sil_wrh_mem((uint16_t *)((uint8_t *)p_siopcb->p_siopinib->port + REG_SCSCR), scrval);
|
---|
| 338 | }
|
---|
| 339 |
|
---|
| 340 |
|
---|
| 341 | /*
|
---|
| 342 | * åä¿¡å²è¾¼ã¿è¨±å¯
|
---|
| 343 | */
|
---|
| 344 | Inline void scif_enable_rcv(SIOPCB *p_siopcb)
|
---|
| 345 | {
|
---|
| 346 | uint16_t scrval;
|
---|
| 347 |
|
---|
| 348 | scrval = sil_reh_mem((uint16_t *)((uint8_t *)p_siopcb->p_siopinib->port + REG_SCSCR));
|
---|
| 349 | scrval |= SCSCR_RIE;
|
---|
| 350 | sil_wrh_mem((uint16_t *)((uint8_t *)p_siopcb->p_siopinib->port + REG_SCSCR), scrval);
|
---|
| 351 | }
|
---|
| 352 |
|
---|
| 353 | /*
|
---|
| 354 | * åä¿¡å²è¾¼ã¿ç¦æ¢
|
---|
| 355 | */
|
---|
| 356 | Inline void
|
---|
| 357 | scif_disable_rcv(SIOPCB *p_siopcb)
|
---|
| 358 | {
|
---|
| 359 | uint16_t scrval;
|
---|
| 360 |
|
---|
| 361 | scrval = sil_reh_mem((uint16_t *)((uint8_t *)p_siopcb->p_siopinib->port + REG_SCSCR));
|
---|
| 362 | scrval = scrval & ~SCSCR_RIE;
|
---|
| 363 | sil_wrh_mem((uint16_t *)((uint8_t *)p_siopcb->p_siopinib->port + REG_SCSCR), scrval);
|
---|
| 364 | }
|
---|
| 365 |
|
---|
| 366 | /*
|
---|
| 367 | * SIOãã©ã¤ãã®åæå
|
---|
| 368 | */
|
---|
| 369 | void scif_initialize(void)
|
---|
| 370 | {
|
---|
| 371 | SIOPCB *p_siopcb;
|
---|
| 372 | uint_t i;
|
---|
| 373 |
|
---|
| 374 | /*
|
---|
| 375 | * ã·ãªã¢ã«I/Oãã¼ã管çãããã¯ã®åæå
|
---|
| 376 | */
|
---|
| 377 | for (p_siopcb = siopcb_table, i = 0; i < TNUM_SIOP; p_siopcb++, i++) {
|
---|
| 378 | p_siopcb->p_siopinib = &(siopinib_table[i]);
|
---|
| 379 | p_siopcb->openflag = false;
|
---|
| 380 | p_siopcb->sendflag = false;
|
---|
| 381 | }
|
---|
| 382 | }
|
---|
| 383 |
|
---|
| 384 |
|
---|
| 385 | /*
|
---|
| 386 | * ãã¼ãã¦ã§ã¢ã®åæåå¦ç
|
---|
| 387 | */
|
---|
| 388 | static int scif_init_siopinib(const SIOPINIB *p_siopinib)
|
---|
| 389 | {
|
---|
| 390 | uint16_t fsrval;
|
---|
| 391 | uint8_t brrval;
|
---|
| 392 |
|
---|
| 393 | fsrval = RZA1_CLK_P1 / (32 * p_siopinib->bps_setting) - 1;
|
---|
| 394 | if (fsrval > 255) return 1;
|
---|
| 395 | brrval = (uint8_t)fsrval;
|
---|
| 396 |
|
---|
| 397 | sil_wrh_mem((uint16_t *)((uint8_t *)p_siopinib->port + REG_SCSCR), 0);
|
---|
| 398 | sil_wrh_mem((uint16_t *)((uint8_t *)p_siopinib->port + REG_SCFCR), SCFCR_TFRST | SCFCR_RFRST);
|
---|
| 399 | (void)sil_reh_mem((uint16_t *)((uint8_t *)p_siopinib->port + REG_SCFSR));
|
---|
| 400 | (void)sil_reh_mem((uint16_t *)((uint8_t *)p_siopinib->port + REG_SCLSR));
|
---|
| 401 | sil_wrh_mem((uint16_t *)((uint8_t *)p_siopinib->port + REG_SCFSR), 0);
|
---|
| 402 | sil_wrh_mem((uint16_t *)((uint8_t *)p_siopinib->port + REG_SCLSR), 0);
|
---|
| 403 | sil_wrh_mem((uint16_t *)((uint8_t *)p_siopinib->port + REG_SCSCR), SCSCR_INTCLK);
|
---|
| 404 | sil_wrh_mem((uint16_t *)((uint8_t *)p_siopinib->port + REG_SCSMR), SCSMR_CKS1); /* 8N1, P1clock/1 */
|
---|
| 405 | sil_wrh_mem((uint16_t *)((uint8_t *)p_siopinib->port + REG_SCEMR), 0);
|
---|
| 406 | sil_wrb_mem((uint8_t *)p_siopinib->port + REG_SCBRR, brrval);
|
---|
| 407 | sil_wrh_mem((uint16_t *)((uint8_t *)p_siopinib->port + REG_SCFCR), SCFCR_RSTRG_15 | SCFCR_RTRG_1 | SCFCR_TTRG_8);
|
---|
| 408 | sil_wrh_mem((uint16_t *)((uint8_t *)p_siopinib->port + REG_SCSCR), SCSCR_TE | SCSCR_RE | SCSCR_INTCLK);
|
---|
| 409 | while (sil_reh_mem((uint16_t *)((uint8_t *)p_siopinib->port + REG_SCFSR)) & SCFSR_RDF) {
|
---|
| 410 | (void)sil_reb_mem((uint8_t *)p_siopinib->port + REG_SCFRDR);
|
---|
| 411 | sil_wrh_mem((uint16_t *)((uint8_t *)p_siopinib->port + REG_SCFSR), ~SCFSR_RDF);
|
---|
| 412 | }
|
---|
| 413 | sil_wrh_mem((uint16_t *)((uint8_t *)p_siopinib->port + REG_SCFSR), 0);
|
---|
| 414 | return 0;
|
---|
| 415 | }
|
---|
| 416 |
|
---|
| 417 |
|
---|
| 418 | /*
|
---|
| 419 | * ã«ã¼ãã«èµ·åæã®ãã¼ãåºåç¨ã®åæå
|
---|
| 420 | */
|
---|
| 421 | void
|
---|
| 422 | scif_init(ID siopid)
|
---|
| 423 | {
|
---|
| 424 | SIOPCB *p_siopcb = get_siopcb(siopid);
|
---|
| 425 | const SIOPINIB *p_siopinib = get_siopinib(siopid);
|
---|
| 426 | /* ãã®æç¹ã§ã¯ãp_siopcb->p_siopinibã¯åæåããã¦ããªã */
|
---|
| 427 |
|
---|
| 428 | if (!(p_siopcb->is_initialized)) {
|
---|
| 429 | scif_init_siopinib(p_siopinib);
|
---|
| 430 | p_siopcb->is_initialized = true;
|
---|
| 431 | }
|
---|
| 432 | }
|
---|
| 433 |
|
---|
| 434 | /*
|
---|
| 435 | * ãã¼ãnããªã¼ãã³æ¸ã¿ãï¼ï¼ãã¼ãIDãå¼æ°ï¼
|
---|
| 436 | */
|
---|
| 437 | bool_t
|
---|
| 438 | scif_openflag_id(ID siopid)
|
---|
| 439 | {
|
---|
| 440 | return(get_siopcb(siopid)->openflag);
|
---|
| 441 | }
|
---|
| 442 |
|
---|
| 443 | /*
|
---|
| 444 | * ãã¼ãnããªã¼ãã³æ¸ã¿ãï¼
|
---|
| 445 | * ï¼ãã·ãªã¢ã«I/Oãã¼ã管çãããã¯ãã®å
|
---|
| 446 | é çªå°ãå¼æ°ï¼
|
---|
| 447 | */
|
---|
| 448 | bool_t
|
---|
| 449 | scif_openflag_cb(SIOPCB *p_siopcb)
|
---|
| 450 | {
|
---|
| 451 | return(p_siopcb->openflag);
|
---|
| 452 | }
|
---|
| 453 |
|
---|
| 454 | /*
|
---|
| 455 | * ãã¼ãIDã®åå¾
|
---|
| 456 | */
|
---|
| 457 | ID
|
---|
| 458 | scif_get_siopid(SIOPCB *p_siopcb)
|
---|
| 459 | {
|
---|
| 460 | return(SIOPID(p_siopcb));
|
---|
| 461 | }
|
---|
| 462 |
|
---|
| 463 | /*
|
---|
| 464 | * ã·ãªã¢ã«I/Oãã¼ãã®ãªã¼ãã³
|
---|
| 465 | */
|
---|
| 466 | SIOPCB *
|
---|
| 467 | scif_opn_por(ID siopid, intptr_t exinf)
|
---|
| 468 | {
|
---|
| 469 | SIOPCB *p_siopcb;
|
---|
| 470 | const SIOPINIB *p_siopinib;
|
---|
| 471 |
|
---|
| 472 | p_siopcb = get_siopcb(siopid);
|
---|
| 473 | p_siopinib = p_siopcb->p_siopinib;
|
---|
| 474 |
|
---|
| 475 | /*
|
---|
| 476 | * ãã¼ãã¦ã§ã¢ã®åæå
|
---|
| 477 | * ãæ¢ã«åæåãã¦ããå ´åã¯ãäºéã«åæåããªãã
|
---|
| 478 | */
|
---|
| 479 | if (!(p_siopcb->is_initialized)) {
|
---|
| 480 | scif_init_siopinib(p_siopinib);
|
---|
| 481 | p_siopcb->is_initialized = true;
|
---|
| 482 | }
|
---|
| 483 |
|
---|
| 484 | p_siopcb->exinf = exinf;
|
---|
| 485 | p_siopcb->getready = p_siopcb->putready = false;
|
---|
| 486 | p_siopcb->openflag = true;
|
---|
| 487 |
|
---|
| 488 | return(p_siopcb);
|
---|
| 489 | }
|
---|
| 490 |
|
---|
| 491 | /*
|
---|
| 492 | * ã·ãªã¢ã«I/Oãã¼ãã®ã¯ãã¼ãº
|
---|
| 493 | */
|
---|
| 494 | void
|
---|
| 495 | scif_cls_por(SIOPCB *p_siopcb)
|
---|
| 496 | {
|
---|
| 497 | sil_wrh_mem(p_siopcb->p_siopinib->port + REG_SCSCR, 0);
|
---|
| 498 | }
|
---|
| 499 |
|
---|
| 500 |
|
---|
| 501 | /*
|
---|
| 502 | * ã·ãªã¢ã«I/Oãã¼ãã¸ã®ãã¼ãªã³ã°ã§ã®åºå
|
---|
| 503 | */
|
---|
| 504 | void
|
---|
| 505 | scif_pol_putc(char c, ID siopid)
|
---|
| 506 | {
|
---|
| 507 | const SIOPINIB *p_siopinib;
|
---|
| 508 | uint16_t fsrval;
|
---|
| 509 | SIL_PRE_LOC;
|
---|
| 510 |
|
---|
| 511 | p_siopinib = get_siopinib(siopid);
|
---|
| 512 |
|
---|
| 513 | while(1) {
|
---|
| 514 | /*
|
---|
| 515 | * ãªã¨ã³ãã©ã³ãã«ãããããå
|
---|
| 516 | ¨å²è¾¼ã¿ããã¯ç¶æ
|
---|
| 517 | ã«ããã
|
---|
| 518 | */
|
---|
| 519 | SIL_LOC_INT();
|
---|
| 520 |
|
---|
| 521 | fsrval = sil_reh_mem((uint16_t *)((uint8_t *)p_siopinib->port + REG_SCFSR));
|
---|
| 522 | if (fsrval & SCFSR_TDFE) {
|
---|
| 523 | sil_wrb_mem((uint8_t *)p_siopinib->port + REG_SCFTDR, c);
|
---|
| 524 | sil_wrh_mem((uint16_t *)((uint8_t *)p_siopinib->port + REG_SCFSR), ~(SCFSR_TEND | SCFSR_TDFE));
|
---|
| 525 | /*
|
---|
| 526 | * ãªã¿ã¼ã³ããåã«å
|
---|
| 527 | ¨å²è¾¼ã¿ããã¯ãã©ã°ãå
|
---|
| 528 | ã®ç¶æ
|
---|
| 529 | ã«æ»ãã
|
---|
| 530 | */
|
---|
| 531 | SIL_UNL_INT();
|
---|
| 532 | return;
|
---|
| 533 | } else {
|
---|
| 534 | /*
|
---|
| 535 | * ããã§å
|
---|
| 536 | ¨å²è¾¼ã¿ããã¯ã解é¤ãã¦ãå²è¾¼ã¿ãåãä»ããã
|
---|
| 537 | */
|
---|
| 538 | SIL_UNL_INT();
|
---|
| 539 | }
|
---|
| 540 | }
|
---|
| 541 | }
|
---|
| 542 |
|
---|
| 543 |
|
---|
| 544 | /*
|
---|
| 545 | * ã·ãªã¢ã«I/Oãã¼ãã¸ã®æåéä¿¡
|
---|
| 546 | */
|
---|
| 547 | bool_t
|
---|
| 548 | scif_snd_chr(SIOPCB *p_siopcb, char c)
|
---|
| 549 | {
|
---|
| 550 | if (scif_putready(p_siopcb)){
|
---|
| 551 | scif_putchar(p_siopcb, c);
|
---|
| 552 | return(true);
|
---|
| 553 | }
|
---|
| 554 | return(false);
|
---|
| 555 | }
|
---|
| 556 |
|
---|
| 557 | /*
|
---|
| 558 | * ã·ãªã¢ã«I/Oãã¼ãããã®æååä¿¡
|
---|
| 559 | */
|
---|
| 560 | int_t
|
---|
| 561 | scif_rcv_chr(SIOPCB *p_siopcb)
|
---|
| 562 | {
|
---|
| 563 | char rxdata;
|
---|
| 564 | if (scif_getready(p_siopcb)) {
|
---|
| 565 | if (scif_getchar(p_siopcb, &rxdata)) {
|
---|
| 566 | return((int_t)rxdata);
|
---|
| 567 | }
|
---|
| 568 | }
|
---|
| 569 | return(-1);
|
---|
| 570 | }
|
---|
| 571 |
|
---|
| 572 | /*
|
---|
| 573 | * ã·ãªã¢ã«I/Oãã¼ãããã®ã³ã¼ã«ããã¯ã®è¨±å¯
|
---|
| 574 | */
|
---|
| 575 | void
|
---|
| 576 | scif_ena_cbr(SIOPCB *p_siopcb, uint_t cbrtn)
|
---|
| 577 | {
|
---|
| 578 | switch (cbrtn) {
|
---|
| 579 | case SIO_RDY_SND:
|
---|
| 580 | scif_enable_send(p_siopcb);
|
---|
| 581 | break;
|
---|
| 582 | case SIO_RDY_RCV:
|
---|
| 583 | scif_enable_rcv(p_siopcb);
|
---|
| 584 | break;
|
---|
| 585 | }
|
---|
| 586 | }
|
---|
| 587 |
|
---|
| 588 | /*
|
---|
| 589 | * ã·ãªã¢ã«I/Oãã¼ãããã®ã³ã¼ã«ããã¯ã®ç¦æ¢
|
---|
| 590 | */
|
---|
| 591 | void
|
---|
| 592 | scif_dis_cbr(SIOPCB *p_siopcb, uint_t cbrtn)
|
---|
| 593 | {
|
---|
| 594 | switch (cbrtn) {
|
---|
| 595 | case SIO_RDY_SND:
|
---|
| 596 | scif_disable_send(p_siopcb);
|
---|
| 597 | break;
|
---|
| 598 | case SIO_RDY_RCV:
|
---|
| 599 | scif_disable_rcv(p_siopcb);
|
---|
| 600 | break;
|
---|
| 601 | }
|
---|
| 602 | }
|
---|
| 603 |
|
---|
| 604 | /*
|
---|
| 605 | * SIOã®å²è¾¼ã¿ãµã¼ãã¹ã«ã¼ãã³
|
---|
| 606 | */
|
---|
| 607 | void
|
---|
| 608 | scif_tx_isr(ID siopid)
|
---|
| 609 | {
|
---|
| 610 | SIOPCB *p_siopcb = get_siopcb(siopid);
|
---|
| 611 |
|
---|
| 612 | if (scif_putready(p_siopcb)) {
|
---|
| 613 | scif_irdy_snd(p_siopcb->exinf);
|
---|
| 614 | }
|
---|
| 615 | }
|
---|
| 616 |
|
---|
| 617 |
|
---|
| 618 | /*
|
---|
| 619 | * SIOã®å²è¾¼ã¿ãµã¼ãã¹ã«ã¼ãã³
|
---|
| 620 | */
|
---|
| 621 | void
|
---|
| 622 | scif_rx_isr(ID siopid)
|
---|
| 623 | {
|
---|
| 624 | SIOPCB *p_siopcb = get_siopcb(siopid);
|
---|
| 625 | while (scif_getready(p_siopcb)) {
|
---|
| 626 | scif_irdy_rcv(p_siopcb->exinf);
|
---|
| 627 | }
|
---|
| 628 | }
|
---|