[302] | 1 |
|
---|
| 2 | TOPPERSããã¸ã§ã¯ã è¨è¨ã¡ã¢
|
---|
| 3 | MPCoreããã³ãããç¨ãããããï¼ãã¼ãã«é¢ããã¡ã¢
|
---|
| 4 |
|
---|
| 5 | ä½æè
|
---|
| 6 | : é«ç°åºç« ï¼åå¤å±å¤§å¦ï¼
|
---|
| 7 | æçµæ´æ°: 2015å¹´8æ9æ¥
|
---|
| 8 |
|
---|
| 9 | âã¡ã¢ã®ä½ç½®ã¥ã
|
---|
| 10 |
|
---|
| 11 | ãã®ã¡ã¢ã¯ï¼MPCoreã¨ï¼ãããç¨ãã以ä¸ã®ãããï¼ãã¼ãã«é¢ãã¦ï¼
|
---|
| 12 | TOPPERSã«ã¼ãã«ããã¼ãã£ã³ã°ããã«ããã£ã¦å¿
|
---|
| 13 | è¦ã¨ãªãäºé
|
---|
| 14 | ãã¾ã¨ãããã®
|
---|
| 15 | ã§ããï¼
|
---|
| 16 |
|
---|
| 17 | ã»ARM11 MPCore
|
---|
| 18 | ã»Core Tile for ARM11 MPCoreï¼CT11MPCoreï¼
|
---|
| 19 | ã»RealView Platform Baseboard for ARM11 MPCore
|
---|
| 20 |
|
---|
| 21 | âç®æ¬¡
|
---|
| 22 |
|
---|
| 23 | ã»åèæç®
|
---|
| 24 | ã»ARM CT11MPcore with RealView Emulation Baseboard
|
---|
| 25 | - ç¨èªã®æ´ç
|
---|
| 26 | - ARM11 MPCoreãã¹ããããã®å²è¾¼ã¿æ©è½
|
---|
| 27 | - CoreTile for ARM11 MPcoreã®å²è¾¼ã¿æ©è½
|
---|
| 28 | - ããã¤ã¹ã¬ã¸ã¹ã¿ã®ã¢ãã¬ã¹
|
---|
| 29 | ã»ARM11 MPCoreå
|
---|
| 30 | èµã¿ã¤ã
|
---|
| 31 | - ã¿ã¤ã
|
---|
| 32 | - ã¦ã©ããããã°
|
---|
| 33 |
|
---|
| 34 | âåèæç®
|
---|
| 35 |
|
---|
| 36 | [1] ARM11 MPCore Processor Technical Reference Manual, 2008
|
---|
| 37 | Revision: r2p0
|
---|
| 38 | DDI0360F_arm11_mpcore_r2p0_trm.pdf
|
---|
| 39 |
|
---|
| 40 | [2] Cortex-A9 MPCore Technical Reference Manual, 2012
|
---|
| 41 | Revision: r4p1
|
---|
| 42 | DDI0407I_cortex_a9_mpcore_r4p1_trm
|
---|
| 43 |
|
---|
| 44 | [3] Core Tile for ARM11 MPCore User Guide
|
---|
| 45 | HBI-0146
|
---|
| 46 | DUI0318F_core_tile_for_arm11_mpcore_ug.pdf
|
---|
| 47 |
|
---|
| 48 | [4] Using a CT11MPCore with the RealView Emulation Baseboard, 2008
|
---|
| 49 | ARM DAI 0152E
|
---|
| 50 | DAI0152E_ct11mpcore_on_emulation_baseboard.pdf
|
---|
| 51 |
|
---|
| 52 | [5] RealView Platform Baseboard for ARM11 MPCore User Guide, 2011
|
---|
| 53 | HBI-0159, HBI-0175, HBI-0176
|
---|
| 54 | DUI0351E_realview_platform_baseboard_for_arm11_mpcore_ug.pdf
|
---|
| 55 |
|
---|
| 56 | âARM CT11MPcore with RealView Emulation Baseboard
|
---|
| 57 |
|
---|
| 58 | âç¨èªã®æ´ç
|
---|
| 59 |
|
---|
| 60 | ã»Emulation Baseboardï¼EBï¼
|
---|
| 61 | - ã³ã¢ãå«ã¾ãªããã¼ã¹ãã¼ã
|
---|
| 62 | - ã¡ã¢ãªãå種ã®ããªãã§ã©ã«ãæè¼ãã
|
---|
| 63 |
|
---|
| 64 | ã»Platform Baseboardï¼PBï¼
|
---|
| 65 | - ã³ã¢ãæè¼ãããã¼ã¹ãã¼ã
|
---|
| 66 | - ã¡ã¢ãªãå種ã®ããªãã§ã©ã«ãæè¼ãã
|
---|
| 67 |
|
---|
| 68 | ã»CoreTileï¼CTï¼
|
---|
| 69 | - Emulation Baseboardï¼EBï¼ã«è¼ããããã®ã³ã¢ãæè¼ããå°åãã¼ã
|
---|
| 70 |
|
---|
| 71 | ã»Core Tile for ARM11 MPCoreï¼CT11MPCoreï¼
|
---|
| 72 | - ARM11 MPCoreã®ãã¹ãããããæè¼ããCoreTile
|
---|
| 73 | + 4ããã»ããµæ§æã®ARM11 MPCore
|
---|
| 74 | + L220 ã¬ãã«2 ãã£ãã·ã¥ã³ã³ããã¼ã©
|
---|
| 75 |
|
---|
| 76 | ã»HDRXï¼HDRYï¼HDRZï¼ä½ã®ç¥ãä¸æï¼
|
---|
| 77 | - Baseboardã¨CoreTileãæ¥ç¶ãã3ã¤ã®ã³ãã¯ã¿ã®å称
|
---|
| 78 |
|
---|
| 79 | ã»DCCï¼Debug Communications Controllerï¼
|
---|
| 80 |
|
---|
| 81 | âARM11 MPCoreãã¹ããããã®å²è¾¼ã¿æ©è½ï¼[3] 4.3.2ç¯ï¼
|
---|
| 82 |
|
---|
| 83 | ã»æè¼ããã¦ããå²è¾¼ã¿ã³ã³ããã¼ã©
|
---|
| 84 | - DICï¼Distributed Interrupt Controllerï¼
|
---|
| 85 | - GICã®å身ã¨ãªãä»æ§ï¼GICv0ã«ç¸å½ï¼
|
---|
| 86 |
|
---|
| 87 | ã»ãããå¤ããã®å²è¾¼ã¿è¦æ±ã©ã¤ã³
|
---|
| 88 | - nIRQ[3:0] ⦠DICã®å²è¾¼ã¿ID31ã«
|
---|
| 89 | - nFIQ[3:0] ⦠åããã»ããµã®FIQã«ç´çµ
|
---|
| 90 | - INT[15:0] ⦠DICã®å²è¾¼ã¿ID32ã47ã«
|
---|
| 91 |
|
---|
| 92 | ã»CPSRä¸ã®Fããããç¡å¹ã«ãã¦ï¼FIQãNMIæ±ãã§ãã
|
---|
| 93 | - ãã¹ããããå²è¾¼ã¿å¶å¾¡ã¬ã¸ã¹ã¿ã§è¨å®
|
---|
| 94 | PERIPHBASEï¼0x3004U
|
---|
| 95 |
|
---|
| 96 | ã»DICã¯32æ¬ã®å²è¾¼ã¿è¦æ±ã©ã¤ã³ãæã¤
|
---|
| 97 | - ãã¼ãã¦ã§ã¢å²è¾¼ã¿ï¼GICã®SPIã«ç¸å½ï¼ã®æ¬æ°ã®ãã¨ã¨æããã
|
---|
| 98 |
|
---|
| 99 | ã»ãã¹ããããã®INT[31:16]ã¯ï¼ãããå
|
---|
| 100 | ã«éãã¦ä½¿ç¨
|
---|
| 101 | - INT[31:29]ï¼L220ããã®å²è¾¼ã¿ï¼3æ¬ï¼
|
---|
| 102 | - INT[17:28]ï¼åããã»ããµããã³SCUããã®å²è¾¼ã¿ï¼12æ¬ï¼PMUIRQ[0:11]
|
---|
| 103 | - INT[16]ï¼æªä½¿ç¨ï¼1æ¬ï¼
|
---|
| 104 |
|
---|
| 105 | âCoreTile for ARM11 MPcoreã®å²è¾¼ã¿æ©è½ï¼[3] 3.4.2ç¯ï¼
|
---|
| 106 |
|
---|
| 107 | ã»3ã¤ã®å²è¾¼ã¿ã¢ã¼ãããµãã¼ã
|
---|
| 108 | - Legacy mode
|
---|
| 109 | - Normal mode with DCC interrupt routing
|
---|
| 110 | - Normal mode without DCC interrupt routing ⦠ããã§ä½¿ã£ã¦ãã
|
---|
| 111 | - EBã·ã¹ãã FPGAã®SYS_PLD_CTL1ã¬ã¸ã¹ã¿ã®INTMODE[2:0]ã§è¨å®ãã
|
---|
| 112 |
|
---|
| 113 | ã»Normal mode without DCC
|
---|
| 114 | - Emulation Baseboardããã®16æ¬ã«å²è¾¼ã¿è¦æ±ã©ã¤ã³ãï¼ãã®ã¾ã¾
|
---|
| 115 | INT[15:0]ã«æ¥ç¶ï¼nIRQ[3:0]ã¨nFIQ[3:0]ã¯ä½¿ããªã
|
---|
| 116 | - å²è¾¼ã¿çªå·ã®ã¢ãµã¤ã³
|
---|
| 117 | INT[0]ï¼ACCI
|
---|
| 118 | INT[1]ï¼EB_TIMER0/1
|
---|
| 119 | INT[2]ï¼EB_TIMER2/3
|
---|
| 120 | INT[3]ï¼USB
|
---|
| 121 | INT[4]ï¼EB_UART0
|
---|
| 122 | INT[5]ï¼EB_UART1
|
---|
| 123 | â¦
|
---|
| 124 | INT[10]ï¼EB_GIC1_nIRQ
|
---|
| 125 | INT[11]ï¼EB_GIC2_nIRQ
|
---|
| 126 | INT[12]ï¼EB_GIC1_nFIQ
|
---|
| 127 | INT[13]ï¼EB_GIC2_nFIQ
|
---|
| 128 | â¦
|
---|
| 129 |
|
---|
| 130 | âããã¤ã¹ã¬ã¸ã¹ã¿ã®ã¢ãã¬ã¹
|
---|
| 131 |
|
---|
| 132 | ã»ããªãã§ã©ã«ãã¼ã¹ã¢ãã¬ã¹ï¼PERIPHBASEï¼ï¼[3] 3.10.1ç¯ï¼
|
---|
| 133 | - 以ä¸ã®ã¬ã¸ã¹ã¿ã®ã¢ãã¬ã¹ã決ãã
|
---|
| 134 | + ARM11 MPCoreã®ã¬ã¸ã¹ã¿
|
---|
| 135 | Snoop Control Unitï¼SCUï¼ã®å¶å¾¡ã¬ã¸ã¹ã¿
|
---|
| 136 | + L220ãã£ãã·ã¥ã³ã³ããã¼ã©ã®ã¬ã¸ã¹ã¿
|
---|
| 137 | + ARM11 MPCoreãã¹ããããã®ã¬ã¸ã¹ã¿
|
---|
| 138 | Test chip PLL control register
|
---|
| 139 | Test chip interrupt control register
|
---|
| 140 | Test chip cluster ID register
|
---|
| 141 | Test chip power status register
|
---|
| 142 | Test chip way map register
|
---|
| 143 | Test chip clock divider register
|
---|
| 144 | - CT11MPCoreã§ã¯ï¼CoreTileä¸ã®ã¸ã£ã³ãã¹ã¤ããã§è¨å®å¯è½
|
---|
| 145 | + ããã©ã«ãã¯ï¼0x1F000000
|
---|
| 146 | - QEMUã§ã¯ï¼0x10100000ã«è¨å®ããã¦ããï¼qemu-2.1.0/hw/arm/realview.cï¼
|
---|
| 147 |
|
---|
| 148 | ã»Emulation Baseboardä¸ã®ãªã½ã¼ã¹ã®ã¢ãã¬ã¹ï¼[4] 5.2ç¯ï¼[5] 4ç« ï¼
|
---|
| 149 | - ãã¼ã¹ã¢ãã¬ã¹ã¯ï¼0x10000000
|
---|
| 150 | - ã¬ã¸ã¹ã¿ãã¢ã³ããã¯ããæ¹æ³
|
---|
| 151 | + base+0x20ã«ï¼0xA05Fãæ¸ãè¾¼ã
|
---|
| 152 | - ã¡ã¢ãªããã
|
---|
| 153 | 0x10000000ã0x10000fff ã·ã¹ãã ã¬ã¸ã¹ã¿
|
---|
| 154 | 0x10001000ã0x10001fff ã·ã¹ãã ã³ã³ããã¼ã©ï¼SP810ï¼
|
---|
| 155 | â¦ä¸ç¥â¦
|
---|
| 156 | 0x10009000ã0x10009fff UART0 ⦠ARM UART PL011 r1p3
|
---|
| 157 | 0x1000a000ã0x1000afff UART1 ⦠ARM UART PL011 r1p3
|
---|
| 158 | 0x1000b000ã0x1000bfff UART2 ⦠ARM UART PL011 r1p3
|
---|
| 159 | 0x1000c000ã0x1000cfff UART3 ⦠ARM UART PL011 r1p3
|
---|
| 160 | â¦ä¸ç¥â¦
|
---|
| 161 | 0x10010000ã0x10010fff Watchdog ⦠ARM WDOG SP805 r2p0
|
---|
| 162 | 0x10011000ã0x10011fff Timer 0&1 ⦠ARM Dual-Timer SP804 r1p2
|
---|
| 163 | 0x10012000ã0x10012fff Timer 2&3 ⦠ARM Dual-Timer SP804 r1p2
|
---|
| 164 | â¦ä¸ç¥â¦
|
---|
| 165 |
|
---|
| 166 | âARM11 MPCoreå
|
---|
| 167 | èµã¿ã¤ãï¼[1] 9.2ç¯ï¼
|
---|
| 168 |
|
---|
| 169 | ARM11 MPCoreã¯ï¼ã³ã¢æ¯ã«ï¼ã¿ã¤ãã¨ã¦ã©ããããã°ãæã¤ï¼ã¦ã©ããããã°
|
---|
| 170 | ã¯ï¼ã¿ã¤ãã¨ãã¦ä½¿ç¨ãããã¨ãã§ããï¼
|
---|
| 171 |
|
---|
| 172 | âã¿ã¤ã
|
---|
| 173 |
|
---|
| 174 | ã¿ã¤ããã¼ãã¬ã¸ã¹ã¿ï¼MPCORE_TMR_LRï¼â¦ 32ããã
|
---|
| 175 | - ã«ã¦ã³ãã¬ã¸ã¹ã¿ã0ã«ãªã£ãæã«ãªãã¼ãããå¤ãä¿æããã¬ã¸ã¹ã¿ï¼
|
---|
| 176 | - ãã®ã¬ã¸ã¹ã¿ã«æ¸ãè¾¼ãã¨ï¼ã«ã¦ã³ãã¬ã¸ã¹ã¿ã«ãæ¸ãè¾¼ã¾ããï¼
|
---|
| 177 |
|
---|
| 178 | ã¿ã¤ãã«ã¦ã³ãã¬ã¸ã¹ã¿ï¼MPCORE_TMR_CNTï¼â¦ 32ããã
|
---|
| 179 | - ãã¦ã³ã«ã¦ã³ã¿ï¼
|
---|
| 180 | - 0ã«ãªã£ããï¼å²è¾¼ã¿ãè¦æ±ããï¼
|
---|
| 181 | - ãªã¼ããªãã¼ãã¢ã¼ãã§ã¯ï¼0ã«ãªã£ããï¼ãã¼ãã¬ã¸ã¹ã¿ã®å¤ã«æ»ãï¼
|
---|
| 182 | - ãã¼ãã¬ã¸ã¹ã¿ãã«ã¦ã³ã¿ã¬ã¸ã¹ã¿ã«æ¸ãè¾¼ãã¨ï¼æ°ããå¤ããã«ã¦ã³ãï¼
|
---|
| 183 |
|
---|
| 184 | ã¿ã¤ãå¶å¾¡ã¬ã¸ã¹ã¿ï¼MPCORE_TMR_CTRLï¼â¦ 32ããã
|
---|
| 185 | [31:16] äºç´ï¼SBZ/RAZï¼
|
---|
| 186 | [15:8] ããªã¹ã±ã¼ã©
|
---|
| 187 | [7:3] äºç´ï¼SBZ/RAZï¼
|
---|
| 188 | [2] å²è¾¼ã¿ã¤ãã¼ãã«
|
---|
| 189 | [1] ãªã¼ããªãã¼ã
|
---|
| 190 | [0] ã¿ã¤ãã¤ãã¼ãã«
|
---|
| 191 |
|
---|
| 192 | ã¿ã¤ãå²è¾¼ã¿ç¶æ
|
---|
| 193 | ã¬ã¸ã¹ã¿ï¼MPCORE_TMR_ISRï¼â¦ 32ããã
|
---|
| 194 | [31:1] äºç´
|
---|
| 195 | [0] ã¤ãã³ããã©ã°
|
---|
| 196 | - ã«ã¦ã³ã¿ã¬ã¸ã¹ã¿ã0ã«ãªã£ãæã«ã»ãããããï¼
|
---|
| 197 | - 1ãæ¸ãè¾¼ãã¨ã¯ãªã¢ãããï¼
|
---|
| 198 |
|
---|
| 199 | âã¦ã©ããããã°
|
---|
| 200 |
|
---|
| 201 | ã¦ã©ããããã°ãã¼ãã¬ã¸ã¹ã¿ï¼MPCORE_WDG_LRï¼â¦ 32ããã
|
---|
| 202 | - ã«ã¦ã³ãã¬ã¸ã¹ã¿ã0ã«ãªã£ãæã«ãªãã¼ãããå¤ãä¿æããã¬ã¸ã¹ã¿ï¼
|
---|
| 203 | - ãã®ã¬ã¸ã¹ã¿ã«æ¸ãè¾¼ãã¨ï¼ã«ã¦ã³ãã¬ã¸ã¹ã¿ã«ãæ¸ãè¾¼ã¾ããï¼
|
---|
| 204 |
|
---|
| 205 | ã¦ã©ããããã°ã«ã¦ã³ãã¬ã¸ã¹ã¿ï¼MPCORE_WDG_CNTï¼â¦ 32ããã
|
---|
| 206 | - ãã¦ã³ã«ã¦ã³ã¿ï¼
|
---|
| 207 | ã+ ã¿ã¤ãã¢ã¼ã
|
---|
| 208 | - 0ã«ãªã£ããï¼å²è¾¼ã¿ãè¦æ±ããï¼
|
---|
| 209 | - ãªã¼ããªãã¼ãã¢ã¼ãã§ã¯ï¼0ã«ãªã£ããï¼ãã¼ãã¬ã¸ã¹ã¿ã®å¤ã«æ»ãï¼
|
---|
| 210 | - ãã¼ãã¬ã¸ã¹ã¿ãã«ã¦ã³ã¿ã¬ã¸ã¹ã¿ã«æ¸ãè¾¼ãã¨ï¼æ°ããå¤ããã«ã¦ã³ãï¼
|
---|
| 211 | ã+ ã¦ã©ããããã°ã¢ã¼ã
|
---|
| 212 | - 0ã«ãªã£ããï¼ãªã»ãããè¦æ±ããï¼
|
---|
| 213 | - ãã®ã¬ã¸ã¹ã¿ã¸ã¯æ¸ãè¾¼ããªãï¼
|
---|
| 214 |
|
---|
| 215 | ã¦ã©ããããã°å¶å¾¡ã¬ã¸ã¹ã¿ï¼MPCORE_WDG_CTRLï¼â¦ 32ããã
|
---|
| 216 | [31:16] äºç´ï¼SBZ/RAZï¼
|
---|
| 217 | [15:8] ããªã¹ã±ã¼ã©
|
---|
| 218 | [7:4] äºç´ï¼SBZ/RAZï¼
|
---|
| 219 | [3] ã¦ã©ããããã°ã¢ã¼ãï¼ããã«0ãæ¸ãã¦ãå¤æ´ã§ããªãï¼
|
---|
| 220 | [2] å²è¾¼ã¿ã¤ãã¼ãã«
|
---|
| 221 | [1] ãªã¼ããªãã¼ã
|
---|
| 222 | [0] ã¦ã©ããããã°ã¤ãã¼ãã«
|
---|
| 223 |
|
---|
| 224 | ã¦ã©ããããã°å²è¾¼ã¿ç¶æ
|
---|
| 225 | ã¬ã¸ã¹ã¿ï¼MPCORE_WDG_ISRï¼â¦ 32ããã
|
---|
| 226 | [31:1] äºç´
|
---|
| 227 | [0] ã¤ãã³ããã©ã°
|
---|
| 228 | - ã¿ã¤ãã¢ã¼ãã§ï¼ã«ã¦ã³ã¿ã¬ã¸ã¹ã¿ã0ã«ãªã£ãæã«ã»ããï¼
|
---|
| 229 | - 1ãæ¸ãè¾¼ãã¨ã¯ãªã¢ï¼
|
---|
| 230 |
|
---|
| 231 | ã¦ã©ããããã°ãªã»ããç¶æ
|
---|
| 232 | ã¬ã¸ã¹ã¿ï¼MPCORE_WDG_RSTï¼â¦ 32ããã
|
---|
| 233 | [31:1] äºç´
|
---|
| 234 | [0] ãªã»ãããã©ã°
|
---|
| 235 | - ã¦ã©ããããã°ã¢ã¼ãã§ï¼ã«ã¦ã³ã¿ã¬ã¸ã¹ã¿ã0ã«ãªã£ãæã«
|
---|
| 236 | ã»ããï¼
|
---|
| 237 | - 1ãæ¸ãè¾¼ãã¨ã¯ãªã¢ï¼
|
---|
| 238 |
|
---|
| 239 | ã¦ã©ããããã°ãã£ã¹ã¨ã¼ãã«ã¬ã¸ã¹ã¿ï¼MPCORE_WDG_DISï¼â¦ 32ããã
|
---|
| 240 | 0x12345678ã¨0x87654321ããã®é ã§æ¸ãã¨ï¼ã¦ã©ããããã°ããã£ã¹ã¨ã¼
|
---|
| 241 | ãã«ãããï¼å¶å¾¡ã¬ã¸ã¹ã¿ä¸ã®ã¦ã©ããããã°ã¢ã¼ããããã0ã«ãªãï¼ï¼
|
---|
| 242 |
|
---|
| 243 | 以ä¸
|
---|