1 | /*
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2 | * TOPPERS/ASP Kernel
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3 | * Toyohashi Open Platform for Embedded Real-Time Systems/
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4 | * Advanced Standard Profile Kernel
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5 | *
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6 | * Copyright (C) 2000-2003 by Embedded and Real-Time Systems Laboratory
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7 | * Toyohashi Univ. of Technology, JAPAN
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8 | * Copyright (C) 2006-2015 by Embedded and Real-Time Systems Laboratory
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9 | * Graduate School of Information Science, Nagoya Univ., JAPAN
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10 | *
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11 | * ä¸è¨èä½æ¨©è
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12 | ã¯ï¼ä»¥ä¸ã®(1)ã(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
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13 | * ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ã使ç¨ã»è¤è£½ã»æ¹
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14 | * å¤ã»åé
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15 | å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
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16 | * (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
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17 | * 権表示ï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
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18 | * ã¹ã³ã¼ãä¸ã«å«ã¾ãã¦ãããã¨ï¼
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19 | * (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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20 | * ç¨ã§ããå½¢ã§åé
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21 | å¸ããå ´åã«ã¯ï¼åé
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22 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨
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23 | * è
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24 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
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25 | * ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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26 | * (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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27 | * ç¨ã§ããªãå½¢ã§åé
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28 | å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
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29 | * ã¨ï¼
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30 | * (a) åé
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31 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨è
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32 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
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33 | * ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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34 | * (b) åé
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35 | å¸ã®å½¢æ
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36 | ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSããã¸ã§ã¯ãã«
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37 | * å ±åãããã¨ï¼
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38 | * (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
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39 | * 害ãããï¼ä¸è¨èä½æ¨©è
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40 | ããã³TOPPERSããã¸ã§ã¯ããå
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41 | 責ãããã¨ï¼
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42 | * ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
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43 | * ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
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44 | ããã³TOPPERSããã¸ã§ã¯ãã
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45 | * å
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46 | 責ãããã¨ï¼
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47 | *
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48 | * æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
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49 | ã
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50 | * ãã³TOPPERSããã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
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51 | * ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
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52 | * ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ害ã«é¢ãã¦ãï¼ã
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53 | * ã®è²¬ä»»ãè² ããªãï¼
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54 | *
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55 | * $Id: core_kernel_impl.c 430 2015-08-08 11:38:46Z ertl-hiro $
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56 | */
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57 |
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58 | /*
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59 | * ã«ã¼ãã«ã®ã³ã¢ä¾åé¨ï¼ARMç¨ï¼
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60 | */
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61 |
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62 | #include "kernel_impl.h"
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63 | #include "check.h"
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64 | #include "task.h"
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65 | #include "arm.h"
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66 |
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67 | /*
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68 | * ã³ã³ããã¹ãåç
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69 | §ã®ããã®å¤æ°
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70 | */
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71 | uint32_t excpt_nest_count; /* ä¾å¤ãã¹ãã«ã¦ã³ã */
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72 |
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73 | /*
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74 | * MMUé¢é£ã®æä½ï¼VMSAï¼
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75 | */
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76 | #ifdef USE_ARM_MMU
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77 |
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78 | #define D0_CLIENT 0x01U /* å¤æãã¼ãã«ã«å¾ã£ã¦ãã¡ã¤ã³0ã«ã¢ã¯ã»ã¹ */
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79 | #define USE_ASID 1 /* 使ç¨ããASID */
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80 |
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81 | /*
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82 | * ã»ã¯ã·ã§ã³ãã¼ãã«
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83 | */
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84 | static uint32_t section_table[ARM_SECTION_TABLE_ENTRY]
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85 | __attribute__((aligned(ARM_SECTION_TABLE_ALIGN)));
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86 |
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87 | /*
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88 | * MMUã®ã»ã¯ã·ã§ã³ãã¼ãã«ã¨ã³ããªã®è¨å®
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89 | */
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90 | Inline void
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91 | config_section_entry(ARM_MMU_CONFIG *p_ammuc)
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92 | {
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93 | uint32_t vaddr = p_ammuc->vaddr;
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94 | uint32_t paddr = p_ammuc->paddr;
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95 | uint32_t size = p_ammuc->size;
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96 | uint_t i;
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97 |
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98 | while (size > 0) {
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99 | #ifdef USE_ARM_SSECTION
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100 | if (size >= ARM_SSECTION_SIZE && (vaddr % ARM_SSECTION_SIZE) == 0) {
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101 | for (i = 0; i < 16; i++) {
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102 | section_table[vaddr / ARM_SECTION_SIZE] = paddr
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103 | |ARM_MMU_DSCR1_SSECTION|p_ammuc->attr;
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104 | vaddr += ARM_SECTION_SIZE;
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105 | }
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106 | paddr += ARM_SSECTION_SIZE;
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107 | size -= ARM_SSECTION_SIZE;
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108 | }
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109 | else {
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110 | #endif /* USE_ARM_SSECTION */
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111 | section_table[vaddr / ARM_SECTION_SIZE] = paddr
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112 | |ARM_MMU_DSCR1_SECTION|p_ammuc->attr;
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113 | vaddr += ARM_SECTION_SIZE;
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114 | paddr += ARM_SECTION_SIZE;
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115 | size -= ARM_SECTION_SIZE;
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116 | #ifdef USE_ARM_SSECTION
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117 | }
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118 | #endif /* USE_ARM_SSECTION */
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119 | }
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120 | }
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121 |
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122 | /*
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123 | * MMUã®åæå
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124 | */
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125 | void
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126 | arm_mmu_initialize(void)
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127 | {
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128 | uint32_t reg;
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129 | uint_t i;
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130 |
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131 | /*
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132 | * MMUã®ã»ã¯ã·ã§ã³ãã¼ãã«ã®è¨å®
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133 | */
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134 | for (i = 0; i < ARM_SECTION_TABLE_ENTRY; i++) {
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135 | section_table[i] = ARM_MMU_DSCR1_FAULT;
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136 | }
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137 | for (i = 0; i < arm_tnum_memory_area; i++) {
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138 | config_section_entry(&(arm_memory_area[i]));
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139 | }
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140 |
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141 | /*
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142 | * TTBR0ãç¨ããããã«æå®ï¼ARMv6以éï¼
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143 | */
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144 | #if __TARGET_ARCH_ARM >= 6
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145 | CP15_WRITE_TTBCR(0U);
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146 | #endif /* __TARGET_ARCH_ARM >= 6 */
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147 |
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148 | /*
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149 | * å¤æãã¼ãã«ã¨ãã¦ï¼section_tableã使ç¨ããï¼
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150 | */
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151 | reg = ((uint32_t) &(section_table[0])) | TTBR_CONFIG;
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152 | CP15_WRITE_TTBR0(reg);
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153 |
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154 | /*
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155 | * ãã¡ã¤ã³ã¢ã¯ã»ã¹å¶å¾¡ã®è¨å®
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156 | */
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157 | CP15_WRITE_DACR(D0_CLIENT);
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158 |
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159 | /*
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160 | * ASIDã®è¨å®
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161 | */
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162 | #if __TARGET_ARCH_ARM >= 6
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163 | CP15_WRITE_CONTEXTIDR(USE_ASID);
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164 | #endif /* __TARGET_ARCH_ARM >= 6 */
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165 |
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166 | /*
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167 | * TLBå
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168 | ¨ä½ã®ç¡å¹å
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169 | */
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170 | arm_invalidate_tlb();
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171 |
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172 | /*
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173 | * MMUãæå¹ã«ããï¼ARMv6ã§ã¯ï¼æ¡å¼µãã¼ã¸ãã¼ãã«è¨å®ã使ãï¼ãµã
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174 | * ãã¼ã¸ã¯ä½¿ããªãï¼ããã«è¨å®ããï¼
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175 | */
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176 | CP15_READ_SCTLR(reg);
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177 | #if __TARGET_ARCH_ARM == 6
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178 | reg |= (CP15_SCTLR_MMU|CP15_SCTLR_EXTPAGE);
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179 | #else /* __TARGET_ARCH_ARM == 6 */
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180 | reg |= CP15_SCTLR_MMU;
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181 | #endif /* __TARGET_ARCH_ARM == 6 */
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182 | CP15_WRITE_SCTLR(reg);
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183 | inst_sync_barrier();
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184 | }
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185 |
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186 | #endif /* USE_ARM_MMU */
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187 |
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188 | /*
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189 | * ã³ã¢ä¾åã®åæå
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190 | */
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191 | void
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192 | core_initialize(void)
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193 | {
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194 | /*
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195 | * ã«ã¼ãã«èµ·åæã¯éã¿ã¹ã¯ã³ã³ããã¹ãã¨ãã¦åä½ãããããã«ï¼ä¾å¤
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196 | * ã®ãã¹ãåæ°ã1ã«åæåããï¼
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197 | */
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198 | excpt_nest_count = 1U;
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199 |
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200 | /*
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201 | * ããã©ã¼ãã³ã¹ã¢ãã¿ã®åæå
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202 | */
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203 | #if defined(USE_ARM_PM_HIST) && __TARGET_ARCH_ARM == 7
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204 | arm_init_pmcnt();
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205 | #endif /* defined(USE_ARM_PM_HIST) && __TARGET_ARCH_ARM == 7 */
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206 | }
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207 |
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208 | /*
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209 | * ã³ã¢ä¾åã®çµäºå¦ç
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210 | */
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211 | void
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212 | core_terminate(void)
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213 | {
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214 | }
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215 |
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216 | /*
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217 | * CPUä¾å¤ã®çºçç¶æ³ã®ãã°åºå
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218 | */
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219 | #ifndef OMIT_XLOG_SYS
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220 |
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221 | /*
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222 | * CPUä¾å¤ãã³ãã©ã®ä¸ããï¼CPUä¾å¤æ
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223 | å ±ãã¤ã³ã¿ï¼p_excinfï¼ãå¼æ°ã¨ã
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224 | * ã¦å¼ã³åºããã¨ã§ï¼CPUä¾å¤ã®çºçç¶æ³ãã·ã¹ãã ãã°ã«åºåããï¼
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225 | */
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226 | void
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227 | xlog_sys(void *p_excinf)
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228 | {
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229 | syslog_4(LOG_EMERG, "pc = %08x, cpsr = %08x, lr = %08x, r12 = %08x",
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230 | ((T_EXCINF *)(p_excinf))->pc, ((T_EXCINF *)(p_excinf))->cpsr,
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231 | ((T_EXCINF *)(p_excinf))->lr, ((T_EXCINF *)(p_excinf))->r12);
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232 | syslog_4(LOG_EMERG, "r0 = %08x, r1 = %08x, r2 = %08x, r3 = %08x",
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233 | ((T_EXCINF *)(p_excinf))->r0, ((T_EXCINF *)(p_excinf))->r1,
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234 | ((T_EXCINF *)(p_excinf))->r2, ((T_EXCINF *)(p_excinf))->r3);
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235 | syslog_2(LOG_EMERG, "nest_count = %d, intpri = %d",
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236 | ((T_EXCINF *)(p_excinf))->nest_count,
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237 | ((T_EXCINF *)(p_excinf))->intpri);
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238 | }
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239 |
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240 | /*
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241 | * ããªãã§ããï¼ãã¼ã¿ã¢ãã¼ããçºçããç¶æ³ï¼ç¶æ
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242 | ã¨ã¢ãã¬ã¹ï¼ãã·ã¹
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243 | * ãã ãã°ã«åºåããï¼
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244 | */
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245 | void
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246 | xlog_fsr(uint32_t fsr, uint32_t far)
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247 | {
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248 | char *status;
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249 |
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250 | switch (fsr & CP15_FSR_FS_MASK) {
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251 | case CP15_FSR_FS_ALIGNMENT:
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252 | status = "alignment fault";
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253 | break;
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254 | case CP15_FSR_FS_TRANSLATION1:
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255 | status = "translation fault (1st level)";
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256 | break;
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257 | case CP15_FSR_FS_TRANSLATION2:
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258 | status = "translation fault (2nd level)";
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259 | break;
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260 | case CP15_FSR_FS_PERMISSION1:
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261 | status = "permission fault (1st level)";
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262 | break;
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263 | case CP15_FSR_FS_PERMISSION2:
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264 | status = "permission fault (2nd level)";
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265 | break;
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266 | default:
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267 | status = "other fault";
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268 | break;
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269 | }
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270 | syslog_2(LOG_EMERG, "Fault status: 0x%04x (%s)", fsr, status);
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271 | syslog_1(LOG_EMERG, "Fault address: 0x%08x", far);
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272 | }
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273 |
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274 | #endif /* OMIT_XLOG_SYS */
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275 |
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276 | /*
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277 | * æªå®ç¾©ã®å²è¾¼ã¿ãå
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278 | ¥ã£ãå ´åã®å¦ç
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279 | */
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280 | #ifndef OMIT_DEFAULT_INT_HANDLER
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281 |
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282 | void
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283 | default_int_handler(void)
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284 | {
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285 | syslog_0(LOG_EMERG, "Unregistered interrupt occurs.");
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286 | ext_ker();
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287 | }
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288 |
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289 | #endif /* OMIT_DEFAULT_INT_HANDLER */
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290 |
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291 | /*
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292 | * æªå®ç¾©ã®ä¾å¤ãå
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293 | ¥ã£ãå ´åã®å¦ç
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294 | */
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295 | #ifndef OMIT_DEFAULT_EXC_HANDLER
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296 |
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297 | void
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298 | default_exc_handler(void *p_excinf, EXCNO excno)
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299 | {
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300 | #ifdef OMIT_XLOG_SYS
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301 | syslog_1(LOG_EMERG, "Unregistered exception %d occurs.", excno);
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302 | #else /* OMIT_XLOG_SYS */
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303 | switch (excno) {
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304 | case EXCNO_UNDEF:
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305 | syslog_0(LOG_EMERG, "Undefined Instruction exception occurs.");
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306 | break;
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307 | case EXCNO_SVC:
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308 | syslog_0(LOG_EMERG, "Supervisor Call exception occurs.");
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309 | break;
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310 | case EXCNO_PABORT:
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311 | syslog_0(LOG_EMERG, "Prefetch Abort exception occurs.");
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312 | break;
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313 | case EXCNO_DABORT:
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314 | syslog_0(LOG_EMERG, "Data Abort exception occurs.");
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315 | break;
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316 | case EXCNO_IRQ:
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317 | syslog_0(LOG_EMERG, "IRQ exception occurs.");
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318 | break;
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319 | case EXCNO_FIQ:
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320 | syslog_0(LOG_EMERG, "FIQ exception occurs.");
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321 | break;
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322 | }
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323 | xlog_sys(p_excinf);
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324 |
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325 | if (excno == EXCNO_PABORT || excno == EXCNO_DABORT) {
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326 | uint32_t fsr, far;
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327 |
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328 | #if __TARGET_ARCH_ARM >= 6
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329 | if (excno == EXCNO_PABORT) {
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330 | CP15_READ_IFSR(fsr);
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331 | CP15_READ_IFAR(far);
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332 | }
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333 | else {
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334 | CP15_READ_DFSR(fsr);
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335 | CP15_READ_DFAR(far);
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336 | }
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337 | #else /* __TARGET_ARCH_ARM >= 6 */
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338 | CP15_READ_FSR(fsr);
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339 | CP15_READ_FAR(far);
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340 | #endif /* __TARGET_ARCH_ARM >= 6 */
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341 |
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342 | xlog_fsr(fsr, far);
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343 | }
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344 | #endif /* OMIT_XLOG_SYS */
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345 | ext_ker();
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346 | }
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347 |
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348 | #endif /* OMIT_DEFAULT_EXC_HANDLER */
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