1 | /*
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2 | * TOPPERS Software
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3 | * Toyohashi Open Platform for Embedded Real-Time Systems
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4 | *
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5 | * Copyright (C) 2000-2003 by Embedded and Real-Time Systems Laboratory
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6 | * Toyohashi Univ. of Technology, JAPAN
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7 | * Copyright (C) 2006-2015 by Embedded and Real-Time Systems Laboratory
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8 | * Graduate School of Information Science, Nagoya Univ., JAPAN
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9 | *
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10 | * ä¸è¨èä½æ¨©è
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11 | ã¯ï¼ä»¥ä¸ã®(1)ã(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
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12 | * ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ã使ç¨ã»è¤è£½ã»æ¹
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13 | * å¤ã»åé
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14 | å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
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15 | * (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
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16 | * 権表示ï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
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17 | * ã¹ã³ã¼ãä¸ã«å«ã¾ãã¦ãããã¨ï¼
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18 | * (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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19 | * ç¨ã§ããå½¢ã§åé
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20 | å¸ããå ´åã«ã¯ï¼åé
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21 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨
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22 | * è
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23 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
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24 | * ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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25 | * (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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26 | * ç¨ã§ããªãå½¢ã§åé
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27 | å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
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28 | * ã¨ï¼
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29 | * (a) åé
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30 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨è
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31 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
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32 | * ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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33 | * (b) åé
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34 | å¸ã®å½¢æ
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35 | ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSããã¸ã§ã¯ãã«
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36 | * å ±åãããã¨ï¼
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37 | * (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
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38 | * 害ãããï¼ä¸è¨èä½æ¨©è
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39 | ããã³TOPPERSããã¸ã§ã¯ããå
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40 | 責ãããã¨ï¼
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41 | * ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
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42 | * ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
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43 | ããã³TOPPERSããã¸ã§ã¯ãã
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44 | * å
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45 | 責ãããã¨ï¼
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46 | *
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47 | * æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
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48 | ã
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49 | * ãã³TOPPERSããã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
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50 | * ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
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51 | * ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ害ã«é¢ãã¦ãï¼ã
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52 | * ã®è²¬ä»»ãè² ããªãï¼
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53 | *
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54 | * $Id: arm.h 430 2015-08-08 11:38:46Z ertl-hiro $
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55 | */
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56 |
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57 | /*
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58 | * ARMã³ã¢ãµãã¼ãã¢ã¸ã¥ã¼ã«
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59 | */
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60 |
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61 | #ifndef TOPPERS_ARM_H
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62 | #define TOPPERS_ARM_H
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63 |
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64 | #include <t_stddef.h>
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65 |
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66 | /*
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67 | * ARMã³ã¢ã®ç¹æ®å½ä»¤ã®ã¤ã³ã©ã¤ã³é¢æ°å®ç¾©
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68 | */
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69 | #ifndef TOPPERS_MACRO_ONLY
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70 | #include "arm_insn.h"
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71 | #endif /* TOPPERS_MACRO_ONLY */
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72 |
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73 | /*
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74 | * ARMä¾å¤ãã¯ã¿
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75 | */
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76 | #define RESET_VECTOR UINT_C(0x00)
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77 | #define UNDEF_VECTOR UINT_C(0x04)
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78 | #define SVC_VECTOR UINT_C(0x08)
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79 | #define PABORT_VECTOR UINT_C(0x0c)
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80 | #define DABORT_VECTOR UINT_C(0x10)
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81 | #define IRQ_VECTOR UINT_C(0x18)
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82 | #define FIQ_VECTOR UINT_C(0x1c)
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83 |
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84 | /*
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85 | * ARMä¾å¤ãã¯ã¿çªå·
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86 | */
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87 | #define RESET_NUMBER UINT_C(0)
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88 | #define UNDEF_NUMBER UINT_C(1)
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89 | #define SVC_NUMBER UINT_C(2)
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90 | #define PABORT_NUMBER UINT_C(3)
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91 | #define DABORT_NUMBER UINT_C(4)
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92 | #define IRQ_NUMBER UINT_C(6)
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93 | #define FIQ_NUMBER UINT_C(7)
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94 |
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95 | /*
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96 | * CPSRã®å²è¾¼ã¿ç¦æ¢ããã
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97 | */
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98 | #define CPSR_INT_MASK UINT_C(0xc0)
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99 | #define CPSR_IRQ_BIT UINT_C(0x80)
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100 | #define CPSR_FIQ_BIT UINT_C(0x40)
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101 |
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102 | /*
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103 | * CPSRã®Thumbããã
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104 | */
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105 | #define CPSR_THUMB_BIT UINT_C(0x20)
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106 |
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107 | /*
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108 | * CPSRã®ã¢ã¼ãããã
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109 | */
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110 | #define CPSR_MODE_MASK UINT_C(0x1f)
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111 | #define CPSR_USER_MODE UINT_C(0x10)
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112 | #define CPSR_FIQ_MODE UINT_C(0x11)
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113 | #define CPSR_IRQ_MODE UINT_C(0x12)
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114 | #define CPSR_SVC_MODE UINT_C(0x13)
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115 | #define CPSR_ABT_MODE UINT_C(0x17)
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116 | #define CPSR_UND_MODE UINT_C(0x1b)
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117 | #define CPSR_SYS_MODE UINT_C(0x1f)
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118 |
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119 | /*
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120 | * CP15ã®ã·ã¹ãã å¶å¾¡ã¬ã¸ã¹ã¿ï¼SCTLRï¼ã®è¨å®å¤
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121 | *
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122 | * ARMv7ã§ã¯ï¼CP15_SCTLR_EXTPAGEã¯å¸¸ã«1ã«ãªã£ã¦ããï¼
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123 | */
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124 | #if __TARGET_ARCH_ARM == 6
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125 | #define CP15_SCTLR_EXTPAGE UINT_C(0x00800000)
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126 | #endif /* __TARGET_ARCH_ARM == 6 */
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127 | #define CP15_SCTLR_VECTOR UINT_C(0x00002000)
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128 | #define CP15_SCTLR_ICACHE UINT_C(0x00001000)
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129 | #define CP15_SCTLR_DCACHE UINT_C(0x00000004)
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130 | #define CP15_SCTLR_MMU UINT_C(0x00000001)
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131 |
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132 | /*
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133 | * CP15ã®ãã©ã¼ã«ãç¶æ
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134 | ã¬ã¸ã¹ã¿ã®åç
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135 | §å¤
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136 | */
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137 | #define CP15_FSR_FS_MASK UINT_C(0x0000040f)
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138 | #define CP15_FSR_FS_ALIGNMENT UINT_C(0x00000001)
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139 | #define CP15_FSR_FS_TRANSLATION1 UINT_C(0x00000005)
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140 | #define CP15_FSR_FS_TRANSLATION2 UINT_C(0x00000007)
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141 | #define CP15_FSR_FS_PERMISSION1 UINT_C(0x0000000d)
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142 | #define CP15_FSR_FS_PERMISSION2 UINT_C(0x0000000f)
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143 |
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144 | /*
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145 | * CP15ã®ããã©ã¼ãã³ã¹ã¢ãã¿å¶å¾¡ã¬ã¸ã¹ã¿ï¼PMCRï¼ã®è¨å®å¤
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146 | */
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147 | #define CP15_PMCR_ALLCNTR_ENABLE UINT_C(0x01)
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148 | #define CP15_PMCR_PMCCNTR_DIVIDER UINT_C(0x08)
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149 |
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150 | /*
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151 | * CP15ã®ããã©ã¼ãã³ã¹ã¢ãã¿ã«ã¦ã³ãã¤ãã¼ãã«ã»ããã¬ã¸ã¹ã¿ï¼PMCNTENSETï¼
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152 | * ã®è¨å®å¤
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153 | */
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154 | #define CP15_PMCNTENSET_CCNTR_ENABLE UINT_C(0x80000000)
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155 |
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156 | /*
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157 | * CP15ã®å¤æãã¼ãã«ãã¼ã¹ã¬ã¸ã¹ã¿ï¼TTBRï¼ã®è¨å®å¤
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158 | */
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159 | #define CP15_TTBR_RGN_SHAREABLE UINT_C(0x00000002)
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160 | #if __TARGET_ARCH_ARM == 7
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161 | #define CP15_TTBR_RGN_WBWA UINT_C(0x00000008)
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162 | #endif /* __TARGET_ARCH_ARM == 7 */
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163 | #define CP15_TTBR_RGN_WTHROUGH UINT_C(0x00000010)
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164 | #define CP15_TTBR_RGN_WBACK UINT_C(0x00000018)
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165 | #if __TARGET_ARCH_ARM < 7
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166 | #define CP15_TTBR_RGN_CACHEABLE UINT_C(0x00000001)
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167 | #else /* __TARGET_ARCH_ARM < 7 */
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168 | #define CP15_TTBR_IRGN_WBWA UINT_C(0x00000040)
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169 | #define CP15_TTBR_IRGN_WTHROUGH UINT_C(0x00000001)
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170 | #define CP15_TTBR_IRGN_WBACK UINT_C(0x00000041)
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171 | #endif /* __TARGET_ARCH_ARM < 7 */
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172 |
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173 | /*
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174 | * MMUé¢é£ã®å®ç¾©ï¼VMSAï¼
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175 | */
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176 |
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177 | /*
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178 | * ã»ã¯ã·ã§ã³ã¨ãã¼ã¸ã®ãµã¤ãº
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179 | */
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180 | #define ARM_SSECTION_SIZE UINT_C(0x1000000)
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181 | #define ARM_SECTION_SIZE UINT_C(0x0100000)
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182 | #define ARM_LPAGE_SIZE UINT_C(0x0010000)
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183 | #define ARM_PAGE_SIZE UINT_C(0x0001000)
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184 |
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185 | /*
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186 | * ã»ã¯ã·ã§ã³ãã¼ãã«ã¨ãã¼ã¸ãã¼ãã«ã®ãµã¤ãº
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187 | */
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188 | #define ARM_SECTION_TABLE_SIZE UINT_C(0x4000)
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189 | #define ARM_SECTION_TABLE_ALIGN UINT_C(0x4000)
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190 | #define ARM_SECTION_TABLE_ENTRY (ARM_SECTION_TABLE_SIZE / sizeof(uint32_t))
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191 |
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192 | #define ARM_PAGE_TABLE_SIZE UINT_C(0x0400)
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193 | #define ARM_PAGE_TABLE_ALIGN UINT_C(0x0400)
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194 | #define ARM_PAGE_TABLE_ENTRY (ARM_PAGE_TABLE_SIZE / sizeof(uint32_t))
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195 |
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196 | /*
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197 | * 第1ã¬ãã«ãã£ã¹ã¯ãªãã¿ã®è¨å®å¤
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198 | */
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199 | #define ARM_MMU_DSCR1_FAULT 0x00000U /* ãã©ã«ã */
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200 | #define ARM_MMU_DSCR1_PAGETABLE 0x00001U /* ã³ã¢ã¼ã¹ãã¼ã¸ãã¼ãã« */
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201 | #define ARM_MMU_DSCR1_SECTION 0x00002U /* ã»ã¯ã·ã§ã³ */
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202 | #define ARM_MMU_DSCR1_SSECTION 0x40002U /* ã¹ã¼ãã¼ã»ã¯ã·ã§ã³ */
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203 |
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204 | #define ARM_MMU_DSCR1_SHARED 0x10000U /* ããã»ããµéã§å
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205 | ±æ */
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206 | #define ARM_MMU_DSCR1_TEX000 0x00000U /* TEXãããã000 */
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207 | #define ARM_MMU_DSCR1_TEX001 0x01000U /* TEXãããã001 */
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208 | #define ARM_MMU_DSCR1_TEX010 0x02000U /* TEXãããã010 */
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209 | #define ARM_MMU_DSCR1_TEX100 0x04000U /* TEXãããã100 */
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210 | #define ARM_MMU_DSCR1_AP01 0x00400U /* APãããã01 */
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211 | #define ARM_MMU_DSCR1_AP10 0x00800U /* APãããã10 */
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212 | #define ARM_MMU_DSCR1_AP11 0x00c00U /* APãããã11 */
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213 | #define ARM_MMU_DSCR1_CB00 0x00000U /* Cãããã0ï¼Bãããã0 */
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214 | #define ARM_MMU_DSCR1_CB01 0x00004U /* Cãããã0ï¼Bãããã1 */
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215 | #define ARM_MMU_DSCR1_CB10 0x00008U /* Cãããã1ï¼Bãããã0 */
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216 | #define ARM_MMU_DSCR1_CB11 0x0000cU /* Cãããã1ï¼Bãããã1 */
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217 |
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218 | #if __TARGET_ARCH_ARM >= 6
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219 | #define ARMV6_MMU_DSCR1_NONGLOBAL 0x20000U /* ã°ãã¼ãã«ã§ãªã */
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220 | #define ARMV6_MMU_DSCR1_APX0 0x00000U /* APXãããã0 */
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221 | #define ARMV6_MMU_DSCR1_APX1 0x08000U /* APXãããã1 */
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222 | #define ARMV6_MMU_DSCR1_ECC 0x00200U /* ECCãæå¹ï¼MPCoreï¼*/
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223 | #define ARMV6_MMU_DSCR1_NOEXEC 0x00010U /* å®è¡ä¸å¯ */
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224 | #endif /* __TARGET_ARCH_ARM >= 6 */
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225 |
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226 | /*
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227 | * 第2ã¬ãã«ãã£ã¹ã¯ãªãã¿ã®è¨å®å¤
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228 | */
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229 | #define ARM_MMU_DSCR2_FAULT 0x0000U /* ãã©ã«ã */
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230 | #define ARM_MMU_DSCR2_LARGE 0x0001U /* ã©ã¼ã¸ãã¼ã¸ */
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231 | #define ARM_MMU_DSCR2_SMALL 0x0002U /* ã¹ã¢ã¼ã«ãã¼ã¸ */
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232 |
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233 | #define ARM_MMU_DSCR2_CB00 0x0000U /* Cãããã0ï¼Bãããã0 */
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234 | #define ARM_MMU_DSCR2_CB01 0x0004U /* Cãããã0ï¼Bãããã1 */
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235 | #define ARM_MMU_DSCR2_CB10 0x0008U /* Cãããã1ï¼Bãããã0 */
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236 | #define ARM_MMU_DSCR2_CB11 0x000cU /* Cãããã1ï¼Bãããã1 */
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237 |
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238 | #if __TARGET_ARCH_ARM < 6
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239 |
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240 | #define ARMV5_MMU_DSCR2_AP01 0x0550U /* AP[0-3]ãããã01 */
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241 | #define ARMV5_MMU_DSCR2_AP10 0x0aa0U /* AP[0-3]ãããã10 */
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242 | #define ARMV5_MMU_DSCR2_AP11 0x0ff0U /* AP[0-3]ãããã11 */
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243 |
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244 | /* ã©ã¼ã¸ãã¼ã¸ã®ãã£ã¹ã¯ãªãã¿ç¨ */
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245 | #define ARMV5_MMU_DSCR2L_TEX000 0x0000U /* TEXãããã000 */
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246 | #define ARMV5_MMU_DSCR2L_TEX001 0x1000U /* TEXãããã001 */
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247 | #define ARMV5_MMU_DSCR2L_TEX010 0x2000U /* TEXãããã010 */
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248 | #define ARMV5_MMU_DSCR2L_TEX100 0x4000U /* TEXãããã100 */
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249 |
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250 | #else /* __TARGET_ARCH_ARM < 6 */
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251 |
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252 | #define ARMV6_MMU_DSCR2_NONGLOBAL 0x0800U /* ã°ãã¼ãã«ã§ãªã */
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253 | #define ARMV6_MMU_DSCR2_SHARED 0x0400U /* ããã»ããµéã§å
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254 | ±æ */
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255 | #define ARMV6_MMU_DSCR2_APX0 0x0000U /* APXãããã0 */
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256 | #define ARMV6_MMU_DSCR2_APX1 0x0200U /* APXãããã1 */
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257 | #define ARMV6_MMU_DSCR2_AP01 0x0010U /* APãããã01 */
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258 | #define ARMV6_MMU_DSCR2_AP10 0x0020U /* APãããã10 */
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259 | #define ARMV6_MMU_DSCR2_AP11 0x0030U /* APãããã11 */
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260 |
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261 | /* ã©ã¼ã¸ãã¼ã¸ã®ãã£ã¹ã¯ãªãã¿ç¨ */
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262 | #define ARMV6_MMU_DSCR2L_TEX000 0x0000U /* TEXãããã000 */
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263 | #define ARMV6_MMU_DSCR2L_TEX001 0x1000U /* TEXãããã001 */
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264 | #define ARMV6_MMU_DSCR2L_TEX010 0x2000U /* TEXãããã010 */
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265 | #define ARMV6_MMU_DSCR2L_TEX100 0x4000U /* TEXãããã100 */
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266 | #define ARMV6_MMU_DSCR2L_NOEXEC 0x8000U /* å®è¡ä¸å¯ */
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267 |
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268 | /* ã¹ã¢ã¼ã«ãã¼ã¸ã®ãã£ã¹ã¯ãªãã¿ç¨ */
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269 | #define ARMV6_MMU_DSCR2S_TEX000 0x0000U /* TEXãããã000 */
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270 | #define ARMV6_MMU_DSCR2S_TEX001 0x0040U /* TEXãããã001 */
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271 | #define ARMV6_MMU_DSCR2S_TEX010 0x0080U /* TEXãããã010 */
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272 | #define ARMV6_MMU_DSCR2S_TEX100 0x0100U /* TEXãããã100 */
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273 | #define ARMV6_MMU_DSCR2S_NOEXEC 0x0001U /* å®è¡ä¸å¯ */
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274 |
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275 | #endif /* __TARGET_ARCH_ARM < 6 */
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276 |
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277 | #ifndef TOPPERS_MACRO_ONLY
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278 |
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279 | /*
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280 | * ã³ããã»ããµ15ã®æä½é¢æ°
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281 | */
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282 |
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283 | /*
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284 | * High exception vectorã使ããã®è¨å®
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285 | */
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286 | Inline void
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287 | arm_set_high_vector(bool_t enable)
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288 | {
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289 | uint32_t reg;
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290 |
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291 | CP15_READ_SCTLR(reg);
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292 | if (enable) {
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293 | reg |= CP15_SCTLR_VECTOR;
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294 | }
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295 | else {
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296 | reg &= ~CP15_SCTLR_VECTOR;
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297 | }
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298 | CP15_WRITE_SCTLR(reg);
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299 | }
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300 |
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301 | /*
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302 | * ããã»ããµçªå·ã®åå¾
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303 | *
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304 | * ãã«ãããã»ããµã¢ãã£ããã£ã¬ã¸ã¹ã¿ãèªãã§ï¼ãã®ä¸ä½8ããããè¿ãï¼
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305 | * ARMv6ã§ã¯ï¼ãã«ãããã»ããµããµãã¼ããã¦ããå ´åã«ã®ã¿ä½¿ç¨ã§ããï¼
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306 | */
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307 | #if __TARGET_ARCH_ARM >= 6
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308 |
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309 | Inline uint32_t
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310 | arm_prc_index(void)
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311 | {
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312 | uint32_t reg;
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313 |
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314 | CP15_READ_MPIDR(reg);
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315 | return(reg & 0xffU);
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316 | }
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317 |
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318 | #endif /* __TARGET_ARCH_ARM >= 6 */
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319 |
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320 | /*
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321 | * ãã£ãã·ã¥ã®æä½
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322 | */
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323 |
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324 | /*
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325 | * å½ä»¤ï¼ãã¼ã¿ãã£ãã·ã¥ã®ã¤ãã¼ãã«ï¼ãã£ã¹ã¨ã¼ãã«
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326 | */
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327 | extern void arm_enable_icache(void);
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328 | extern void arm_disable_icache(void);
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329 | extern void arm_enable_dcache(void);
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330 | extern void arm_disable_dcache(void);
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331 |
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332 | /*
|
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333 | * ãã£ãã·ã¥ã®ã¤ãã¼ãã«
|
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334 | */
|
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335 | Inline void
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336 | arm_enable_cache(void)
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337 | {
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338 | arm_enable_icache();
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339 | arm_enable_dcache();
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340 | }
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341 |
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342 | /*
|
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343 | * ãã£ãã·ã¥ã®ãã£ã¹ã¨ã¼ãã«
|
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344 | */
|
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345 | Inline void
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346 | arm_disable_cache(void)
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347 | {
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348 | arm_disable_icache();
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349 | arm_disable_dcache();
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350 | }
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351 |
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352 | /*
|
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353 | * ARMv5ã«ããããã¼ã¿ãã£ãã·ã¥ã®ç¡å¹åï¼ã¯ãªã¼ã³
|
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354 | */
|
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355 | #if __TARGET_ARCH_ARM <= 5
|
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356 | extern void armv5_clean_and_invalidate_dcache(void);
|
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357 | #endif /* __TARGET_ARCH_ARM <= 5 */
|
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358 |
|
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359 | /*
|
---|
360 | * ARMv7ã«ããããã¼ã¿ãã£ãã·ã¥ã®ç¡å¹åï¼ã¯ãªã¼ã³
|
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361 | */
|
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362 | #if __TARGET_ARCH_ARM == 7
|
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363 | extern void armv7_invalidate_dcache(void);
|
---|
364 | extern void armv7_clean_and_invalidate_dcache(void);
|
---|
365 | #endif /* __TARGET_ARCH_ARM == 7 */
|
---|
366 |
|
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367 | /*
|
---|
368 | * ãã¼ã¿ãã£ãã·ã¥ã¨çµ±åãã£ãã·ã¥ã®ç¡å¹å
|
---|
369 | */
|
---|
370 | Inline void
|
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371 | arm_invalidate_dcache(void)
|
---|
372 | {
|
---|
373 | #if __TARGET_ARCH_ARM <= 6
|
---|
374 | CP15_INVALIDATE_DCACHE();
|
---|
375 | CP15_INVALIDATE_UCACHE();
|
---|
376 | #else /* __TARGET_ARCH_ARM <= 6 */
|
---|
377 | armv7_invalidate_dcache();
|
---|
378 | #endif /* __TARGET_ARCH_ARM <= 6 */
|
---|
379 | }
|
---|
380 |
|
---|
381 | /*
|
---|
382 | * ãã¼ã¿ãã£ãã·ã¥ã¨çµ±åãã£ãã·ã¥ã®ã¯ãªã¼ã³ã¨ç¡å¹å
|
---|
383 | */
|
---|
384 | Inline void
|
---|
385 | arm_clean_and_invalidate_dcache(void)
|
---|
386 | {
|
---|
387 | #if __TARGET_ARCH_ARM <= 5
|
---|
388 | armv5_clean_and_invalidate_dcache();
|
---|
389 | #elif __TARGET_ARCH_ARM == 6
|
---|
390 | CP15_CLEAN_AND_INVALIDATE_DCACHE();
|
---|
391 | CP15_CLEAN_AND_INVALIDATE_UCACHE();
|
---|
392 | #else
|
---|
393 | armv7_clean_and_invalidate_dcache();
|
---|
394 | #endif
|
---|
395 | }
|
---|
396 |
|
---|
397 | /*
|
---|
398 | * å½ä»¤ãã£ãã·ã¥ã®ç¡å¹å
|
---|
399 | */
|
---|
400 | Inline void
|
---|
401 | arm_invalidate_icache(void)
|
---|
402 | {
|
---|
403 | CP15_INVALIDATE_ICACHE();
|
---|
404 | }
|
---|
405 |
|
---|
406 | /*
|
---|
407 | * TLBã®ç¡å¹å
|
---|
408 | */
|
---|
409 | Inline void
|
---|
410 | arm_invalidate_tlb(void)
|
---|
411 | {
|
---|
412 | CP15_INVALIDATE_TLB();
|
---|
413 | data_sync_barrier();
|
---|
414 | }
|
---|
415 |
|
---|
416 | #endif /* TOPPERS_MACRO_ONLY */
|
---|
417 | #endif /* TOPPERS_ARM_H */
|
---|