1 | /*******************************************************************************
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2 | * DISCLAIMER
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3 | * This software is supplied by Renesas Electronics Corporation and is only
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4 | * intended for use with Renesas products. No other uses are authorized. This
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5 | * software is owned by Renesas Electronics Corporation and is protected under
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6 | * all applicable laws, including copyright laws.
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7 | * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
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8 | * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
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9 | * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
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10 | * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
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11 | * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
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12 | * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
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13 | * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
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14 | * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
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15 | * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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16 | * Renesas reserves the right, without notice, to make changes to this software
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17 | * and to discontinue the availability of this software. By using this software,
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18 | * you agree to the additional terms and conditions found by accessing the
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19 | * following link:
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20 | * http://www.renesas.com/disclaimer*
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21 | * Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
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22 | *******************************************************************************/
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23 | /*******************************************************************************
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24 | * File Name : pwm_iodefine.h
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25 | * $Rev: $
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26 | * $Date:: $
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27 | * Description : Definition of I/O Register (V1.00a)
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28 | ******************************************************************************/
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29 | #ifndef PWM_IODEFINE_H
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30 | #define PWM_IODEFINE_H
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31 | /* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
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32 | /* ->SEC M1.10.1 : Not magic number */
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33 |
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34 | union reg16_8_t
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35 | {
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36 | volatile uint16_t UINT16; /* 16-bit Access */
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37 | volatile uint8_t UINT8[2]; /* 8-bit Access */
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38 | };
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39 |
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40 | struct st_pwm
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41 | { /* PWM */
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42 | volatile uint8_t dummy559[2]; /* */
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43 | union reg16_8_t PWBTCR; /* PWBTCR */
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44 |
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45 | volatile uint8_t dummy560[216]; /* */
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46 |
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47 | /* start of struct st_pwm_common */
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48 | union reg16_8_t PWCR_1; /* PWCR_1 */
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49 |
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50 | volatile uint8_t dummy561[2]; /* */
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51 | union reg16_8_t PWPR_1; /* PWPR_1 */
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52 |
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53 | volatile uint16_t PWCYR_1; /* PWCYR_1 */
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54 | volatile uint16_t PWBFR_1A; /* PWBFR_1A */
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55 | volatile uint16_t PWBFR_1C; /* PWBFR_1C */
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56 | volatile uint16_t PWBFR_1E; /* PWBFR_1E */
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57 | volatile uint16_t PWBFR_1G; /* PWBFR_1G */
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58 | /* end of struct st_pwm_common */
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59 |
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60 | /* start of struct st_pwm_common */
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61 | union reg16_8_t PWCR_2; /* PWCR_2 */
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62 |
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63 | volatile uint8_t dummy562[2]; /* */
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64 | union reg16_8_t PWPR_2; /* PWPR_2 */
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65 |
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66 | volatile uint16_t PWCYR_2; /* PWCYR_2 */
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67 | volatile uint16_t PWBFR_2A; /* PWBFR_2A */
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68 | volatile uint16_t PWBFR_2C; /* PWBFR_2C */
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69 | volatile uint16_t PWBFR_2E; /* PWBFR_2E */
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70 | volatile uint16_t PWBFR_2G; /* PWBFR_2G */
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71 | /* end of struct st_pwm_common */
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72 | };
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73 |
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74 |
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75 | struct st_pwm_common
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76 | {
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77 | union reg16_8_t PWCR_1; /* PWCR_1 */
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78 |
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79 | volatile uint8_t dummy572[2]; /* */
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80 | union reg16_8_t PWPR_1; /* PWPR_1 */
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81 |
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82 | volatile uint16_t PWCYR_1; /* PWCYR_1 */
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83 | volatile uint16_t PWBFR_1A; /* PWBFR_1A */
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84 | volatile uint16_t PWBFR_1C; /* PWBFR_1C */
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85 | volatile uint16_t PWBFR_1E; /* PWBFR_1E */
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86 | volatile uint16_t PWBFR_1G; /* PWBFR_1G */
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87 | };
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88 |
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89 |
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90 | #define PWM (*(struct st_pwm *)0xFCFF5004uL) /* PWM */
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91 |
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92 |
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93 | /* Start of channnel array defines of PWM */
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94 |
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95 | /* Channnel array defines of PWMn */
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96 | /*(Sample) value = PWMn[ channel ]->PWCR_1.UINT16; */
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97 | #define PWMn_COUNT 2
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98 | #define PWMn_ADDRESS_LIST \
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99 | { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
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100 | &PWM1, &PWM2 \
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101 | } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
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102 | #define PWM1 (*(struct st_pwm_common *)&PWM.PWCR_1) /* PWM1 */
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103 | #define PWM2 (*(struct st_pwm_common *)&PWM.PWCR_2) /* PWM2 */
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104 |
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105 | /* End of channnel array defines of PWM */
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106 |
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107 |
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108 | #define PWMPWBTCR PWM.PWBTCR.UINT16
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109 | #define PWMPWBTCR_BYTE_L PWM.PWBTCR.UINT8[0]
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110 | #define PWMPWBTCR_BYTE_H PWM.PWBTCR.UINT8[1]
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111 | #define PWMPWCR_1 PWM.PWCR_1.UINT16
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112 | #define PWMPWCR_1_BYTE_L PWM.PWCR_1.UINT8[0]
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113 | #define PWMPWCR_1_BYTE_H PWM.PWCR_1.UINT8[1]
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114 | #define PWMPWPR_1 PWM.PWPR_1.UINT16
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115 | #define PWMPWPR_1_BYTE_L PWM.PWPR_1.UINT8[0]
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116 | #define PWMPWPR_1_BYTE_H PWM.PWPR_1.UINT8[1]
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117 | #define PWMPWCYR_1 PWM.PWCYR_1
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118 | #define PWMPWBFR_1A PWM.PWBFR_1A
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119 | #define PWMPWBFR_1C PWM.PWBFR_1C
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120 | #define PWMPWBFR_1E PWM.PWBFR_1E
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121 | #define PWMPWBFR_1G PWM.PWBFR_1G
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122 | #define PWMPWCR_2 PWM.PWCR_2.UINT16
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123 | #define PWMPWCR_2_BYTE_L PWM.PWCR_2.UINT8[0]
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124 | #define PWMPWCR_2_BYTE_H PWM.PWCR_2.UINT8[1]
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125 | #define PWMPWPR_2 PWM.PWPR_2.UINT16
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126 | #define PWMPWPR_2_BYTE_L PWM.PWPR_2.UINT8[0]
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127 | #define PWMPWPR_2_BYTE_H PWM.PWPR_2.UINT8[1]
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128 | #define PWMPWCYR_2 PWM.PWCYR_2
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129 | #define PWMPWBFR_2A PWM.PWBFR_2A
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130 | #define PWMPWBFR_2C PWM.PWBFR_2C
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131 | #define PWMPWBFR_2E PWM.PWBFR_2E
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132 | #define PWMPWBFR_2G PWM.PWBFR_2G
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133 | /* <-SEC M1.10.1 */
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134 | /* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
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135 | #endif
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