1 | /*******************************************************************************
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2 | * DISCLAIMER
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3 | * This software is supplied by Renesas Electronics Corporation and is only
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4 | * intended for use with Renesas products. No other uses are authorized. This
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5 | * software is owned by Renesas Electronics Corporation and is protected under
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6 | * all applicable laws, including copyright laws.
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7 | * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
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8 | * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
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9 | * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
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10 | * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
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11 | * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
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12 | * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
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13 | * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
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14 | * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
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15 | * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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16 | * Renesas reserves the right, without notice, to make changes to this software
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17 | * and to discontinue the availability of this software. By using this software,
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18 | * you agree to the additional terms and conditions found by accessing the
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19 | * following link:
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20 | * http://www.renesas.com/disclaimer*
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21 | * Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
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22 | *******************************************************************************/
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23 | /*******************************************************************************
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24 | * File Name : pfv_iodefine.h
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25 | * $Rev: $
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26 | * $Date:: $
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27 | * Description : Definition of I/O Register (V1.00a)
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28 | ******************************************************************************/
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29 | #ifndef PFV_IODEFINE_H
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30 | #define PFV_IODEFINE_H
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31 | /* ->SEC M1.10.1 : Not magic number */
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32 |
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33 | struct st_pfv
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34 | { /* PFV */
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35 | volatile uint32_t PFVCR; /* PFVCR */
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36 | volatile uint32_t PFVICR; /* PFVICR */
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37 | volatile uint32_t PFVISR; /* PFVISR */
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38 | volatile uint8_t dummy1[20]; /* */
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39 | #define PFVID_COUNT 8
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40 | volatile uint32_t PFVID0; /* PFVID0 */
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41 | volatile uint32_t PFVID1; /* PFVID1 */
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42 | volatile uint32_t PFVID2; /* PFVID2 */
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43 | volatile uint32_t PFVID3; /* PFVID3 */
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44 | volatile uint32_t PFVID4; /* PFVID4 */
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45 | volatile uint32_t PFVID5; /* PFVID5 */
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46 | volatile uint32_t PFVID6; /* PFVID6 */
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47 | volatile uint32_t PFVID7; /* PFVID7 */
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48 | #define PFVOD_COUNT 8
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49 | volatile uint32_t PFVOD0; /* PFVOD0 */
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50 | volatile uint32_t PFVOD1; /* PFVOD1 */
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51 | volatile uint32_t PFVOD2; /* PFVOD2 */
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52 | volatile uint32_t PFVOD3; /* PFVOD3 */
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53 | volatile uint32_t PFVOD4; /* PFVOD4 */
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54 | volatile uint32_t PFVOD5; /* PFVOD5 */
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55 | volatile uint32_t PFVOD6; /* PFVOD6 */
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56 | volatile uint32_t PFVOD7; /* PFVOD7 */
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57 | volatile uint8_t dummy2[4]; /* */
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58 | volatile uint32_t PFVIFSR; /* PFVIFSR */
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59 | volatile uint32_t PFVOFSR; /* PFVOFSR */
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60 | volatile uint32_t PFVACR; /* PFVACR */
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61 | volatile uint32_t PFV_MTX_MODE; /* PFV_MTX_MODE */
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62 | volatile uint32_t PFV_MTX_YG_ADJ0; /* PFV_MTX_YG_ADJ0 */
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63 | volatile uint32_t PFV_MTX_YG_ADJ1; /* PFV_MTX_YG_ADJ1 */
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64 | volatile uint32_t PFV_MTX_CBB_ADJ0; /* PFV_MTX_CBB_ADJ0 */
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65 | volatile uint32_t PFV_MTX_CBB_ADJ1; /* PFV_MTX_CBB_ADJ1 */
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66 | volatile uint32_t PFV_MTX_CRR_ADJ0; /* PFV_MTX_CRR_ADJ0 */
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67 | volatile uint32_t PFV_MTX_CRR_ADJ1; /* PFV_MTX_CRR_ADJ1 */
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68 | volatile uint32_t PFVSZR; /* PFVSZR */
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69 | };
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70 |
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71 |
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72 | #define PFV0 (*(struct st_pfv *)0xE8205000uL) /* PFV0 */
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73 | #define PFV1 (*(struct st_pfv *)0xE8205800uL) /* PFV1 */
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74 |
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75 |
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76 | /* Start of channnel array defines of PFV */
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77 |
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78 | /* Channnel array defines of PFV */
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79 | /*(Sample) value = PFV[ channel ]->PFVCR; */
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80 | #define PFV_COUNT 2
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81 | #define PFV_ADDRESS_LIST \
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82 | { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
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83 | &PFV0, &PFV1 \
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84 | } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
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85 |
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86 | /* End of channnel array defines of PFV */
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87 |
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88 |
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89 | #define PFV0PFVCR PFV0.PFVCR
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90 | #define PFV0PFVICR PFV0.PFVICR
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91 | #define PFV0PFVISR PFV0.PFVISR
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92 | #define PFV0PFVID0 PFV0.PFVID0
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93 | #define PFV0PFVID1 PFV0.PFVID1
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94 | #define PFV0PFVID2 PFV0.PFVID2
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95 | #define PFV0PFVID3 PFV0.PFVID3
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96 | #define PFV0PFVID4 PFV0.PFVID4
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97 | #define PFV0PFVID5 PFV0.PFVID5
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98 | #define PFV0PFVID6 PFV0.PFVID6
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99 | #define PFV0PFVID7 PFV0.PFVID7
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100 | #define PFV0PFVOD0 PFV0.PFVOD0
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101 | #define PFV0PFVOD1 PFV0.PFVOD1
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102 | #define PFV0PFVOD2 PFV0.PFVOD2
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103 | #define PFV0PFVOD3 PFV0.PFVOD3
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104 | #define PFV0PFVOD4 PFV0.PFVOD4
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105 | #define PFV0PFVOD5 PFV0.PFVOD5
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106 | #define PFV0PFVOD6 PFV0.PFVOD6
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107 | #define PFV0PFVOD7 PFV0.PFVOD7
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108 | #define PFV0PFVIFSR PFV0.PFVIFSR
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109 | #define PFV0PFVOFSR PFV0.PFVOFSR
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110 | #define PFV0PFVACR PFV0.PFVACR
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111 | #define PFV0PFV_MTX_MODE PFV0.PFV_MTX_MODE
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112 | #define PFV0PFV_MTX_YG_ADJ0 PFV0.PFV_MTX_YG_ADJ0
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113 | #define PFV0PFV_MTX_YG_ADJ1 PFV0.PFV_MTX_YG_ADJ1
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114 | #define PFV0PFV_MTX_CBB_ADJ0 PFV0.PFV_MTX_CBB_ADJ0
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115 | #define PFV0PFV_MTX_CBB_ADJ1 PFV0.PFV_MTX_CBB_ADJ1
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116 | #define PFV0PFV_MTX_CRR_ADJ0 PFV0.PFV_MTX_CRR_ADJ0
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117 | #define PFV0PFV_MTX_CRR_ADJ1 PFV0.PFV_MTX_CRR_ADJ1
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118 | #define PFV0PFVSZR PFV0.PFVSZR
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119 | #define PFV1PFVCR PFV1.PFVCR
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120 | #define PFV1PFVICR PFV1.PFVICR
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121 | #define PFV1PFVISR PFV1.PFVISR
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122 | #define PFV1PFVID0 PFV1.PFVID0
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123 | #define PFV1PFVID1 PFV1.PFVID1
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124 | #define PFV1PFVID2 PFV1.PFVID2
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125 | #define PFV1PFVID3 PFV1.PFVID3
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126 | #define PFV1PFVID4 PFV1.PFVID4
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127 | #define PFV1PFVID5 PFV1.PFVID5
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128 | #define PFV1PFVID6 PFV1.PFVID6
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129 | #define PFV1PFVID7 PFV1.PFVID7
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130 | #define PFV1PFVOD0 PFV1.PFVOD0
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131 | #define PFV1PFVOD1 PFV1.PFVOD1
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132 | #define PFV1PFVOD2 PFV1.PFVOD2
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133 | #define PFV1PFVOD3 PFV1.PFVOD3
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134 | #define PFV1PFVOD4 PFV1.PFVOD4
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135 | #define PFV1PFVOD5 PFV1.PFVOD5
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136 | #define PFV1PFVOD6 PFV1.PFVOD6
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137 | #define PFV1PFVOD7 PFV1.PFVOD7
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138 | #define PFV1PFVIFSR PFV1.PFVIFSR
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139 | #define PFV1PFVOFSR PFV1.PFVOFSR
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140 | #define PFV1PFVACR PFV1.PFVACR
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141 | #define PFV1PFV_MTX_MODE PFV1.PFV_MTX_MODE
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142 | #define PFV1PFV_MTX_YG_ADJ0 PFV1.PFV_MTX_YG_ADJ0
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143 | #define PFV1PFV_MTX_YG_ADJ1 PFV1.PFV_MTX_YG_ADJ1
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144 | #define PFV1PFV_MTX_CBB_ADJ0 PFV1.PFV_MTX_CBB_ADJ0
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145 | #define PFV1PFV_MTX_CBB_ADJ1 PFV1.PFV_MTX_CBB_ADJ1
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146 | #define PFV1PFV_MTX_CRR_ADJ0 PFV1.PFV_MTX_CRR_ADJ0
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147 | #define PFV1PFV_MTX_CRR_ADJ1 PFV1.PFV_MTX_CRR_ADJ1
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148 | #define PFV1PFVSZR PFV1.PFVSZR
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149 | /* <-SEC M1.10.1 */
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150 | #endif
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