[352] | 1 | /* mbed Microcontroller Library
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| 2 | * Copyright (c) 2006-2013 ARM Limited
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| 3 | *
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| 4 | * Licensed under the Apache License, Version 2.0 (the "License");
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| 5 | * you may not use this file except in compliance with the License.
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| 6 | * You may obtain a copy of the License at
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| 7 | *
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| 8 | * http://www.apache.org/licenses/LICENSE-2.0
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| 9 | *
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| 10 | * Unless required by applicable law or agreed to in writing, software
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| 11 | * distributed under the License is distributed on an "AS IS" BASIS,
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| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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| 13 | * See the License for the specific language governing permissions and
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| 14 | * limitations under the License.
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| 15 | */
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| 16 | #include "us_ticker_api.h"
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[374] | 17 | #include "mbed_drv_cfg.h"
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[352] | 18 |
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[374] | 19 | #define SHIFT_NUM 5 /* P0/32 */
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[352] | 20 |
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[374] | 21 | static int us_ticker_inited = 0;
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[352] | 22 |
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[374] | 23 | void us_ticker_init(void)
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| 24 | {
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| 25 | GIC_DisableIRQ(OSTMI1TINT_IRQn);
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| 26 | GIC_ClearPendingIRQ(OSTMI1TINT_IRQn);
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[352] | 27 |
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[374] | 28 | /* Power Control for Peripherals */
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| 29 | CPGSTBCR5 &= ~(CPG_STBCR5_BIT_MSTP50); /* enable OSTM1 clock */
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[352] | 30 |
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| 31 | if (us_ticker_inited) return;
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| 32 | us_ticker_inited = 1;
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| 33 |
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| 34 | // timer settings
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| 35 | OSTM1TT = 0x01; /* Stop the counter and clears the OSTM1TE bit. */
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| 36 | OSTM1CTL = 0x02; /* Free running timer mode. Interrupt disabled when star counter */
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| 37 |
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[374] | 38 | OSTM1TS = 0x1; /* Start the counter and sets the OSTM0TE bit. */
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[352] | 39 |
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| 40 | // INTC settings
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[374] | 41 | InterruptHandlerRegister(OSTMI1TINT_IRQn, (void (*)(uint32_t))us_ticker_irq_handler);
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| 42 | GIC_SetPriority(OSTMI1TINT_IRQn, 5);
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| 43 | GIC_SetConfiguration(OSTMI1TINT_IRQn, 3);
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[352] | 44 | }
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| 45 |
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[374] | 46 | void us_ticker_free(void)
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| 47 | {
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| 48 | GIC_DisableIRQ(OSTMI1TINT_IRQn);
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| 49 | GIC_ClearPendingIRQ(OSTMI1TINT_IRQn);
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[352] | 50 |
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[374] | 51 | /* Power Control for Peripherals */
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| 52 | CPGSTBCR5 |= (CPG_STBCR5_BIT_MSTP50); /* disable OSTM1 clock */
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| 53 | }
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[352] | 54 |
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[374] | 55 | uint32_t us_ticker_read()
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| 56 | {
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| 57 | return (uint32_t)(OSTM1CNT >> SHIFT_NUM);
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[352] | 58 | }
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| 59 |
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[374] | 60 | void us_ticker_set_interrupt(timestamp_t timestamp)
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| 61 | {
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| 62 | OSTM1CMP = (uint32_t)(timestamp << SHIFT_NUM);
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| 63 | GIC_EnableIRQ(OSTMI1TINT_IRQn);
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[352] | 64 | }
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| 65 |
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[374] | 66 | void us_ticker_fire_interrupt(void)
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| 67 | {
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| 68 | GIC_SetPendingIRQ(OSTMI1TINT_IRQn);
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| 69 | GIC_EnableIRQ(OSTMI1TINT_IRQn);
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[352] | 70 | }
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| 71 |
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[374] | 72 | void us_ticker_disable_interrupt(void)
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| 73 | {
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| 74 | GIC_DisableIRQ(OSTMI1TINT_IRQn);
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[352] | 75 | }
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| 76 |
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[374] | 77 | void us_ticker_clear_interrupt(void)
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| 78 | {
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| 79 | GIC_ClearPendingIRQ(OSTMI1TINT_IRQn);
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[352] | 80 | }
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| 81 |
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[374] | 82 | const ticker_info_t* us_ticker_get_info()
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| 83 | {
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| 84 | static const ticker_info_t info = {
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| 85 | (uint32_t)((float)RENESAS_RZ_A1_P0_CLK / (float)(1 << SHIFT_NUM) + 0.5f),
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| 86 | (32 - SHIFT_NUM)
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| 87 | };
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| 88 | return &info;
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[352] | 89 | }
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| 90 |
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