1 | /* mbed Microcontroller Library
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2 | * Copyright (c) 2006-2013 ARM Limited
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3 | *
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4 | * Licensed under the Apache License, Version 2.0 (the "License");
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5 | * you may not use this file except in compliance with the License.
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6 | * You may obtain a copy of the License at
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7 | *
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8 | * http://www.apache.org/licenses/LICENSE-2.0
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9 | *
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10 | * Unless required by applicable law or agreed to in writing, software
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11 | * distributed under the License is distributed on an "AS IS" BASIS,
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12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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13 | * See the License for the specific language governing permissions and
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14 | * limitations under the License.
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15 | */
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16 | #include "mbed_assert.h"
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17 | #include "pwmout_api.h"
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18 | #include "cmsis.h"
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19 | #include "PeripheralPins.h"
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20 | #include "RZ_A1_Init.h"
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21 | #include "iodefine.h"
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22 | #include "gpio_addrdefine.h"
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23 | #include "mbed_drv_cfg.h"
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24 | #include "mtu2.h"
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25 |
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26 | #define MTU2_PWM_OFFSET 0x20
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27 |
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28 | #ifdef FUNC_MOTOR_CTL_PWM
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29 | typedef enum {
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30 | PWM1A = 0,
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31 | PWM1B,
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32 | PWM1C,
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33 | PWM1D,
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34 | PWM1E,
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35 | PWM1F,
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36 | PWM1G,
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37 | PWM1H,
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38 | PWM2A = 0x10,
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39 | PWM2B,
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40 | PWM2C,
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41 | PWM2D,
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42 | PWM2E,
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43 | PWM2F,
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44 | PWM2G,
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45 | PWM2H,
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46 | } PWMType;
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47 |
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48 | static const PWMType PORT[] = {
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49 | PWM1A, // PWM_PWM1A
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50 | PWM1B, // PWM_PWM1B
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51 | PWM1C, // PWM_PWM1C
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52 | PWM1D, // PWM_PWM1D
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53 | PWM1E, // PWM_PWM1E
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54 | PWM1F, // PWM_PWM1F
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55 | PWM1G, // PWM_PWM1G
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56 | PWM1H, // PWM_PWM1H
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57 | PWM2A, // PWM_PWM2A
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58 | PWM2B, // PWM_PWM2B
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59 | PWM2C, // PWM_PWM2C
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60 | PWM2D, // PWM_PWM2D
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61 | PWM2E, // PWM_PWM2E
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62 | PWM2F, // PWM_PWM2F
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63 | PWM2G, // PWM_PWM2G
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64 | PWM2H, // PWM_PWM2H
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65 | };
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66 |
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67 | static __IO uint16_t *PWM_MATCH[] = {
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68 | &PWMPWBFR_1A, // PWM_PWM1A
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69 | &PWMPWBFR_1A, // PWM_PWM1B
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70 | &PWMPWBFR_1C, // PWM_PWM1C
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71 | &PWMPWBFR_1C, // PWM_PWM1D
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72 | &PWMPWBFR_1E, // PWM_PWM1E
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73 | &PWMPWBFR_1E, // PWM_PWM1F
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74 | &PWMPWBFR_1G, // PWM_PWM1G
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75 | &PWMPWBFR_1G, // PWM_PWM1H
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76 | &PWMPWBFR_2A, // PWM_PWM2A
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77 | &PWMPWBFR_2A, // PWM_PWM2B
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78 | &PWMPWBFR_2C, // PWM_PWM2C
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79 | &PWMPWBFR_2C, // PWM_PWM2D
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80 | &PWMPWBFR_2E, // PWM_PWM2E
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81 | &PWMPWBFR_2E, // PWM_PWM2F
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82 | &PWMPWBFR_2G, // PWM_PWM2G
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83 | &PWMPWBFR_2G, // PWM_PWM2H
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84 | };
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85 |
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86 | static uint16_t init_period_ch1 = 0;
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87 | static uint16_t init_period_ch2 = 0;
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88 | static int32_t period_ch1 = 1;
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89 | static int32_t period_ch2 = 1;
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90 | #endif
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91 |
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92 | #ifdef FUMC_MTU2_PWM
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93 | #define MTU2_PWM_SIGNAL 2
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94 |
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95 | typedef enum {
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96 | TIOC0A = 0,
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97 | TIOC0B,
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98 | TIOC0C,
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99 | TIOC0D,
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100 | TIOC1A = 0x10,
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101 | TIOC1B,
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102 | TIOC2A = 0x20,
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103 | TIOC2B,
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104 | TIOC3A = 0x30,
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105 | TIOC3B,
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106 | TIOC3C,
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107 | TIOC3D,
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108 | TIOC4A = 0x40,
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109 | TIOC4B,
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110 | TIOC4C,
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111 | TIOC4D,
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112 | } MTU2_PWMType;
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113 |
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114 | static const MTU2_PWMType MTU2_PORT[] = {
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115 | TIOC0A, // PWM_TIOC0A
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116 | TIOC0C, // PWM_TIOC0C
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117 | TIOC1A, // PWM_TIOC1A
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118 | TIOC2A, // PWM_TIOC2A
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119 | TIOC3A, // PWM_TIOC3A
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120 | TIOC3C, // PWM_TIOC3C
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121 | TIOC4A, // PWM_TIOC4A
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122 | TIOC4C, // PWM_TIOC4C
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123 | };
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124 |
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125 | static __IO uint16_t *MTU2_PWM_MATCH[][MTU2_PWM_SIGNAL] = {
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126 | { &MTU2TGRA_0, &MTU2TGRB_0 }, // PWM_TIOC0A
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127 | { &MTU2TGRC_0, &MTU2TGRD_0 }, // PWM_TIOC0C
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128 | { &MTU2TGRA_1, &MTU2TGRB_1 }, // PWM_TIOC1A
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129 | { &MTU2TGRA_2, &MTU2TGRB_2 }, // PWM_TIOC2A
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130 | { &MTU2TGRA_3, &MTU2TGRB_3 }, // PWM_TIOC3A
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131 | { &MTU2TGRC_3, &MTU2TGRD_3 }, // PWM_TIOC3C
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132 | { &MTU2TGRA_4, &MTU2TGRB_4 }, // PWM_TIOC4A
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133 | { &MTU2TGRC_4, &MTU2TGRD_4 }, // PWM_TIOC4C
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134 | };
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135 |
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136 | static __IO uint8_t *TCR_MATCH[] = {
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137 | &MTU2TCR_0,
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138 | &MTU2TCR_1,
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139 | &MTU2TCR_2,
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140 | &MTU2TCR_3,
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141 | &MTU2TCR_4,
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142 | };
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143 |
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144 | static __IO uint8_t *TIORH_MATCH[] = {
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145 | &MTU2TIORH_0,
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146 | &MTU2TIOR_1,
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147 | &MTU2TIOR_2,
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148 | &MTU2TIORH_3,
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149 | &MTU2TIORH_4,
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150 | };
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151 |
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152 | static __IO uint8_t *TIORL_MATCH[] = {
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153 | &MTU2TIORL_0,
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154 | NULL,
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155 | NULL,
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156 | &MTU2TIORL_3,
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157 | &MTU2TIORL_4,
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158 | };
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159 |
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160 | static __IO uint16_t *TGRA_MATCH[] = {
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161 | &MTU2TGRA_0,
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162 | &MTU2TGRA_1,
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163 | &MTU2TGRA_2,
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164 | &MTU2TGRA_3,
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165 | &MTU2TGRA_4,
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166 | };
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167 |
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168 | static __IO uint16_t *TGRC_MATCH[] = {
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169 | &MTU2TGRC_0,
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170 | NULL,
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171 | NULL,
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172 | &MTU2TGRC_3,
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173 | &MTU2TGRC_4,
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174 | };
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175 |
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176 | static __IO uint8_t *TMDR_MATCH[] = {
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177 | &MTU2TMDR_0,
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178 | &MTU2TMDR_1,
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179 | &MTU2TMDR_2,
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180 | &MTU2TMDR_3,
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181 | &MTU2TMDR_4,
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182 | };
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183 |
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184 | static int MAX_PERIOD[] = {
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185 | 125000,
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186 | 503000,
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187 | 2000000,
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188 | 2000000,
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189 | 2000000,
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190 | };
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191 |
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192 | typedef enum {
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193 | MTU2_PULSE = 0,
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194 | MTU2_PERIOD
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195 | } MTU2Signal;
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196 |
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197 | static uint16_t init_mtu2_period_ch[5] = {0};
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198 | static int32_t mtu2_period_ch[5] = {1, 1, 1, 1, 1};
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199 | #endif
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200 |
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201 | void pwmout_init(pwmout_t* obj, PinName pin) {
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202 | // determine the channel
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203 | PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM);
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204 | MBED_ASSERT(pwm != (PWMName)NC);
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205 |
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206 | if (pwm >= MTU2_PWM_OFFSET) {
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207 | #ifdef FUMC_MTU2_PWM
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208 | /* PWM by MTU2 */
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209 | int tmp_pwm;
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210 |
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211 | // power on
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212 | mtu2_init();
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213 |
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214 | obj->pwm = pwm;
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215 | tmp_pwm = (int)(obj->pwm - MTU2_PWM_OFFSET);
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216 | if (((uint32_t)MTU2_PORT[tmp_pwm] & 0x00000040) == 0x00000040) {
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217 | obj->ch = 4;
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218 | MTU2TOER |= 0x36;
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219 | } else if (((uint32_t)MTU2_PORT[tmp_pwm] & 0x00000030) == 0x00000030) {
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220 | obj->ch = 3;
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221 | MTU2TOER |= 0x09;
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222 | } else if (((uint32_t)MTU2_PORT[tmp_pwm] & 0x00000020) == 0x00000020) {
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223 | obj->ch = 2;
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224 | } else if (((uint32_t)MTU2_PORT[tmp_pwm] & 0x00000010) == 0x00000010) {
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225 | obj->ch = 1;
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226 | } else {
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227 | obj->ch = 0;
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228 | }
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229 | // Wire pinout
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230 | pinmap_pinout(pin, PinMap_PWM);
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231 |
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232 | int bitmask = 1 << (pin & 0xf);
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233 |
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234 | *PMSR(PINGROUP(pin)) = (bitmask << 16) | 0;
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235 |
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236 | // default duty 0.0f
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237 | pwmout_write(obj, 0);
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238 | if (init_mtu2_period_ch[obj->ch] == 0) {
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239 | // default period 1ms
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240 | pwmout_period_us(obj, 1000);
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241 | init_mtu2_period_ch[obj->ch] = 1;
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242 | }
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243 | #endif
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244 | } else {
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245 | #ifdef FUNC_MOTOR_CTL_PWM
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246 | /* PWM */
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247 | // power on
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248 | CPGSTBCR3 &= ~(CPG_STBCR3_BIT_MSTP30);
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249 |
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250 | obj->pwm = pwm;
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251 | if (((uint32_t)PORT[obj->pwm] & 0x00000010) == 0x00000010) {
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252 | obj->ch = 2;
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253 | PWMPWPR_2 = 0x00;
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254 | } else {
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255 | obj->ch = 1;
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256 | PWMPWPR_1 = 0x00;
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257 | }
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258 |
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259 | // Wire pinout
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260 | pinmap_pinout(pin, PinMap_PWM);
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261 |
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262 | // default to 491us: standard for servos, and fine for e.g. brightness control
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263 | pwmout_write(obj, 0);
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264 | if ((obj->ch == 2) && (init_period_ch2 == 0)) {
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265 | pwmout_period_us(obj, 491);
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266 | init_period_ch2 = 1;
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267 | }
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268 | if ((obj->ch == 1) && (init_period_ch1 == 0)) {
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269 | pwmout_period_us(obj, 491);
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270 | init_period_ch1 = 1;
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271 | }
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272 | #endif
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273 | }
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274 | }
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275 |
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276 | void pwmout_free(pwmout_t* obj) {
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277 | pwmout_write(obj, 0);
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278 | mtu2_free();
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279 | }
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280 |
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281 | void pwmout_write(pwmout_t* obj, float value) {
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282 | uint32_t wk_cycle;
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283 |
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284 | if (obj->pwm >= MTU2_PWM_OFFSET) {
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285 | #ifdef FUMC_MTU2_PWM
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286 | /* PWM by MTU2 */
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287 | int tmp_pwm;
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288 |
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289 | if (value < 0.0f) {
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290 | value = 0.0f;
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291 | } else if (value > 1.0f) {
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292 | value = 1.0f;
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293 | } else {
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294 | // Do Nothing
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295 | }
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296 | tmp_pwm = (int)(obj->pwm - MTU2_PWM_OFFSET);
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297 | wk_cycle = *MTU2_PWM_MATCH[tmp_pwm][MTU2_PERIOD] & 0xffff;
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298 | // set channel match to percentage
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299 | if (value == 1.0f) {
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300 | *MTU2_PWM_MATCH[tmp_pwm][MTU2_PULSE] = (uint16_t)(wk_cycle - 1);
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301 | } else {
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302 | *MTU2_PWM_MATCH[tmp_pwm][MTU2_PULSE] = (uint16_t)((float)wk_cycle * value);
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303 | }
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304 | #endif
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305 | } else {
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306 | #ifdef FUNC_MOTOR_CTL_PWM
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307 | uint16_t v;
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308 |
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309 | /* PWM */
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310 | if (value < 0.0f) {
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311 | value = 0.0f;
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312 | } else if (value > 1.0f) {
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313 | value = 1.0f;
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314 | } else {
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315 | // Do Nothing
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316 | }
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317 |
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318 | if (obj->ch == 2) {
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319 | wk_cycle = PWMPWCYR_2 & 0x03ff;
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320 | } else {
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321 | wk_cycle = PWMPWCYR_1 & 0x03ff;
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322 | }
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323 |
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324 | // set channel match to percentage
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325 | v = (uint16_t)((float)wk_cycle * value);
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326 | *PWM_MATCH[obj->pwm] = (v | ((PORT[obj->pwm] & 1) << 12));
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327 | #endif
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328 | }
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329 | }
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330 |
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331 | float pwmout_read(pwmout_t* obj) {
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332 | uint32_t wk_cycle;
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333 | float value;
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334 |
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335 | if (obj->pwm >= MTU2_PWM_OFFSET) {
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336 | #ifdef FUMC_MTU2_PWM
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337 | /* PWM by MTU2 */
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338 | uint32_t wk_pulse;
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339 | int tmp_pwm;
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340 |
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341 | tmp_pwm = (int)(obj->pwm - MTU2_PWM_OFFSET);
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342 | wk_cycle = *MTU2_PWM_MATCH[tmp_pwm][MTU2_PERIOD] & 0xffff;
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343 | wk_pulse = *MTU2_PWM_MATCH[tmp_pwm][MTU2_PULSE] & 0xffff;
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344 | value = ((float)wk_pulse / (float)wk_cycle);
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345 | #endif
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346 | } else {
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347 | #ifdef FUNC_MOTOR_CTL_PWM
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348 | /* PWM */
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349 | if (obj->ch == 2) {
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350 | wk_cycle = PWMPWCYR_2 & 0x03ff;
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351 | } else {
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352 | wk_cycle = PWMPWCYR_1 & 0x03ff;
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353 | }
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354 | value = ((float)(*PWM_MATCH[obj->pwm] & 0x03ff) / (float)wk_cycle);
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355 | #endif
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356 | }
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357 |
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358 | return (value > 1.0f) ? (1.0f) : (value);
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359 | }
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360 |
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361 | void pwmout_period(pwmout_t* obj, float seconds) {
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362 | pwmout_period_us(obj, seconds * 1000000.0f);
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363 | }
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364 |
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365 | void pwmout_period_ms(pwmout_t* obj, int ms) {
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366 | pwmout_period_us(obj, ms * 1000);
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367 | }
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368 |
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369 | #ifdef FUNC_MOTOR_CTL_PWM
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370 | static void set_duty_again(__IO uint16_t *p_pwmpbfr, uint16_t last_cycle, uint16_t new_cycle){
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371 | uint16_t wk_pwmpbfr;
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372 | float value;
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373 | uint16_t v;
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374 |
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375 | wk_pwmpbfr = *p_pwmpbfr;
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376 | value = ((float)(wk_pwmpbfr & 0x03ff) / (float)last_cycle);
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377 | v = (uint16_t)((float)new_cycle * value);
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378 | *p_pwmpbfr = (v | (wk_pwmpbfr & 0x1000));
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379 | }
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380 | #endif
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381 |
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382 | #ifdef FUMC_MTU2_PWM
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383 | static void set_mtu2_duty_again(__IO uint16_t *p_pwmpbfr, uint16_t last_cycle, uint16_t new_cycle){
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384 | uint16_t wk_pwmpbfr;
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385 | float value;
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386 |
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387 | wk_pwmpbfr = *p_pwmpbfr;
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388 | value = ((float)(wk_pwmpbfr & 0xffff) / (float)last_cycle);
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389 | *p_pwmpbfr = (uint16_t)((float)new_cycle * value);
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390 | }
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391 | #endif
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392 |
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393 | // Set the PWM period, keeping the duty cycle the same.
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394 | void pwmout_period_us(pwmout_t* obj, int us) {
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395 | uint32_t pclk_base;
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396 | uint32_t wk_cycle;
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397 | uint32_t wk_cks = 0;
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398 | uint16_t wk_last_cycle;
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399 |
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400 | if (obj->pwm >= MTU2_PWM_OFFSET) {
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401 | #ifdef FUMC_MTU2_PWM
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402 | uint64_t wk_cycle_mtu2;
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403 | int max_us = 0;
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404 |
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405 | /* PWM by MTU2 */
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406 | int tmp_pwm;
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407 | uint8_t tmp_tcr_up;
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408 | uint8_t tmp_tstr_sp;
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409 | uint8_t tmp_tstr_st;
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410 |
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411 | max_us = MAX_PERIOD[obj->ch];
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412 | if (us > max_us) {
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413 | us = max_us;
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414 | } else if (us < 1) {
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415 | us = 1;
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416 | } else {
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417 | // Do Nothing
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418 | }
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419 |
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420 | if (RZ_A1_IsClockMode0() == false) {
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421 | pclk_base = (uint32_t)CM1_RENESAS_RZ_A1_P0_CLK;
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422 | } else {
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423 | pclk_base = (uint32_t)CM0_RENESAS_RZ_A1_P0_CLK;
|
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424 | }
|
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425 |
|
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426 | wk_cycle_mtu2 = (uint64_t)pclk_base * us;
|
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427 | while (wk_cycle_mtu2 >= 65535000000) {
|
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428 | if ((obj->ch == 1) && (wk_cks == 3)) {
|
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429 | wk_cks+=2;
|
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430 | } else if ((obj->ch == 2) && (wk_cks == 3)) {
|
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431 | wk_cycle_mtu2 >>= 2;
|
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432 | wk_cks+=3;
|
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433 | }
|
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434 | wk_cycle_mtu2 >>= 2;
|
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435 | wk_cks++;
|
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436 | }
|
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437 | wk_cycle = (uint32_t)(wk_cycle_mtu2 / 1000000);
|
---|
438 |
|
---|
439 | tmp_pwm = (int)(obj->pwm - MTU2_PWM_OFFSET);
|
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440 | if (((uint8_t)MTU2_PORT[tmp_pwm] & 0x02) == 0x02) {
|
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441 | tmp_tcr_up = 0xC0;
|
---|
442 | } else {
|
---|
443 | tmp_tcr_up = 0x40;
|
---|
444 | }
|
---|
445 | if ((obj->ch == 4) || (obj->ch == 3)) {
|
---|
446 | tmp_tstr_sp = ~(0x38 | (1 << (obj->ch + 3)));
|
---|
447 | tmp_tstr_st = (1 << (obj->ch + 3));
|
---|
448 | } else {
|
---|
449 | tmp_tstr_sp = ~(0x38 | (1 << obj->ch));
|
---|
450 | tmp_tstr_st = (1 << obj->ch);
|
---|
451 | }
|
---|
452 | // Counter Stop
|
---|
453 | MTU2TSTR &= tmp_tstr_sp;
|
---|
454 | wk_last_cycle = *MTU2_PWM_MATCH[tmp_pwm][MTU2_PERIOD] & 0xffff;
|
---|
455 | *TCR_MATCH[obj->ch] = tmp_tcr_up | wk_cks;
|
---|
456 | *TIORH_MATCH[obj->ch] = 0x21;
|
---|
457 | if ((obj->ch == 0) || (obj->ch == 3) || (obj->ch == 4)) {
|
---|
458 | *TIORL_MATCH[obj->ch] = 0x21;
|
---|
459 | }
|
---|
460 | *MTU2_PWM_MATCH[tmp_pwm][MTU2_PERIOD] = (uint16_t)wk_cycle; // Set period
|
---|
461 |
|
---|
462 | // Set duty again(TGRA)
|
---|
463 | set_mtu2_duty_again(TGRA_MATCH[obj->ch], wk_last_cycle, wk_cycle);
|
---|
464 | if ((obj->ch == 0) || (obj->ch == 3) || (obj->ch == 4)) {
|
---|
465 | // Set duty again(TGRC)
|
---|
466 | set_mtu2_duty_again(TGRC_MATCH[obj->ch], wk_last_cycle, wk_cycle);
|
---|
467 | }
|
---|
468 | *TMDR_MATCH[obj->ch] = 0x02; // PWM mode 1
|
---|
469 |
|
---|
470 | // Counter Start
|
---|
471 | MTU2TSTR |= tmp_tstr_st;
|
---|
472 | // Save for future use
|
---|
473 | mtu2_period_ch[obj->ch] = us;
|
---|
474 | #endif
|
---|
475 | } else {
|
---|
476 | #ifdef FUNC_MOTOR_CTL_PWM
|
---|
477 | /* PWM */
|
---|
478 | if (us > 491) {
|
---|
479 | us = 491;
|
---|
480 | } else if (us < 1) {
|
---|
481 | us = 1;
|
---|
482 | } else {
|
---|
483 | // Do Nothing
|
---|
484 | }
|
---|
485 |
|
---|
486 | if (RZ_A1_IsClockMode0() == false) {
|
---|
487 | pclk_base = (uint32_t)CM1_RENESAS_RZ_A1_P0_CLK / 10000;
|
---|
488 | } else {
|
---|
489 | pclk_base = (uint32_t)CM0_RENESAS_RZ_A1_P0_CLK / 10000;
|
---|
490 | }
|
---|
491 |
|
---|
492 | wk_cycle = pclk_base * us;
|
---|
493 | while (wk_cycle >= 102350) {
|
---|
494 | wk_cycle >>= 1;
|
---|
495 | wk_cks++;
|
---|
496 | }
|
---|
497 | wk_cycle = (wk_cycle + 50) / 100;
|
---|
498 |
|
---|
499 | if (obj->ch == 2) {
|
---|
500 | wk_last_cycle = PWMPWCYR_2 & 0x03ff;
|
---|
501 | PWMPWCR_2 = 0xc0 | wk_cks;
|
---|
502 | PWMPWCYR_2 = (uint16_t)wk_cycle;
|
---|
503 |
|
---|
504 | // Set duty again
|
---|
505 | set_duty_again(&PWMPWBFR_2A, wk_last_cycle, wk_cycle);
|
---|
506 | set_duty_again(&PWMPWBFR_2C, wk_last_cycle, wk_cycle);
|
---|
507 | set_duty_again(&PWMPWBFR_2E, wk_last_cycle, wk_cycle);
|
---|
508 | set_duty_again(&PWMPWBFR_2G, wk_last_cycle, wk_cycle);
|
---|
509 |
|
---|
510 | // Counter Start
|
---|
511 | PWMPWCR_2 |= 0x08;
|
---|
512 |
|
---|
513 | // Save for future use
|
---|
514 | period_ch2 = us;
|
---|
515 | } else {
|
---|
516 | wk_last_cycle = PWMPWCYR_1 & 0x03ff;
|
---|
517 | PWMPWCR_1 = 0xc0 | wk_cks;
|
---|
518 | PWMPWCYR_1 = (uint16_t)wk_cycle;
|
---|
519 |
|
---|
520 | // Set duty again
|
---|
521 | set_duty_again(&PWMPWBFR_1A, wk_last_cycle, wk_cycle);
|
---|
522 | set_duty_again(&PWMPWBFR_1C, wk_last_cycle, wk_cycle);
|
---|
523 | set_duty_again(&PWMPWBFR_1E, wk_last_cycle, wk_cycle);
|
---|
524 | set_duty_again(&PWMPWBFR_1G, wk_last_cycle, wk_cycle);
|
---|
525 |
|
---|
526 | // Counter Start
|
---|
527 | PWMPWCR_1 |= 0x08;
|
---|
528 |
|
---|
529 | // Save for future use
|
---|
530 | period_ch1 = us;
|
---|
531 | }
|
---|
532 | #endif
|
---|
533 | }
|
---|
534 | }
|
---|
535 |
|
---|
536 | void pwmout_pulsewidth(pwmout_t* obj, float seconds) {
|
---|
537 | pwmout_pulsewidth_us(obj, seconds * 1000000.0f);
|
---|
538 | }
|
---|
539 |
|
---|
540 | void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) {
|
---|
541 | pwmout_pulsewidth_us(obj, ms * 1000);
|
---|
542 | }
|
---|
543 |
|
---|
544 | void pwmout_pulsewidth_us(pwmout_t* obj, int us) {
|
---|
545 | float value = 0;
|
---|
546 |
|
---|
547 | if (obj->pwm >= MTU2_PWM_OFFSET) {
|
---|
548 | #ifdef FUMC_MTU2_PWM
|
---|
549 | /* PWM by MTU2 */
|
---|
550 | if (mtu2_period_ch[obj->ch] != 0) {
|
---|
551 | value = (float)us / (float)mtu2_period_ch[obj->ch];
|
---|
552 | }
|
---|
553 | #endif
|
---|
554 | } else {
|
---|
555 | #ifdef FUNC_MOTOR_CTL_PWM
|
---|
556 | /* PWM */
|
---|
557 | if (obj->ch == 2) {
|
---|
558 | if (period_ch2 != 0) {
|
---|
559 | value = (float)us / (float)period_ch2;
|
---|
560 | }
|
---|
561 | } else {
|
---|
562 | if (period_ch1 != 0) {
|
---|
563 | value = (float)us / (float)period_ch1;
|
---|
564 | }
|
---|
565 | }
|
---|
566 | #endif
|
---|
567 | }
|
---|
568 | pwmout_write(obj, value);
|
---|
569 | }
|
---|