[374] | 1 | /* mbed Microcontroller Library
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| 2 | * Copyright (c) 2006-2017 ARM Limited
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| 3 | *
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| 4 | * Licensed under the Apache License, Version 2.0 (the "License");
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| 5 | * you may not use this file except in compliance with the License.
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| 6 | * You may obtain a copy of the License at
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| 7 | *
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| 8 | * http://www.apache.org/licenses/LICENSE-2.0
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| 9 | *
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| 10 | * Unless required by applicable law or agreed to in writing, software
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| 11 | * distributed under the License is distributed on an "AS IS" BASIS,
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| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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| 13 | * See the License for the specific language governing permissions and
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| 14 | * limitations under the License.
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| 15 | */
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| 16 | #if DEVICE_LPTICKER
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| 17 | #include "lp_ticker_api.h"
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| 18 | #include "mtu2_iodefine.h"
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| 19 | #include "mtu2_iobitmask.h"
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| 20 | #include "mbed_drv_cfg.h"
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| 21 | #include "mtu2.h"
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| 22 |
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| 23 | #if (LP_TICKER_MTU2_CH == 2)
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| 24 | #define LP_TICKER_TIMER_IRQn (TGI2A_IRQn)
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| 25 | #define MTU2TCR (MTU2TCR_2)
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| 26 | #define MTU2TCNT (MTU2TCNT_2)
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| 27 | #define MTU2TIER (MTU2TIER_2)
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| 28 | #define MTU2TGRA (MTU2TGRA_2)
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| 29 | #define MTU2TSR (MTU2TSR_2)
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| 30 | #define MTU2_TSTR_CST MTU2_TSTR_CST2
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| 31 | #define MTU2_TCR_TPSC (0x07)
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| 32 | #elif (LP_TICKER_MTU2_CH == 3)
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| 33 | #define LP_TICKER_TIMER_IRQn (TGI3A_IRQn)
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| 34 | #define MTU2TCR (MTU2TCR_3)
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| 35 | #define MTU2TCNT (MTU2TCNT_3)
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| 36 | #define MTU2TIER (MTU2TIER_3)
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| 37 | #define MTU2TGRA (MTU2TGRA_3)
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| 38 | #define MTU2TSR (MTU2TSR_3)
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| 39 | #define MTU2_TSTR_CST MTU2_TSTR_CST3
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| 40 | #define MTU2_TCR_TPSC (0x05)
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| 41 | #elif (LP_TICKER_MTU2_CH == 4)
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| 42 | #define LP_TICKER_TIMER_IRQn (TGI4A_IRQn)
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| 43 | #define MTU2TCR (MTU2TCR_4)
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| 44 | #define MTU2TCNT (MTU2TCNT_4)
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| 45 | #define MTU2TIER (MTU2TIER_4)
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| 46 | #define MTU2TGRA (MTU2TGRA_4)
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| 47 | #define MTU2TSR (MTU2TSR_4)
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| 48 | #define MTU2_TSTR_CST MTU2_TSTR_CST4
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| 49 | #define MTU2_TCR_TPSC (0x05)
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| 50 | #else
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| 51 | #error "Invalid number : LP_TICKER_MTU2_CH (2-4)"
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| 52 | #endif
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| 53 |
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| 54 | static int lp_ticker_inited = 0;
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| 55 |
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| 56 | void lp_ticker_init(void)
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| 57 | {
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| 58 | GIC_DisableIRQ(LP_TICKER_TIMER_IRQn);
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| 59 | GIC_ClearPendingIRQ(LP_TICKER_TIMER_IRQn);
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| 60 |
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| 61 | /* Power Control for Peripherals */
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| 62 | mtu2_init();
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| 63 |
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| 64 | if (lp_ticker_inited) return;
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| 65 | lp_ticker_inited = 1;
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| 66 |
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| 67 | MTU2TCR = MTU2_TCR_TPSC;
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| 68 | MTU2TSTR |= MTU2_TSTR_CST;
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| 69 | MTU2TIER |= MTU2_TIER_n_TGIEA;
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| 70 |
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| 71 | // INTC settings
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| 72 | InterruptHandlerRegister(LP_TICKER_TIMER_IRQn, (void (*)(uint32_t))lp_ticker_irq_handler);
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| 73 | GIC_SetPriority(LP_TICKER_TIMER_IRQn, 5);
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| 74 | GIC_SetConfiguration(LP_TICKER_TIMER_IRQn, 3);
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| 75 | }
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| 76 |
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| 77 | void lp_ticker_free(void)
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| 78 | {
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| 79 | GIC_DisableIRQ(LP_TICKER_TIMER_IRQn);
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| 80 | GIC_ClearPendingIRQ(LP_TICKER_TIMER_IRQn);
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| 81 |
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| 82 | MTU2TIER &= ~MTU2_TIER_n_TGIEA;
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| 83 | lp_ticker_inited = 0;
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| 84 | mtu2_free();
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| 85 | }
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| 86 |
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| 87 | uint32_t lp_ticker_read()
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| 88 | {
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| 89 | return (uint32_t)MTU2TCNT;
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| 90 | }
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| 91 |
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| 92 | void lp_ticker_set_interrupt(timestamp_t timestamp)
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| 93 | {
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| 94 | MTU2TSR = (MTU2TSR & 0xFE);
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| 95 | MTU2TGRA = (uint16_t)timestamp;
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| 96 | GIC_EnableIRQ(LP_TICKER_TIMER_IRQn);
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| 97 | }
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| 98 |
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| 99 | void lp_ticker_fire_interrupt(void)
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| 100 | {
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| 101 | GIC_SetPendingIRQ(LP_TICKER_TIMER_IRQn);
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| 102 | GIC_EnableIRQ(LP_TICKER_TIMER_IRQn);
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| 103 | }
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| 104 |
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| 105 | void lp_ticker_disable_interrupt(void)
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| 106 | {
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| 107 | GIC_DisableIRQ(LP_TICKER_TIMER_IRQn);
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| 108 | }
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| 109 |
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| 110 | void lp_ticker_clear_interrupt(void)
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| 111 | {
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| 112 | MTU2TSR = (MTU2TSR & 0xFE);
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| 113 | GIC_ClearPendingIRQ(LP_TICKER_TIMER_IRQn);
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| 114 | }
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| 115 |
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| 116 | const ticker_info_t* lp_ticker_get_info()
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| 117 | {
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| 118 | static const ticker_info_t info = {
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| 119 | (uint32_t)((float)RENESAS_RZ_A1_P0_CLK / 1024.0f + 0.5f),
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| 120 | 16
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| 121 | };
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| 122 | return &info;
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| 123 | }
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| 124 |
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| 125 | #endif // DEVICE_LPTICKER
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