1 | /* mbed Microcontroller Library
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2 | * Copyright (c) 2018 ARM Limited
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3 | *
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4 | * Licensed under the Apache License, Version 2.0 (the "License");
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5 | * you may not use this file except in compliance with the License.
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6 | * You may obtain a copy of the License at
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7 | *
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8 | * http://www.apache.org/licenses/LICENSE-2.0
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9 | *
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10 | * Unless required by applicable law or agreed to in writing, software
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11 | * distributed under the License is distributed on an "AS IS" BASIS,
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12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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13 | * See the License for the specific language governing permissions and
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14 | * limitations under the License.
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15 | */
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16 |
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17 | #include "flash_api.h"
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18 | #include "mbed_critical.h"
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19 |
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20 | #if DEVICE_FLASH
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21 | #include "iodefine.h"
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22 | #include "spibsc_iobitmask.h"
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23 | #include "spibsc.h"
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24 | #include "mbed_drv_cfg.h"
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25 |
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26 | /* ---- serial flash command ---- */
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27 | #define SFLASHCMD_SECTOR_ERASE (0x20u) /* SE 3-byte address(1bit) */
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28 | #define SFLASHCMD_PAGE_PROGRAM (0x02u) /* PP 3-byte address(1bit), data(1bit) */
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29 | #define SFLASHCMD_READ_STATUS_REG (0x05u) /* RDSR data(1bit) */
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30 | #define SFLASHCMD_WRITE_ENABLE (0x06u) /* WREN */
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31 | /* ---- serial flash register definitions ---- */
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32 | #define STREG_BUSY_BIT (0x01u) /* SR.[0]BUSY Erase/Write In Progress (RO) */
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33 |
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34 | /* Definition of the base address for the MMU translation table */
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35 | #if defined(__CC_ARM) || defined(__GNUC__)
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36 | extern uint32_t Image$$TTB$$ZI$$Base;
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37 | #define TTB ((uint32_t)&Image$$TTB$$ZI$$Base) /* using linker symbol */
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38 | #elif defined(__ICCARM__)
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39 | #pragma section="TTB"
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40 | #define TTB ((uint32_t)__section_begin("TTB"))
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41 | #endif
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42 |
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43 | typedef struct {
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44 | uint32_t cdb; /* bit-width : command */
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45 | uint32_t ocdb; /* bit-width : optional command */
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46 | uint32_t adb; /* bit-width : address */
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47 | uint32_t opdb; /* bit-width : option data */
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48 | uint32_t spidb; /* bit-width : data */
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49 |
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50 | uint32_t cde; /* Enable : command */
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51 | uint32_t ocde; /* Enable : optional command */
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52 | uint32_t ade; /* Enable : address */
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53 | uint32_t opde; /* Enable : option data */
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54 | uint32_t spide; /* Enable : data */
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55 |
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56 | uint32_t sslkp; /* SPBSSL level */
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57 | uint32_t spire; /* Enable data read */
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58 | uint32_t spiwe; /* Enable data write */
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59 |
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60 | uint32_t dme; /* Enable : dummy cycle */
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61 |
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62 | uint32_t addre; /* DDR enable : address */
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63 | uint32_t opdre; /* DDR enable : option data */
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64 | uint32_t spidre; /* DDR enable : data */
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65 |
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66 | uint8_t dmdb; /* bit-width : dummy cycle */
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67 | uint8_t dmcyc; /* number of dummy cycles */
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68 |
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69 | uint8_t cmd; /* command */
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70 | uint8_t ocmd; /* optional command */
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71 | uint32_t addr; /* address */
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72 | uint8_t opd[4]; /* option data 3/2/1/0 */
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73 | uint32_t smrdr[2]; /* read data */
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74 | uint32_t smwdr[2]; /* write data */
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75 | } st_spibsc_spimd_reg_t;
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76 |
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77 | /* SPI Multi-I/O bus address space address definitions */
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78 | #define SPIBSC_ADDR_START (0x18000000uL)
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79 | #define SPIBSC_ADDR_END (0x1BFFFFFFuL)
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80 |
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81 | typedef struct {
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82 | uint32_t b0 : 1 ; /* bit 0 : - (0) */
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83 | uint32_t b1 : 1 ; /* bit 1 : - (1) */
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84 | uint32_t B : 1 ; /* bit 2 : B Memory region attribute bit */
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85 | uint32_t C : 1 ; /* bit 3 : C Memory region attribute bit */
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86 | uint32_t XN : 1 ; /* bit 4 : XN Execute-never bit */
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87 | uint32_t Domain : 4 ; /* bit 8-5 : Domain Domain field */
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88 | uint32_t b9 : 1 ; /* bit 9 : IMP IMPLEMENTATION DEFINED */
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89 | uint32_t AP1_0 : 2 ; /* bit 11-10 : AP[1:0] Access permissions bits:bit1-0 */
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90 | uint32_t TEX : 3 ; /* bit 14-12 : TEX[2:0] Memory region attribute bits */
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91 | uint32_t AP2 : 1 ; /* bit 15 : AP[2] Access permissions bits:bit2 */
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92 | uint32_t S : 1 ; /* bit 16 : S Shareable bit */
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93 | uint32_t nG : 1 ; /* bit 17 : nG Not global bit */
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94 | uint32_t b18 : 1 ; /* bit 18 : - (0) */
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95 | uint32_t NS : 1 ; /* bit 19 : NS Non-secure bit */
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96 | uint32_t base_addr : 12; /* bit 31-20 : PA[31:20] PA(physical address) bits:bit31-20 */
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97 | } mmu_ttbl_desc_section_t;
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98 |
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99 | static mmu_ttbl_desc_section_t desc_tbl[(SPIBSC_ADDR_END >> 20) - (SPIBSC_ADDR_START >> 20) + 1];
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100 | static volatile struct st_spibsc* SPIBSC = &SPIBSC0;
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101 | static st_spibsc_spimd_reg_t spimd_reg;
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102 |
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103 | #if defined(__ICCARM__)
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104 | #define RAM_CODE_SEC __ramfunc
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105 | #else
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106 | #define RAM_CODE_SEC __attribute__((section("RAM_CODE")))
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107 | #endif
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108 |
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109 | /* Global function for optimization */
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110 | RAM_CODE_SEC int32_t _sector_erase(uint32_t addr);
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111 | RAM_CODE_SEC int32_t _page_program(uint32_t addr, const uint8_t * buf, int32_t size);
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112 |
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113 | static RAM_CODE_SEC int32_t write_enable(void);
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114 | static RAM_CODE_SEC int32_t busy_wait(void);
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115 | static RAM_CODE_SEC int32_t read_register(uint8_t cmd, uint8_t * status);
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116 | static RAM_CODE_SEC int32_t data_send(uint32_t bit_width, uint32_t spbssl_level, const uint8_t * buf, int32_t size);
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117 | static RAM_CODE_SEC void spi_mode(void);
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118 | static RAM_CODE_SEC void ex_mode(void);
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119 | static RAM_CODE_SEC void clear_spimd_reg(st_spibsc_spimd_reg_t * regset);
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120 | static RAM_CODE_SEC int32_t spibsc_transfer(st_spibsc_spimd_reg_t * regset);
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121 | static RAM_CODE_SEC uint32_t RegRead_32(volatile uint32_t * ioreg, uint32_t shift, uint32_t mask);
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122 | static RAM_CODE_SEC void RegWwrite_32(volatile uint32_t * ioreg, uint32_t write_value, uint32_t shift, uint32_t mask);
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123 | static RAM_CODE_SEC void change_mmu_ttbl_spibsc(uint32_t type);
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124 | static RAM_CODE_SEC void spibsc_stop(void);
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125 | static RAM_CODE_SEC void cache_control(void);
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126 |
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127 | int32_t flash_init(flash_t *obj)
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128 | {
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129 | return 0;
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130 | }
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131 |
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132 | int32_t flash_free(flash_t *obj)
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133 | {
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134 | return 0;
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135 | }
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136 |
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137 | int32_t flash_erase_sector(flash_t *obj, uint32_t address)
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138 | {
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139 | int32_t ret;
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140 |
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141 | core_util_critical_section_enter();
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142 | ret = _sector_erase(address - FLASH_BASE);
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143 | core_util_critical_section_exit();
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144 |
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145 | return ret;
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146 | }
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147 |
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148 | int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, uint32_t size)
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149 | {
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150 | int32_t ret;
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151 |
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152 | core_util_critical_section_enter();
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153 | ret = _page_program(address - FLASH_BASE, data, size);
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154 | core_util_critical_section_exit();
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155 |
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156 | return ret;
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157 | }
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158 |
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159 | uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address)
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160 | {
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161 | if ((address >= (FLASH_BASE + FLASH_SIZE)) || (address < FLASH_BASE)) {
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162 | return MBED_FLASH_INVALID_SIZE;
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163 | }
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164 |
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165 | return FLASH_SECTOR_SIZE;
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166 | }
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167 |
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168 | uint32_t flash_get_page_size(const flash_t *obj)
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169 | {
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170 | return 1;
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171 | }
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172 |
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173 | uint32_t flash_get_start_address(const flash_t *obj)
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174 | {
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175 | return FLASH_BASE;
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176 | }
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177 |
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178 | uint32_t flash_get_size(const flash_t *obj)
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179 | {
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180 | return FLASH_SIZE;
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181 | }
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182 |
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183 | int32_t _sector_erase(uint32_t addr)
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184 | {
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185 | int32_t ret;
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186 |
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187 | spi_mode();
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188 |
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189 | /* ---- Write enable ---- */
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190 | ret = write_enable(); /* WREN Command */
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191 | if (ret != 0) {
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192 | ex_mode();
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193 | return ret;
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194 | }
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195 |
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196 | /* ---- spimd_reg init ---- */
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197 | clear_spimd_reg(&spimd_reg);
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198 |
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199 | /* ---- command ---- */
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200 | spimd_reg.cde = SPIBSC_OUTPUT_ENABLE;
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201 | spimd_reg.cdb = SPIBSC_1BIT;
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202 | spimd_reg.cmd = SFLASHCMD_SECTOR_ERASE;
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203 |
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204 | /* ---- address ---- */
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205 | spimd_reg.ade = SPIBSC_OUTPUT_ADDR_24;
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206 | spimd_reg.addre = SPIBSC_SDR_TRANS; /* SDR */
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207 | spimd_reg.adb = SPIBSC_1BIT;
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208 | spimd_reg.addr = addr;
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209 |
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210 | ret = spibsc_transfer(&spimd_reg);
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211 | if (ret != 0) {
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212 | ex_mode();
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213 | return ret;
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214 | }
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215 |
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216 | ret = busy_wait();
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217 |
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218 | ex_mode();
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219 | return ret;
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220 | }
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221 |
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222 | int32_t _page_program(uint32_t addr, const uint8_t * buf, int32_t size)
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223 | {
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224 | int32_t ret;
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225 | int32_t program_size;
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226 | int32_t remainder;
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227 | int32_t idx = 0;
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228 |
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229 | spi_mode();
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230 |
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231 | while (size > 0) {
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232 | if (size > FLASH_PAGE_SIZE) {
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233 | program_size = FLASH_PAGE_SIZE;
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234 | } else {
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235 | program_size = size;
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236 | }
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237 | remainder = FLASH_PAGE_SIZE - (addr % FLASH_PAGE_SIZE);
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238 | if ((remainder != 0) && (program_size > remainder)) {
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239 | program_size = remainder;
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240 | }
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241 |
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242 | /* ---- Write enable ---- */
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243 | ret = write_enable(); /* WREN Command */
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244 | if (ret != 0) {
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245 | ex_mode();
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246 | return ret;
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247 | }
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248 |
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249 | /* ----------- 1. Command, Address ---------------*/
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250 | /* ---- spimd_reg init ---- */
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251 | clear_spimd_reg(&spimd_reg);
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252 |
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253 | /* ---- command ---- */
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254 | spimd_reg.cde = SPIBSC_OUTPUT_ENABLE;
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255 | spimd_reg.cdb = SPIBSC_1BIT;
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256 | spimd_reg.cmd = SFLASHCMD_PAGE_PROGRAM;
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257 |
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258 | /* ---- address ---- */
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259 | spimd_reg.ade = SPIBSC_OUTPUT_ADDR_24;
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260 | spimd_reg.addre = SPIBSC_SDR_TRANS; /* SDR */
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261 | spimd_reg.adb = SPIBSC_1BIT;
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262 | spimd_reg.addr = addr;
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263 |
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264 | /* ---- Others ---- */
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265 | spimd_reg.sslkp = SPIBSC_SPISSL_KEEP; /* SPBSSL level */
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266 |
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267 | ret = spibsc_transfer(&spimd_reg); /* Command,Address */
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268 | if (ret != 0) {
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269 | ex_mode();
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270 | return ret;
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271 | }
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272 |
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273 | /* ----------- 2. Data ---------------*/
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274 | ret = data_send(SPIBSC_1BIT, SPIBSC_SPISSL_NEGATE, &buf[idx], program_size);
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275 | if (ret != 0) {
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276 | ex_mode();
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277 | return ret;
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278 | }
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279 |
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280 | ret = busy_wait();
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281 | if (ret != 0) {
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282 | ex_mode();
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283 | return ret;
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284 | }
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285 |
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286 | addr += program_size;
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287 | idx += program_size;
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288 | size -= program_size;
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289 | }
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290 |
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291 | ex_mode();
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292 | return ret;
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293 | }
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294 |
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295 | static int32_t write_enable(void)
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296 | {
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297 | int32_t ret;
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298 |
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299 | /* ---- spimd_reg init ---- */
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300 | clear_spimd_reg(&spimd_reg);
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301 |
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302 | /* ---- command ---- */
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303 | spimd_reg.cde = SPIBSC_OUTPUT_ENABLE;
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304 | spimd_reg.cdb = SPIBSC_1BIT;
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305 | spimd_reg.cmd = SFLASHCMD_WRITE_ENABLE;
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306 |
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307 | ret = spibsc_transfer(&spimd_reg);
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308 |
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309 | return ret;
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310 | }
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311 |
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312 | static int32_t busy_wait(void)
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313 | {
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314 | int32_t ret;
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315 | uint8_t st_reg;
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316 |
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317 | while (1) {
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318 | ret = read_register(SFLASHCMD_READ_STATUS_REG, &st_reg);
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319 | if (ret != 0) {
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320 | break;
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321 | }
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322 | if ((st_reg & STREG_BUSY_BIT) == 0) {
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323 | break;
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324 | }
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325 | }
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326 |
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327 | return ret;
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328 | }
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329 |
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330 | static int32_t read_register(uint8_t cmd, uint8_t * status)
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331 | {
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332 | int32_t ret;
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333 |
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334 | /* ---- spimd_reg init ---- */
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335 | clear_spimd_reg(&spimd_reg);
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336 |
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337 | /* ---- command ---- */
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338 | spimd_reg.cde = SPIBSC_OUTPUT_ENABLE;
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339 | spimd_reg.cdb = SPIBSC_1BIT;
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340 | spimd_reg.cmd = cmd;
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341 |
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342 | /* ---- Others ---- */
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343 | spimd_reg.sslkp = SPIBSC_SPISSL_NEGATE; /* SPBSSL level */
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344 | spimd_reg.spire = SPIBSC_SPIDATA_ENABLE; /* read enable/disable */
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345 | spimd_reg.spiwe = SPIBSC_SPIDATA_ENABLE; /* write enable/disable */
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346 |
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347 | /* ---- data ---- */
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348 | spimd_reg.spide = SPIBSC_OUTPUT_SPID_8; /* Enable(8bit) */
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349 | spimd_reg.spidre = SPIBSC_SDR_TRANS; /* SDR */
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350 | spimd_reg.spidb = SPIBSC_1BIT;
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351 | spimd_reg.smwdr[0] = 0x00; /* Output 0 in read status */
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352 | spimd_reg.smwdr[1] = 0x00; /* Output 0 in read status */
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353 |
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354 | ret = spibsc_transfer(&spimd_reg);
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355 | if (ret == 0) {
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356 | *status = (uint8_t)(spimd_reg.smrdr[0]); /* Data[7:0] */
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357 | }
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358 |
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359 | return ret;
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360 | }
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361 |
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362 | static int32_t data_send(uint32_t bit_width, uint32_t spbssl_level, const uint8_t * buf, int32_t size)
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363 | {
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364 | int32_t ret = 0;
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365 | int32_t unit;
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366 | uint8_t *buf_b;
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367 | uint16_t *buf_s;
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368 | uint32_t *buf_l;
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369 |
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370 | /* ---- spimd_reg init ---- */
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371 | clear_spimd_reg(&spimd_reg);
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372 |
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373 | /* ---- Others ---- */
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374 | spimd_reg.sslkp = SPIBSC_SPISSL_KEEP; /* SPBSSL level */
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375 | spimd_reg.spiwe = SPIBSC_SPIDATA_ENABLE; /* write enable/disable */
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376 |
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377 | /* ---- data ---- */
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378 | spimd_reg.spidb = bit_width;
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379 | spimd_reg.spidre= SPIBSC_SDR_TRANS; /* SDR */
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380 |
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381 | if (((uint32_t)size & 0x3) == 0) {
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382 | spimd_reg.spide = SPIBSC_OUTPUT_SPID_32; /* Enable(32bit) */
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383 | unit = 4;
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384 | } else if (((uint32_t)size & 0x1) == 0) {
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385 | spimd_reg.spide = SPIBSC_OUTPUT_SPID_16; /* Enable(16bit) */
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386 | unit = 2;
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387 | } else {
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388 | spimd_reg.spide = SPIBSC_OUTPUT_SPID_8; /* Enable(8bit) */
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389 | unit = 1;
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390 | }
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391 |
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392 | while (size > 0) {
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393 | if (unit == 1) {
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394 | buf_b = (uint8_t *)buf;
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395 | spimd_reg.smwdr[0] = (uint32_t)(((uint32_t)*buf_b) & 0x000000FF);
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396 | } else if (unit == 2) {
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397 | buf_s = (uint16_t *)buf;
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398 | spimd_reg.smwdr[0] = (uint32_t)(((uint32_t)*buf_s) & 0x0000FFFF);
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399 | } else if (unit == 4) {
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400 | buf_l = (uint32_t *)buf;
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401 | spimd_reg.smwdr[0] = (uint32_t)(((uint32_t)(*buf_l)) & 0xfffffffful);
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402 | } else {
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403 | /* Do Nothing */
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404 | }
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405 |
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406 | buf += unit;
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407 | size -= unit;
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408 |
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409 | if (size <= 0) {
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410 | spimd_reg.sslkp = spbssl_level;
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411 | }
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412 |
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413 | ret = spibsc_transfer(&spimd_reg); /* Data */
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414 | if (ret != 0) {
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415 | return ret;
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416 | }
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417 | }
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418 |
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419 | return ret;
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420 | }
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421 |
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422 | static void spi_mode(void)
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423 | {
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424 | volatile uint32_t dummy_read_32;
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425 |
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426 | if (RegRead_32(&SPIBSC->CMNCR, SPIBSC_CMNCR_MD_SHIFT, SPIBSC_CMNCR_MD) != SPIBSC_CMNCR_MD_SPI) {
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427 | /* ==== Change the MMU translation table SPI Multi-I/O bus space settings
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428 | for use in SPI operating mode ==== */
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429 | change_mmu_ttbl_spibsc(0);
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430 |
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431 | /* ==== Cleaning and invalidation of cache ==== */
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432 | cache_control();
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433 |
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434 | /* ==== Switch to SPI operating mode ==== */
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435 | spibsc_stop();
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436 |
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437 | dummy_read_32 = SPIBSC->CMNCR; /* dummy read */
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438 | /* SPI Mode */
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439 | RegWwrite_32(&SPIBSC->CMNCR, SPIBSC_CMNCR_MD_SPI, SPIBSC_CMNCR_MD_SHIFT, SPIBSC_CMNCR_MD);
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440 | dummy_read_32 = SPIBSC->CMNCR; /* dummy read */
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441 |
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442 | }
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443 | (void)dummy_read_32;
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444 | }
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445 |
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446 | static void ex_mode(void)
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447 | {
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448 | volatile uint32_t dummy_read_32;
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449 |
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450 | if (RegRead_32(&SPIBSC->CMNCR, SPIBSC_CMNCR_MD_SHIFT, SPIBSC_CMNCR_MD) != SPIBSC_CMNCR_MD_EXTRD) {
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451 | /* ==== Switch to external address space read mode and clear SPIBSC read cache ==== */
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452 | spibsc_stop();
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453 |
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454 | /* Flush SPIBSC's read cache */
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455 | RegWwrite_32(&SPIBSC->DRCR, SPIBSC_DRCR_RCF_EXE, SPIBSC_DRCR_RCF_SHIFT, SPIBSC_DRCR_RCF);
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456 | dummy_read_32 = SPIBSC->DRCR; /* dummy read */
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457 |
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458 | /* External address space read mode */
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459 | RegWwrite_32(&SPIBSC->CMNCR, SPIBSC_CMNCR_MD_EXTRD, SPIBSC_CMNCR_MD_SHIFT, SPIBSC_CMNCR_MD);
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460 | dummy_read_32 = SPIBSC->CMNCR; /* dummy read */
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461 |
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462 | /* ==== Change the MMU translation table SPI Multi-I/O bus space settings
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463 | for use in external address space read mode ==== */
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464 | change_mmu_ttbl_spibsc(1);
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465 |
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466 | /* ==== Cleaning and invalidation of cache ==== */
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467 | cache_control();
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468 | }
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469 | (void)dummy_read_32;
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470 | }
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471 |
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472 | static void clear_spimd_reg(st_spibsc_spimd_reg_t * regset)
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473 | {
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474 | /* ---- command ---- */
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475 | regset->cde = SPIBSC_OUTPUT_DISABLE;
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476 | regset->cdb = SPIBSC_1BIT;
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477 | regset->cmd = 0x00;
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478 |
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479 | /* ---- optional command ---- */
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480 | regset->ocde = SPIBSC_OUTPUT_DISABLE;
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481 | regset->ocdb = SPIBSC_1BIT;
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482 | regset->ocmd = 0x00;
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483 |
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484 | /* ---- address ---- */
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485 | regset->ade = SPIBSC_OUTPUT_DISABLE;
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486 | regset->addre = SPIBSC_SDR_TRANS; /* SDR */
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487 | regset->adb = SPIBSC_1BIT;
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488 | regset->addr = 0x00000000;
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489 |
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490 | /* ---- option data ---- */
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491 | regset->opde = SPIBSC_OUTPUT_DISABLE;
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492 | regset->opdre = SPIBSC_SDR_TRANS; /* SDR */
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493 | regset->opdb = SPIBSC_1BIT;
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494 | regset->opd[0] = 0x00; /* OPD3 */
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495 | regset->opd[1] = 0x00; /* OPD2 */
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496 | regset->opd[2] = 0x00; /* OPD1 */
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497 | regset->opd[3] = 0x00; /* OPD0 */
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498 |
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499 | /* ---- dummy cycle ---- */
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500 | regset->dme = SPIBSC_DUMMY_CYC_DISABLE;
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501 | regset->dmdb = SPIBSC_1BIT;
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502 | regset->dmcyc = SPIBSC_DUMMY_1CYC;
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503 |
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504 | /* ---- data ---- */
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505 | regset->spide = SPIBSC_OUTPUT_DISABLE;
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506 | regset->spidre = SPIBSC_SDR_TRANS; /* SDR */
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507 | regset->spidb = SPIBSC_1BIT;
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508 |
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509 | /* ---- Others ---- */
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510 | regset->sslkp = SPIBSC_SPISSL_NEGATE; /* SPBSSL level */
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511 | regset->spire = SPIBSC_SPIDATA_DISABLE; /* read enable/disable */
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512 | regset->spiwe = SPIBSC_SPIDATA_DISABLE; /* write enable/disable */
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513 | }
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514 |
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515 | static int32_t spibsc_transfer(st_spibsc_spimd_reg_t * regset)
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516 | {
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517 | if (RegRead_32(&SPIBSC->CMNCR, SPIBSC_CMNCR_MD_SHIFT, SPIBSC_CMNCR_MD) != SPIBSC_CMNCR_MD_SPI) {
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518 | if (RegRead_32(&SPIBSC->CMNSR, SPIBSC_CMNSR_SSLF_SHIFT, SPIBSC_CMNSR_SSLF) != SPIBSC_SSL_NEGATE) {
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519 | return -1;
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520 | }
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521 | /* SPI Mode */
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522 | RegWwrite_32(&SPIBSC->CMNCR, SPIBSC_CMNCR_MD_SPI, SPIBSC_CMNCR_MD_SHIFT, SPIBSC_CMNCR_MD);
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523 | }
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524 |
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525 | if (RegRead_32(&SPIBSC->CMNSR, SPIBSC_CMNSR_TEND_SHIFT, SPIBSC_CMNSR_TEND) != SPIBSC_TRANS_END) {
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526 | return -1;
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527 | }
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528 |
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529 | /* ---- Command ---- */
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530 | /* Enable/Disable */
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531 | RegWwrite_32(&SPIBSC->SMENR, regset->cde, SPIBSC_SMENR_CDE_SHIFT, SPIBSC_SMENR_CDE);
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532 | if (regset->cde != SPIBSC_OUTPUT_DISABLE) {
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533 | /* Command */
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534 | RegWwrite_32(&SPIBSC->SMCMR, regset->cmd, SPIBSC_SMCMR_CMD_SHIFT, SPIBSC_SMCMR_CMD);
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535 | /* Single/Dual/Quad */
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536 | RegWwrite_32(&SPIBSC->SMENR, regset->cdb, SPIBSC_SMENR_CDB_SHIFT, SPIBSC_SMENR_CDB);
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537 | }
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538 |
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539 | /* ---- Option Command ---- */
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540 | /* Enable/Disable */
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541 | RegWwrite_32(&SPIBSC->SMENR, regset->ocde, SPIBSC_SMENR_OCDE_SHIFT, SPIBSC_SMENR_OCDE);
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542 | if (regset->ocde != SPIBSC_OUTPUT_DISABLE) {
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543 | /* Option Command */
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544 | RegWwrite_32(&SPIBSC->SMCMR, regset->ocmd, SPIBSC_SMCMR_OCMD_SHIFT, SPIBSC_SMCMR_OCMD);
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545 | /* Single/Dual/Quad */
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546 | RegWwrite_32(&SPIBSC->SMENR, regset->ocdb, SPIBSC_SMENR_OCDB_SHIFT, SPIBSC_SMENR_OCDB);
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547 | }
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548 |
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549 | /* ---- Address ---- */
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550 | /* Enable/Disable */
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551 | RegWwrite_32(&SPIBSC->SMENR, regset->ade, SPIBSC_SMENR_ADE_SHIFT, SPIBSC_SMENR_ADE);
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552 | if (regset->ade != SPIBSC_OUTPUT_DISABLE) {
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553 | /* Address */
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554 | RegWwrite_32(&SPIBSC->SMADR, regset->addr, SPIBSC_SMADR_ADR_SHIFT, SPIBSC_SMADR_ADR);
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555 | /* Single/Dual/Quad */
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556 | RegWwrite_32(&SPIBSC->SMENR, regset->adb, SPIBSC_SMENR_ADB_SHIFT, SPIBSC_SMENR_ADB);
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557 | }
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558 |
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559 | /* ---- Option Data ---- */
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560 | /* Enable/Disable */
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561 | RegWwrite_32(&SPIBSC->SMENR, regset->opde, SPIBSC_SMENR_OPDE_SHIFT, SPIBSC_SMENR_OPDE);
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562 | if (regset->opde != SPIBSC_OUTPUT_DISABLE) {
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563 | /* Option Data */
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564 | RegWwrite_32(&SPIBSC->SMOPR, regset->opd[0], SPIBSC_SMOPR_OPD3_SHIFT, SPIBSC_SMOPR_OPD3);
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565 | RegWwrite_32(&SPIBSC->SMOPR, regset->opd[1], SPIBSC_SMOPR_OPD2_SHIFT, SPIBSC_SMOPR_OPD2);
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566 | RegWwrite_32(&SPIBSC->SMOPR, regset->opd[2], SPIBSC_SMOPR_OPD1_SHIFT, SPIBSC_SMOPR_OPD1);
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567 | RegWwrite_32(&SPIBSC->SMOPR, regset->opd[3], SPIBSC_SMOPR_OPD0_SHIFT, SPIBSC_SMOPR_OPD0);
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568 | /* Single/Dual/Quad */
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569 | RegWwrite_32(&SPIBSC->SMENR, regset->opdb, SPIBSC_SMENR_OPDB_SHIFT, SPIBSC_SMENR_OPDB);
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570 | }
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571 |
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572 | /* ---- Dummy ---- */
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573 | /* Enable/Disable */
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574 | RegWwrite_32(&SPIBSC->SMENR, regset->dme, SPIBSC_SMENR_DME_SHIFT, SPIBSC_SMENR_DME);
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575 | if (regset->dme != SPIBSC_DUMMY_CYC_DISABLE) {
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576 | RegWwrite_32(&SPIBSC->SMDMCR, regset->dmdb, SPIBSC_SMDMCR_DMDB_SHIFT, SPIBSC_SMDMCR_DMDB);
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577 | /* Dummy Cycle */
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578 | RegWwrite_32(&SPIBSC->SMDMCR, regset->dmcyc, SPIBSC_SMDMCR_DMCYC_SHIFT, SPIBSC_SMDMCR_DMCYC);
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579 | }
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580 |
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581 | /* ---- Data ---- */
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582 | /* Enable/Disable */
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583 | RegWwrite_32(&SPIBSC->SMENR, regset->spide, SPIBSC_SMENR_SPIDE_SHIFT, SPIBSC_SMENR_SPIDE);
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584 | if (regset->spide != SPIBSC_OUTPUT_DISABLE) {
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585 | if (SPIBSC_OUTPUT_SPID_8 == regset->spide) {
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586 | if (RegRead_32(&SPIBSC0.CMNCR, SPIBSC_CMNCR_BSZ_SHIFT, SPIBSC_CMNCR_BSZ) == SPIBSC_CMNCR_BSZ_SINGLE) {
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587 | SPIBSC->SMWDR0.UINT8[0] = (uint8_t)(regset->smwdr[0]);
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588 | } else {
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589 | SPIBSC->SMWDR0.UINT16[0] = (uint16_t)(regset->smwdr[0]);
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590 | }
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591 | } else if (regset->spide == SPIBSC_OUTPUT_SPID_16) {
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592 | if (RegRead_32(&SPIBSC0.CMNCR, SPIBSC_CMNCR_BSZ_SHIFT, SPIBSC_CMNCR_BSZ) == SPIBSC_CMNCR_BSZ_SINGLE) {
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593 | SPIBSC->SMWDR0.UINT16[0] = (uint16_t)(regset->smwdr[0]);
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594 | } else {
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595 | SPIBSC->SMWDR0.UINT32 = regset->smwdr[0];
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596 | }
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597 | } else if (regset->spide == SPIBSC_OUTPUT_SPID_32) {
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598 | if (RegRead_32(&SPIBSC0.CMNCR, SPIBSC_CMNCR_BSZ_SHIFT, SPIBSC_CMNCR_BSZ) == SPIBSC_CMNCR_BSZ_SINGLE) {
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599 | SPIBSC->SMWDR0.UINT32 = (uint32_t)(regset->smwdr[0]);
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600 | } else {
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601 | SPIBSC->SMWDR0.UINT32 = (uint32_t)(regset->smwdr[0]);
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602 | SPIBSC->SMWDR1.UINT32 = (uint32_t)(regset->smwdr[1]); /* valid in two serial-flash */
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603 | }
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604 | } else {
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605 | /* none */
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606 | }
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607 |
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608 | /* Single/Dual/Quad */
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609 | RegWwrite_32(&SPIBSC->SMENR, regset->spidb, SPIBSC_SMENR_SPIDB_SHIFT, SPIBSC_SMENR_SPIDB);
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610 | }
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611 |
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612 | RegWwrite_32(&SPIBSC->SMCR, regset->sslkp, SPIBSC_SMCR_SSLKP_SHIFT, SPIBSC_SMCR_SSLKP);
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613 |
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614 | if ((regset->spidb != SPIBSC_1BIT) && (regset->spide != SPIBSC_OUTPUT_DISABLE)) {
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615 | if ((regset->spire == SPIBSC_SPIDATA_ENABLE) && (regset->spiwe == SPIBSC_SPIDATA_ENABLE)) {
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616 | /* not set in same time */
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617 | return -1;
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618 | }
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619 | }
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620 |
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621 | RegWwrite_32(&SPIBSC->SMCR, regset->spire, SPIBSC_SMCR_SPIRE_SHIFT, SPIBSC_SMCR_SPIRE);
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622 | RegWwrite_32(&SPIBSC->SMCR, regset->spiwe, SPIBSC_SMCR_SPIWE_SHIFT, SPIBSC_SMCR_SPIWE);
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623 |
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624 | /* SDR Transmission/DDR Transmission Setting */
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625 | RegWwrite_32(&SPIBSC->SMDRENR, regset->addre, SPIBSC_SMDRENR_ADDRE_SHIFT, SPIBSC_SMDRENR_ADDRE);
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626 | RegWwrite_32(&SPIBSC->SMDRENR, regset->opdre, SPIBSC_SMDRENR_OPDRE_SHIFT, SPIBSC_SMDRENR_OPDRE);
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627 | RegWwrite_32(&SPIBSC->SMDRENR, regset->spidre, SPIBSC_SMDRENR_SPIDRE_SHIFT, SPIBSC_SMDRENR_SPIDRE);
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628 |
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629 | /* execute after setting SPNDL bit */
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630 | RegWwrite_32(&SPIBSC->SMCR, SPIBSC_SPI_ENABLE, SPIBSC_SMCR_SPIE_SHIFT, SPIBSC_SMCR_SPIE);
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631 |
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632 | /* wait for transfer-start */
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633 | while (RegRead_32(&SPIBSC->CMNSR, SPIBSC_CMNSR_TEND_SHIFT, SPIBSC_CMNSR_TEND) != SPIBSC_TRANS_END) {
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634 | /* wait for transfer-end */
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635 | }
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636 |
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637 | if (SPIBSC_OUTPUT_SPID_8 == regset->spide) {
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638 | if (RegRead_32(&SPIBSC0.CMNCR, SPIBSC_CMNCR_BSZ_SHIFT, SPIBSC_CMNCR_BSZ) == SPIBSC_CMNCR_BSZ_SINGLE) {
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639 | regset->smrdr[0] = SPIBSC->SMRDR0.UINT8[0];
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640 | } else {
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641 | regset->smrdr[0] = SPIBSC->SMRDR0.UINT16[0]; /* valid in two serial-flash */
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642 | }
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643 | } else if (regset->spide == SPIBSC_OUTPUT_SPID_16) {
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644 | if (RegRead_32(&SPIBSC0.CMNCR, SPIBSC_CMNCR_BSZ_SHIFT, SPIBSC_CMNCR_BSZ) == SPIBSC_CMNCR_BSZ_SINGLE) {
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645 | regset->smrdr[0] = SPIBSC->SMRDR0.UINT16[0];
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646 | } else {
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647 | regset->smrdr[0] = SPIBSC->SMRDR0.UINT32; /* valid in two serial-flash */
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648 | }
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649 | } else if (regset->spide == SPIBSC_OUTPUT_SPID_32) {
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650 | if (RegRead_32(&SPIBSC0.CMNCR, SPIBSC_CMNCR_BSZ_SHIFT, SPIBSC_CMNCR_BSZ) == SPIBSC_CMNCR_BSZ_SINGLE) {
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651 | regset->smrdr[0] = SPIBSC->SMRDR0.UINT32;
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652 | } else {
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653 | regset->smrdr[0] = SPIBSC->SMRDR0.UINT32; /* valid in two serial-flash */
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654 | regset->smrdr[1] = SPIBSC->SMRDR1.UINT32;
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655 | }
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656 | } else {
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657 | /* none */
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658 | }
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659 |
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660 | return 0;
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661 | }
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662 |
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663 | static uint32_t RegRead_32(volatile uint32_t * ioreg, uint32_t shift, uint32_t mask)
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664 | {
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665 | uint32_t reg_value;
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666 |
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667 | reg_value = *ioreg; /* Read from register */
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668 | reg_value = (reg_value & mask) >> shift; /* Clear other bit and Bit shift */
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669 |
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670 | return reg_value;
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671 | }
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672 |
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673 | static void RegWwrite_32(volatile uint32_t * ioreg, uint32_t write_value, uint32_t shift, uint32_t mask)
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674 | {
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675 | uint32_t reg_value;
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676 |
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677 | reg_value = *ioreg; /* Read from register */
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678 | reg_value = (reg_value & (~mask)) | (write_value << shift); /* Modify value */
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679 | *ioreg = reg_value; /* Write to register */
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680 | }
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681 |
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682 | static void change_mmu_ttbl_spibsc(uint32_t type)
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683 | {
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684 | uint32_t index; /* Loop variable: table index */
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685 | mmu_ttbl_desc_section_t desc; /* Loop variable: descriptor */
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686 | mmu_ttbl_desc_section_t * table = (mmu_ttbl_desc_section_t *)TTB;
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687 |
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688 | /* ==== Modify SPI Multi-I/O bus space settings in the MMU translation table ==== */
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689 | for (index = (SPIBSC_ADDR_START >> 20); index <= (SPIBSC_ADDR_END >> 20); index++) {
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690 | /* Modify memory attribute descriptor */
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691 | if (type == 0) { /* Spi */
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692 | desc = table[index];
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693 | desc_tbl[index - (SPIBSC_ADDR_START >> 20)] = desc;
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694 | desc.AP1_0 = 0x0u; /* AP[2:0] = b'000 (No access) */
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695 | desc.AP2 = 0x0u;
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696 | desc.XN = 0x1u; /* XN = 1 (Execute never) */
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697 | } else { /* Xip */
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698 | desc = desc_tbl[index - (SPIBSC_ADDR_START >> 20)];
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699 | }
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700 | /* Write descriptor back to translation table */
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701 | table[index] = desc;
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702 | }
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703 | }
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704 |
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705 | static void spibsc_stop(void)
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706 | {
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707 | if (((SPIBSC->DRCR & SPIBSC_DRCR_RBE) != 0) &&
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708 | ((SPIBSC->DRCR & SPIBSC_DRCR_SSLE) != 0)) {
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709 | RegWwrite_32(&SPIBSC->DRCR, 1, SPIBSC_DRCR_SSLN_SHIFT, SPIBSC_DRCR_SSLN);
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710 | }
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711 |
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712 | while (RegRead_32(&SPIBSC->CMNSR, SPIBSC_CMNSR_SSLF_SHIFT, SPIBSC_CMNSR_SSLF) != SPIBSC_SSL_NEGATE) {
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713 | ;
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714 | }
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715 |
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716 | while (RegRead_32(&SPIBSC->CMNSR, SPIBSC_CMNSR_TEND_SHIFT, SPIBSC_CMNSR_TEND) != SPIBSC_TRANS_END) {
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717 | ;
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718 | }
|
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719 | }
|
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720 |
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721 | static void cache_control(void)
|
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722 | {
|
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723 | unsigned int assoc;
|
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724 |
|
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725 | /* ==== Cleaning and invalidation of the L1 data cache ==== */
|
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726 | L1C_CleanInvalidateDCacheAll();
|
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727 | __DSB();
|
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728 |
|
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729 | /* ==== Cleaning and invalidation of the L2 cache ==== */
|
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730 | if (L2C_310->AUX_CNT & (1U << 16U)) {
|
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731 | assoc = 16U;
|
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732 | } else {
|
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733 | assoc = 8U;
|
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734 | }
|
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735 | L2C_310->CLEAN_INV_WAY = (1U << assoc) - 1U;
|
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736 | while (L2C_310->CLEAN_INV_WAY & ((1U << assoc) - 1U)); // poll invalidate
|
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737 | L2C_310->CACHE_SYNC = 0x0;
|
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738 |
|
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739 | /* ==== Invalidate all TLB entries ==== */
|
---|
740 | __set_TLBIALL(0);
|
---|
741 | __DSB(); // ensure completion of the invalidation
|
---|
742 | __ISB(); // ensure instruction fetch path sees new state
|
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743 |
|
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744 | /* ==== Invalidate the L1 instruction cache ==== */
|
---|
745 | __set_ICIALLU(0);
|
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746 | __DSB(); // ensure completion of the invalidation
|
---|
747 | __ISB(); // ensure instruction fetch path sees new I cache state
|
---|
748 | }
|
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749 | #endif
|
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