source: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/rspi_iodefine.h@ 374

Last change on this file since 374 was 374, checked in by coas-nagasima, 5 years ago

mbed関連を更新
シリアルドライバをmbedのHALを使うよう変更
ファイルディスクリプタの処理を更新
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1/*******************************************************************************
2* DISCLAIMER
3* This software is supplied by Renesas Electronics Corporation and is only
4* intended for use with Renesas products. No other uses are authorized. This
5* software is owned by Renesas Electronics Corporation and is protected under
6* all applicable laws, including copyright laws.
7* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
8* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
9* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
10* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
11* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
12* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
13* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
14* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
15* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
16* Renesas reserves the right, without notice, to make changes to this software
17* and to discontinue the availability of this software. By using this software,
18* you agree to the additional terms and conditions found by accessing the
19* following link:
20* http://www.renesas.com/disclaimer*
21* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
22*******************************************************************************/
23/*******************************************************************************
24* File Name : rspi_iodefine.h
25* $Rev: $
26* $Date:: $
27* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
28******************************************************************************/
29#ifndef RSPI_IODEFINE_H
30#define RSPI_IODEFINE_H
31/* ->QAC 0639 : Over 127 members (C90) */
32/* ->QAC 0857 : Over 1024 #define (C90) */
33/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
34/* ->SEC M1.10.1 : Not magic number */
35
36#define RSPI0 (*(struct st_rspi *)0xE800C800uL) /* RSPI0 */
37#define RSPI1 (*(struct st_rspi *)0xE800D000uL) /* RSPI1 */
38#define RSPI2 (*(struct st_rspi *)0xE800D800uL) /* RSPI2 */
39#define RSPI3 (*(struct st_rspi *)0xE800E000uL) /* RSPI3 */
40#define RSPI4 (*(struct st_rspi *)0xE800E800uL) /* RSPI4 */
41
42
43/* Start of channel array defines of RSPI */
44
45/* Channel array defines of RSPI */
46/*(Sample) value = RSPI[ channel ]->SPCR; */
47#define RSPI_COUNT (5)
48#define RSPI_ADDRESS_LIST \
49{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
50 &RSPI0, &RSPI1, &RSPI2, &RSPI3, &RSPI4 \
51} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
52
53/* End of channel array defines of RSPI */
54
55
56#define SPCR_0 (RSPI0.SPCR)
57#define SSLP_0 (RSPI0.SSLP)
58#define SPPCR_0 (RSPI0.SPPCR)
59#define SPSR_0 (RSPI0.SPSR)
60#define SPDR_0 (RSPI0.SPDR.UINT32)
61#define SPDR_0L (RSPI0.SPDR.UINT16[R_IO_L])
62#define SPDR_0H (RSPI0.SPDR.UINT16[R_IO_H])
63#define SPDR_0LL (RSPI0.SPDR.UINT8[R_IO_LL])
64#define SPDR_0LH (RSPI0.SPDR.UINT8[R_IO_LH])
65#define SPDR_0HL (RSPI0.SPDR.UINT8[R_IO_HL])
66#define SPDR_0HH (RSPI0.SPDR.UINT8[R_IO_HH])
67#define SPSCR_0 (RSPI0.SPSCR)
68#define SPSSR_0 (RSPI0.SPSSR)
69#define SPBR_0 (RSPI0.SPBR)
70#define SPDCR_0 (RSPI0.SPDCR)
71#define SPCKD_0 (RSPI0.SPCKD)
72#define SSLND_0 (RSPI0.SSLND)
73#define SPND_0 (RSPI0.SPND)
74#define SPCMD0_0 (RSPI0.SPCMD0)
75#define SPCMD1_0 (RSPI0.SPCMD1)
76#define SPCMD2_0 (RSPI0.SPCMD2)
77#define SPCMD3_0 (RSPI0.SPCMD3)
78#define SPBFCR_0 (RSPI0.SPBFCR)
79#define SPBFDR_0 (RSPI0.SPBFDR)
80#define SPCR_1 (RSPI1.SPCR)
81#define SSLP_1 (RSPI1.SSLP)
82#define SPPCR_1 (RSPI1.SPPCR)
83#define SPSR_1 (RSPI1.SPSR)
84#define SPDR_1 (RSPI1.SPDR.UINT32)
85#define SPDR_1L (RSPI1.SPDR.UINT16[R_IO_L])
86#define SPDR_1H (RSPI1.SPDR.UINT16[R_IO_H])
87#define SPDR_1LL (RSPI1.SPDR.UINT8[R_IO_LL])
88#define SPDR_1LH (RSPI1.SPDR.UINT8[R_IO_LH])
89#define SPDR_1HL (RSPI1.SPDR.UINT8[R_IO_HL])
90#define SPDR_1HH (RSPI1.SPDR.UINT8[R_IO_HH])
91#define SPSCR_1 (RSPI1.SPSCR)
92#define SPSSR_1 (RSPI1.SPSSR)
93#define SPBR_1 (RSPI1.SPBR)
94#define SPDCR_1 (RSPI1.SPDCR)
95#define SPCKD_1 (RSPI1.SPCKD)
96#define SSLND_1 (RSPI1.SSLND)
97#define SPND_1 (RSPI1.SPND)
98#define SPCMD0_1 (RSPI1.SPCMD0)
99#define SPCMD1_1 (RSPI1.SPCMD1)
100#define SPCMD2_1 (RSPI1.SPCMD2)
101#define SPCMD3_1 (RSPI1.SPCMD3)
102#define SPBFCR_1 (RSPI1.SPBFCR)
103#define SPBFDR_1 (RSPI1.SPBFDR)
104#define SPCR_2 (RSPI2.SPCR)
105#define SSLP_2 (RSPI2.SSLP)
106#define SPPCR_2 (RSPI2.SPPCR)
107#define SPSR_2 (RSPI2.SPSR)
108#define SPDR_2 (RSPI2.SPDR.UINT32)
109#define SPDR_2L (RSPI2.SPDR.UINT16[R_IO_L])
110#define SPDR_2H (RSPI2.SPDR.UINT16[R_IO_H])
111#define SPDR_2LL (RSPI2.SPDR.UINT8[R_IO_LL])
112#define SPDR_2LH (RSPI2.SPDR.UINT8[R_IO_LH])
113#define SPDR_2HL (RSPI2.SPDR.UINT8[R_IO_HL])
114#define SPDR_2HH (RSPI2.SPDR.UINT8[R_IO_HH])
115#define SPSCR_2 (RSPI2.SPSCR)
116#define SPSSR_2 (RSPI2.SPSSR)
117#define SPBR_2 (RSPI2.SPBR)
118#define SPDCR_2 (RSPI2.SPDCR)
119#define SPCKD_2 (RSPI2.SPCKD)
120#define SSLND_2 (RSPI2.SSLND)
121#define SPND_2 (RSPI2.SPND)
122#define SPCMD0_2 (RSPI2.SPCMD0)
123#define SPCMD1_2 (RSPI2.SPCMD1)
124#define SPCMD2_2 (RSPI2.SPCMD2)
125#define SPCMD3_2 (RSPI2.SPCMD3)
126#define SPBFCR_2 (RSPI2.SPBFCR)
127#define SPBFDR_2 (RSPI2.SPBFDR)
128#define SPCR_3 (RSPI3.SPCR)
129#define SSLP_3 (RSPI3.SSLP)
130#define SPPCR_3 (RSPI3.SPPCR)
131#define SPSR_3 (RSPI3.SPSR)
132#define SPDR_3 (RSPI3.SPDR.UINT32)
133#define SPDR_3L (RSPI3.SPDR.UINT16[R_IO_L])
134#define SPDR_3H (RSPI3.SPDR.UINT16[R_IO_H])
135#define SPDR_3LL (RSPI3.SPDR.UINT8[R_IO_LL])
136#define SPDR_3LH (RSPI3.SPDR.UINT8[R_IO_LH])
137#define SPDR_3HL (RSPI3.SPDR.UINT8[R_IO_HL])
138#define SPDR_3HH (RSPI3.SPDR.UINT8[R_IO_HH])
139#define SPSCR_3 (RSPI3.SPSCR)
140#define SPSSR_3 (RSPI3.SPSSR)
141#define SPBR_3 (RSPI3.SPBR)
142#define SPDCR_3 (RSPI3.SPDCR)
143#define SPCKD_3 (RSPI3.SPCKD)
144#define SSLND_3 (RSPI3.SSLND)
145#define SPND_3 (RSPI3.SPND)
146#define SPCMD0_3 (RSPI3.SPCMD0)
147#define SPCMD1_3 (RSPI3.SPCMD1)
148#define SPCMD2_3 (RSPI3.SPCMD2)
149#define SPCMD3_3 (RSPI3.SPCMD3)
150#define SPBFCR_3 (RSPI3.SPBFCR)
151#define SPBFDR_3 (RSPI3.SPBFDR)
152#define SPCR_4 (RSPI4.SPCR)
153#define SSLP_4 (RSPI4.SSLP)
154#define SPPCR_4 (RSPI4.SPPCR)
155#define SPSR_4 (RSPI4.SPSR)
156#define SPDR_4 (RSPI4.SPDR.UINT32)
157#define SPDR_4L (RSPI4.SPDR.UINT16[R_IO_L])
158#define SPDR_4H (RSPI4.SPDR.UINT16[R_IO_H])
159#define SPDR_4LL (RSPI4.SPDR.UINT8[R_IO_LL])
160#define SPDR_4LH (RSPI4.SPDR.UINT8[R_IO_LH])
161#define SPDR_4HL (RSPI4.SPDR.UINT8[R_IO_HL])
162#define SPDR_4HH (RSPI4.SPDR.UINT8[R_IO_HH])
163#define SPSCR_4 (RSPI4.SPSCR)
164#define SPSSR_4 (RSPI4.SPSSR)
165#define SPBR_4 (RSPI4.SPBR)
166#define SPDCR_4 (RSPI4.SPDCR)
167#define SPCKD_4 (RSPI4.SPCKD)
168#define SSLND_4 (RSPI4.SSLND)
169#define SPND_4 (RSPI4.SPND)
170#define SPCMD0_4 (RSPI4.SPCMD0)
171#define SPCMD1_4 (RSPI4.SPCMD1)
172#define SPCMD2_4 (RSPI4.SPCMD2)
173#define SPCMD3_4 (RSPI4.SPCMD3)
174#define SPBFCR_4 (RSPI4.SPBFCR)
175#define SPBFDR_4 (RSPI4.SPBFDR)
176
177#define SPCMD_COUNT (4)
178
179
180typedef struct st_rspi
181{
182 /* RSPI */
183 volatile uint8_t SPCR; /* SPCR */
184 volatile uint8_t SSLP; /* SSLP */
185 volatile uint8_t SPPCR; /* SPPCR */
186 volatile uint8_t SPSR; /* SPSR */
187 union iodefine_reg32_t SPDR; /* SPDR */
188
189 volatile uint8_t SPSCR; /* SPSCR */
190 volatile uint8_t SPSSR; /* SPSSR */
191 volatile uint8_t SPBR; /* SPBR */
192 volatile uint8_t SPDCR; /* SPDCR */
193 volatile uint8_t SPCKD; /* SPCKD */
194 volatile uint8_t SSLND; /* SSLND */
195 volatile uint8_t SPND; /* SPND */
196 volatile uint8_t dummy1[1]; /* */
197
198/* #define SPCMD_COUNT (4) */
199 volatile uint16_t SPCMD0; /* SPCMD0 */
200 volatile uint16_t SPCMD1; /* SPCMD1 */
201 volatile uint16_t SPCMD2; /* SPCMD2 */
202 volatile uint16_t SPCMD3; /* SPCMD3 */
203 volatile uint8_t dummy2[8]; /* */
204 volatile uint8_t SPBFCR; /* SPBFCR */
205 volatile uint8_t dummy3[1]; /* */
206 volatile uint16_t SPBFDR; /* SPBFDR */
207} r_io_rspi_t;
208
209
210/* Channel array defines of RSPI (2)*/
211#ifdef DECLARE_RSPI_CHANNELS
212volatile struct st_rspi* RSPI[ RSPI_COUNT ] =
213 /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
214 RSPI_ADDRESS_LIST;
215 /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
216#endif /* DECLARE_RSPI_CHANNELS */
217/* End of channel array defines of RSPI (2)*/
218
219
220/* <-SEC M1.10.1 */
221/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
222/* <-QAC 0857 */
223/* <-QAC 0639 */
224#endif
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