1 | /*******************************************************************************
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2 | * DISCLAIMER
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3 | * This software is supplied by Renesas Electronics Corporation and is only
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4 | * intended for use with Renesas products. No other uses are authorized. This
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5 | * software is owned by Renesas Electronics Corporation and is protected under
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6 | * all applicable laws, including copyright laws.
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7 | * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
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8 | * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
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9 | * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
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10 | * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
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11 | * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
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12 | * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
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13 | * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
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14 | * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
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15 | * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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16 | * Renesas reserves the right, without notice, to make changes to this software
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17 | * and to discontinue the availability of this software. By using this software,
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18 | * you agree to the additional terms and conditions found by accessing the
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19 | * following link:
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20 | * http://www.renesas.com/disclaimer*
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21 | * Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
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22 | *******************************************************************************/
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23 | /*******************************************************************************
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24 | * File Name : inb_iodefine.h
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25 | * $Rev: $
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26 | * $Date:: $
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27 | * Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
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28 | ******************************************************************************/
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29 | #ifndef INB_IODEFINE_H
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30 | #define INB_IODEFINE_H
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31 | /* ->QAC 0639 : Over 127 members (C90) */
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32 | /* ->QAC 0857 : Over 1024 #define (C90) */
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33 | /* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
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34 | /* ->SEC M1.10.1 : Not magic number */
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35 |
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36 | #define INB (*(struct st_inb *)0xFCFE1A00uL) /* INB */
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37 |
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38 |
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39 | #define INBRMPR (INB.RMPR)
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40 | #define INBAXIBUSCTL0 (INB.AXIBUSCTL0)
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41 | #define INBAXIBUSCTL1 (INB.AXIBUSCTL1)
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42 | #define INBAXIBUSCTL2 (INB.AXIBUSCTL2)
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43 | #define INBAXIBUSCTL3 (INB.AXIBUSCTL3)
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44 | #define INBAXIBUSCTL4 (INB.AXIBUSCTL4)
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45 | #define INBAXIBUSCTL5 (INB.AXIBUSCTL5)
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46 | #define INBAXIBUSCTL6 (INB.AXIBUSCTL6)
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47 | #define INBAXIBUSCTL7 (INB.AXIBUSCTL7)
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48 | #define INBAXIBUSCTL8 (INB.AXIBUSCTL8)
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49 | #define INBAXIBUSCTL9 (INB.AXIBUSCTL9)
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50 | #define INBAXIBUSCTL10 (INB.AXIBUSCTL10)
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51 | #define INBAXIRERRCTL0 (INB.AXIRERRCTL0)
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52 | #define INBAXIRERRCTL1 (INB.AXIRERRCTL1)
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53 | #define INBAXIRERRCTL2 (INB.AXIRERRCTL2)
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54 | #define INBAXIRERRCTL3 (INB.AXIRERRCTL3)
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55 | #define INBAXIRERRST0 (INB.AXIRERRST0)
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56 | #define INBAXIRERRST1 (INB.AXIRERRST1)
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57 | #define INBAXIRERRST2 (INB.AXIRERRST2)
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58 | #define INBAXIRERRST3 (INB.AXIRERRST3)
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59 | #define INBAXIRERRCLR0 (INB.AXIRERRCLR0)
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60 | #define INBAXIRERRCLR1 (INB.AXIRERRCLR1)
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61 | #define INBAXIRERRCLR2 (INB.AXIRERRCLR2)
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62 | #define INBAXIRERRCLR3 (INB.AXIRERRCLR3)
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63 |
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64 | #define INB_AXIBUSCTLn_COUNT (11)
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65 | #define INB_AXIRERRCTLn_COUNT (4)
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66 | #define INB_AXIRERRSTn_COUNT (4)
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67 | #define INB_AXIRERRCLRn_COUNT (4)
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68 |
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69 |
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70 | typedef struct st_inb
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71 | {
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72 | /* INB */
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73 | volatile uint32_t RMPR; /* RMPR */
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74 |
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75 | /* #define INB_AXIBUSCTLn_COUNT (11) */
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76 | volatile uint32_t AXIBUSCTL0; /* AXIBUSCTL0 */
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77 | volatile uint32_t AXIBUSCTL1; /* AXIBUSCTL1 */
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78 | volatile uint32_t AXIBUSCTL2; /* AXIBUSCTL2 */
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79 | volatile uint32_t AXIBUSCTL3; /* AXIBUSCTL3 */
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80 | volatile uint32_t AXIBUSCTL4; /* AXIBUSCTL4 */
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81 | volatile uint32_t AXIBUSCTL5; /* AXIBUSCTL5 */
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82 | volatile uint32_t AXIBUSCTL6; /* AXIBUSCTL6 */
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83 | volatile uint32_t AXIBUSCTL7; /* AXIBUSCTL7 */
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84 | volatile uint32_t AXIBUSCTL8; /* AXIBUSCTL8 */
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85 | volatile uint32_t AXIBUSCTL9; /* AXIBUSCTL9 */
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86 | volatile uint32_t AXIBUSCTL10; /* AXIBUSCTL10 */
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87 |
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88 | /* #define INB_AXIRERRCTLn_COUNT (4) */
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89 | volatile uint32_t AXIRERRCTL0; /* AXIRERRCTL0 */
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90 | volatile uint32_t AXIRERRCTL1; /* AXIRERRCTL1 */
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91 | volatile uint32_t AXIRERRCTL2; /* AXIRERRCTL2 */
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92 | volatile uint32_t AXIRERRCTL3; /* AXIRERRCTL3 */
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93 |
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94 | /* #define INB_AXIRERRSTn_COUNT (4) */
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95 | volatile uint32_t AXIRERRST0; /* AXIRERRST0 */
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96 | volatile uint32_t AXIRERRST1; /* AXIRERRST1 */
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97 | volatile uint32_t AXIRERRST2; /* AXIRERRST2 */
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98 | volatile uint32_t AXIRERRST3; /* AXIRERRST3 */
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99 |
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100 | /* #define INB_AXIRERRCLRn_COUNT (4) */
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101 | volatile uint32_t AXIRERRCLR0; /* AXIRERRCLR0 */
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102 | volatile uint32_t AXIRERRCLR1; /* AXIRERRCLR1 */
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103 | volatile uint32_t AXIRERRCLR2; /* AXIRERRCLR2 */
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104 | volatile uint32_t AXIRERRCLR3; /* AXIRERRCLR3 */
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105 | } r_io_inb_t;
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106 |
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107 |
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108 | /* <-SEC M1.10.1 */
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109 | /* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
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110 | /* <-QAC 0857 */
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111 | /* <-QAC 0639 */
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112 | #endif
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