[352] | 1 |
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| 2 | /** \addtogroup hal */
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| 3 | /** @{*/
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| 4 | /* mbed Microcontroller Library
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| 5 | * Copyright (c) 2006-2013 ARM Limited
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| 6 | *
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| 7 | * Licensed under the Apache License, Version 2.0 (the "License");
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| 8 | * you may not use this file except in compliance with the License.
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| 9 | * You may obtain a copy of the License at
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| 10 | *
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| 11 | * http://www.apache.org/licenses/LICENSE-2.0
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| 12 | *
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| 13 | * Unless required by applicable law or agreed to in writing, software
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| 14 | * distributed under the License is distributed on an "AS IS" BASIS,
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| 15 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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| 16 | * See the License for the specific language governing permissions and
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| 17 | * limitations under the License.
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| 18 | */
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| 19 | #ifndef MBED_SPI_API_H
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| 20 | #define MBED_SPI_API_H
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| 21 |
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| 22 | #include "device.h"
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| 23 | #include "hal/dma_api.h"
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| 24 | #include "hal/buffer.h"
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| 25 |
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| 26 | #if DEVICE_SPI
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| 27 |
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| 28 | #define SPI_EVENT_ERROR (1 << 1)
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| 29 | #define SPI_EVENT_COMPLETE (1 << 2)
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| 30 | #define SPI_EVENT_RX_OVERFLOW (1 << 3)
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| 31 | #define SPI_EVENT_ALL (SPI_EVENT_ERROR | SPI_EVENT_COMPLETE | SPI_EVENT_RX_OVERFLOW)
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| 32 |
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| 33 | #define SPI_EVENT_INTERNAL_TRANSFER_COMPLETE (1 << 30) // Internal flag to report that an event occurred
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| 34 |
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| 35 | #define SPI_FILL_WORD (0xFFFF)
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| 36 |
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| 37 | #if DEVICE_SPI_ASYNCH
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| 38 | /** Asynch SPI HAL structure
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| 39 | */
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| 40 | typedef struct {
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| 41 | struct spi_s spi; /**< Target specific SPI structure */
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| 42 | struct buffer_s tx_buff; /**< Tx buffer */
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| 43 | struct buffer_s rx_buff; /**< Rx buffer */
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| 44 | } spi_t;
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| 45 |
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| 46 | #else
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| 47 | /** Non-asynch SPI HAL structure
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| 48 | */
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| 49 | typedef struct spi_s spi_t;
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| 50 |
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| 51 | #endif
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| 52 |
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| 53 | #ifdef __cplusplus
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| 54 | extern "C" {
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| 55 | #endif
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| 56 |
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| 57 | /**
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| 58 | * \defgroup hal_GeneralSPI SPI Configuration Functions
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| 59 | * @{
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| 60 | */
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| 61 |
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| 62 | /** Initialize the SPI peripheral
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| 63 | *
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| 64 | * Configures the pins used by SPI, sets a default format and frequency, and enables the peripheral
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| 65 | * @param[out] obj The SPI object to initialize
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| 66 | * @param[in] mosi The pin to use for MOSI
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| 67 | * @param[in] miso The pin to use for MISO
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| 68 | * @param[in] sclk The pin to use for SCLK
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| 69 | * @param[in] ssel The pin to use for SSEL
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| 70 | */
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| 71 | void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel);
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| 72 |
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| 73 | /** Release a SPI object
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| 74 | *
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| 75 | * TODO: spi_free is currently unimplemented
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| 76 | * This will require reference counting at the C++ level to be safe
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| 77 | *
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| 78 | * Return the pins owned by the SPI object to their reset state
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| 79 | * Disable the SPI peripheral
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| 80 | * Disable the SPI clock
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| 81 | * @param[in] obj The SPI object to deinitialize
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| 82 | */
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| 83 | void spi_free(spi_t *obj);
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| 84 |
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| 85 | /** Configure the SPI format
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| 86 | *
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| 87 | * Set the number of bits per frame, configure clock polarity and phase, shift order and master/slave mode.
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| 88 | * The default bit order is MSB.
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| 89 | * @param[in,out] obj The SPI object to configure
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| 90 | * @param[in] bits The number of bits per frame
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| 91 | * @param[in] mode The SPI mode (clock polarity, phase, and shift direction)
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| 92 | * @param[in] slave Zero for master mode or non-zero for slave mode
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| 93 | */
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| 94 | void spi_format(spi_t *obj, int bits, int mode, int slave);
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| 95 |
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| 96 | /** Set the SPI baud rate
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| 97 | *
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| 98 | * Actual frequency may differ from the desired frequency due to available dividers and bus clock
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| 99 | * Configures the SPI peripheral's baud rate
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| 100 | * @param[in,out] obj The SPI object to configure
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| 101 | * @param[in] hz The baud rate in Hz
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| 102 | */
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| 103 | void spi_frequency(spi_t *obj, int hz);
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| 104 |
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| 105 | /**@}*/
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| 106 | /**
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| 107 | * \defgroup SynchSPI Synchronous SPI Hardware Abstraction Layer
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| 108 | * @{
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| 109 | */
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| 110 |
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| 111 | /** Write a byte out in master mode and receive a value
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| 112 | *
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| 113 | * @param[in] obj The SPI peripheral to use for sending
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| 114 | * @param[in] value The value to send
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| 115 | * @return Returns the value received during send
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| 116 | */
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| 117 | int spi_master_write(spi_t *obj, int value);
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| 118 |
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| 119 | /** Check if a value is available to read
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| 120 | *
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| 121 | * @param[in] obj The SPI peripheral to check
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| 122 | * @return non-zero if a value is available
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| 123 | */
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| 124 | int spi_slave_receive(spi_t *obj);
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| 125 |
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| 126 | /** Get a received value out of the SPI receive buffer in slave mode
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| 127 | *
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| 128 | * Blocks until a value is available
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| 129 | * @param[in] obj The SPI peripheral to read
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| 130 | * @return The value received
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| 131 | */
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| 132 | int spi_slave_read(spi_t *obj);
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| 133 |
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| 134 | /** Write a value to the SPI peripheral in slave mode
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| 135 | *
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| 136 | * Blocks until the SPI peripheral can be written to
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| 137 | * @param[in] obj The SPI peripheral to write
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| 138 | * @param[in] value The value to write
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| 139 | */
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| 140 | void spi_slave_write(spi_t *obj, int value);
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| 141 |
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| 142 | /** Checks if the specified SPI peripheral is in use
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| 143 | *
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| 144 | * @param[in] obj The SPI peripheral to check
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| 145 | * @return non-zero if the peripheral is currently transmitting
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| 146 | */
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| 147 | int spi_busy(spi_t *obj);
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| 148 |
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| 149 | /** Get the module number
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| 150 | *
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| 151 | * @param[in] obj The SPI peripheral to check
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| 152 | * @return The module number
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| 153 | */
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| 154 | uint8_t spi_get_module(spi_t *obj);
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| 155 |
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| 156 | /**@}*/
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| 157 |
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| 158 | #if DEVICE_SPI_ASYNCH
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| 159 | /**
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| 160 | * \defgroup AsynchSPI Asynchronous SPI Hardware Abstraction Layer
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| 161 | * @{
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| 162 | */
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| 163 |
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| 164 | /** Begin the SPI transfer. Buffer pointers and lengths are specified in tx_buff and rx_buff
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| 165 | *
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| 166 | * @param[in] obj The SPI object that holds the transfer information
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| 167 | * @param[in] tx The transmit buffer
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| 168 | * @param[in] tx_length The number of bytes to transmit
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| 169 | * @param[in] rx The receive buffer
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| 170 | * @param[in] rx_length The number of bytes to receive
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| 171 | * @param[in] bit_width The bit width of buffer words
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| 172 | * @param[in] event The logical OR of events to be registered
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| 173 | * @param[in] handler SPI interrupt handler
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| 174 | * @param[in] hint A suggestion for how to use DMA with this transfer
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| 175 | */
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| 176 | void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint);
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| 177 |
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| 178 | /** The asynchronous IRQ handler
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| 179 | *
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| 180 | * Reads the received values out of the RX FIFO, writes values into the TX FIFO and checks for transfer termination
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| 181 | * conditions, such as buffer overflows or transfer complete.
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| 182 | * @param[in] obj The SPI object that holds the transfer information
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| 183 | * @return Event flags if a transfer termination condition was met; otherwise 0.
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| 184 | */
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| 185 | uint32_t spi_irq_handler_asynch(spi_t *obj);
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| 186 |
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| 187 | /** Attempts to determine if the SPI peripheral is already in use
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| 188 | *
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| 189 | * If a temporary DMA channel has been allocated, peripheral is in use.
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| 190 | * If a permanent DMA channel has been allocated, check if the DMA channel is in use. If not, proceed as though no DMA
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| 191 | * channel were allocated.
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| 192 | * If no DMA channel is allocated, check whether tx and rx buffers have been assigned. For each assigned buffer, check
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| 193 | * if the corresponding buffer position is less than the buffer length. If buffers do not indicate activity, check if
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| 194 | * there are any bytes in the FIFOs.
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| 195 | * @param[in] obj The SPI object to check for activity
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| 196 | * @return Non-zero if the SPI port is active or zero if it is not.
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| 197 | */
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| 198 | uint8_t spi_active(spi_t *obj);
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| 199 |
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| 200 | /** Abort an SPI transfer
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| 201 | *
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| 202 | * @param obj The SPI peripheral to stop
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| 203 | */
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| 204 | void spi_abort_asynch(spi_t *obj);
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| 205 |
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| 206 |
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| 207 | #endif
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| 208 |
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| 209 | /**@}*/
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| 210 |
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| 211 | #ifdef __cplusplus
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| 212 | }
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| 213 | #endif // __cplusplus
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| 214 |
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| 215 | #endif // SPI_DEVICE
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| 216 |
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| 217 | #endif // MBED_SPI_API_H
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| 218 |
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| 219 | /** @}*/
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