source: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/cmsis/core_cm4.h@ 352

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1/**************************************************************************//**
2 * @file core_cm4.h
3 * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
4 * @version V4.10
5 * @date 18. March 2015
6 *
7 * @note
8 *
9 ******************************************************************************/
10/* Copyright (c) 2009 - 2015 ARM LIMITED
11
12 All rights reserved.
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 - Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 - Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 - Neither the name of ARM nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23 *
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ---------------------------------------------------------------------------*/
36
37
38#if defined ( __ICCARM__ )
39 #pragma system_include /* treat file as system include file for MISRA check */
40#endif
41
42#ifndef __CORE_CM4_H_GENERIC
43#define __CORE_CM4_H_GENERIC
44
45#ifdef __cplusplus
46 extern "C" {
47#endif
48
49/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
50 CMSIS violates the following MISRA-C:2004 rules:
51
52 \li Required Rule 8.5, object/function definition in header file.<br>
53 Function definitions in header files are used to allow 'inlining'.
54
55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
56 Unions are used for effective representation of core registers.
57
58 \li Advisory Rule 19.7, Function-like macro defined.<br>
59 Function-like macros are used to allow more efficient code.
60 */
61
62
63/*******************************************************************************
64 * CMSIS definitions
65 ******************************************************************************/
66/** \ingroup Cortex_M4
67 @{
68 */
69
70/* CMSIS CM4 definitions */
71#define __CM4_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
72#define __CM4_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
73#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \
74 __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
75
76#define __CORTEX_M (0x04) /*!< Cortex-M Core */
77
78
79#if defined ( __CC_ARM )
80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
82 #define __STATIC_INLINE static __inline
83
84#elif defined ( __GNUC__ )
85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
87 #define __STATIC_INLINE static inline
88
89#elif defined ( __ICCARM__ )
90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
92 #define __STATIC_INLINE static inline
93
94#elif defined ( __TMS470__ )
95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
96 #define __STATIC_INLINE static inline
97
98#elif defined ( __TASKING__ )
99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
101 #define __STATIC_INLINE static inline
102
103#elif defined ( __CSMC__ )
104 #define __packed
105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
107 #define __STATIC_INLINE static inline
108
109#endif
110
111/** __FPU_USED indicates whether an FPU is used or not.
112 For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
113*/
114#if defined ( __CC_ARM )
115 #if defined __TARGET_FPU_VFP
116 #if (__FPU_PRESENT == 1)
117 #define __FPU_USED 1
118 #else
119 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
120 #define __FPU_USED 0
121 #endif
122 #else
123 #define __FPU_USED 0
124 #endif
125
126#elif defined ( __GNUC__ )
127 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
128 #if (__FPU_PRESENT == 1)
129 #define __FPU_USED 1
130 #else
131 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
132 #define __FPU_USED 0
133 #endif
134 #else
135 #define __FPU_USED 0
136 #endif
137
138#elif defined ( __ICCARM__ )
139 #if defined __ARMVFP__
140 #if (__FPU_PRESENT == 1)
141 #define __FPU_USED 1
142 #else
143 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
144 #define __FPU_USED 0
145 #endif
146 #else
147 #define __FPU_USED 0
148 #endif
149
150#elif defined ( __TMS470__ )
151 #if defined __TI_VFP_SUPPORT__
152 #if (__FPU_PRESENT == 1)
153 #define __FPU_USED 1
154 #else
155 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
156 #define __FPU_USED 0
157 #endif
158 #else
159 #define __FPU_USED 0
160 #endif
161
162#elif defined ( __TASKING__ )
163 #if defined __FPU_VFP__
164 #if (__FPU_PRESENT == 1)
165 #define __FPU_USED 1
166 #else
167 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
168 #define __FPU_USED 0
169 #endif
170 #else
171 #define __FPU_USED 0
172 #endif
173
174#elif defined ( __CSMC__ ) /* Cosmic */
175 #if ( __CSMC__ & 0x400) // FPU present for parser
176 #if (__FPU_PRESENT == 1)
177 #define __FPU_USED 1
178 #else
179 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
180 #define __FPU_USED 0
181 #endif
182 #else
183 #define __FPU_USED 0
184 #endif
185#endif
186
187#include <stdint.h> /* standard types definitions */
188#include <core_cmInstr.h> /* Core Instruction Access */
189#include <core_cmFunc.h> /* Core Function Access */
190#include <core_cmSimd.h> /* Compiler specific SIMD Intrinsics */
191
192#ifdef __cplusplus
193}
194#endif
195
196#endif /* __CORE_CM4_H_GENERIC */
197
198#ifndef __CMSIS_GENERIC
199
200#ifndef __CORE_CM4_H_DEPENDANT
201#define __CORE_CM4_H_DEPENDANT
202
203#ifdef __cplusplus
204 extern "C" {
205#endif
206
207/* check device defines and use defaults */
208#if defined __CHECK_DEVICE_DEFINES
209 #ifndef __CM4_REV
210 #define __CM4_REV 0x0000
211 #warning "__CM4_REV not defined in device header file; using default!"
212 #endif
213
214 #ifndef __FPU_PRESENT
215 #define __FPU_PRESENT 0
216 #warning "__FPU_PRESENT not defined in device header file; using default!"
217 #endif
218
219 #ifndef __MPU_PRESENT
220 #define __MPU_PRESENT 0
221 #warning "__MPU_PRESENT not defined in device header file; using default!"
222 #endif
223
224 #ifndef __NVIC_PRIO_BITS
225 #define __NVIC_PRIO_BITS 4
226 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
227 #endif
228
229 #ifndef __Vendor_SysTickConfig
230 #define __Vendor_SysTickConfig 0
231 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
232 #endif
233#endif
234
235/* IO definitions (access restrictions to peripheral registers) */
236/**
237 \defgroup CMSIS_glob_defs CMSIS Global Defines
238
239 <strong>IO Type Qualifiers</strong> are used
240 \li to specify the access to peripheral variables.
241 \li for automatic generation of peripheral register debug information.
242*/
243#ifdef __cplusplus
244 #define __I volatile /*!< Defines 'read only' permissions */
245#else
246 #define __I volatile const /*!< Defines 'read only' permissions */
247#endif
248#define __O volatile /*!< Defines 'write only' permissions */
249#define __IO volatile /*!< Defines 'read / write' permissions */
250
251#ifdef __cplusplus
252 #define __IM volatile /*!< Defines 'read only' permissions */
253#else
254 #define __IM volatile const /*!< Defines 'read only' permissions */
255#endif
256#define __OM volatile /*!< Defines 'write only' permissions */
257#define __IOM volatile /*!< Defines 'read / write' permissions */
258
259/*@} end of group Cortex_M4 */
260
261
262
263/*******************************************************************************
264 * Register Abstraction
265 Core Register contain:
266 - Core Register
267 - Core NVIC Register
268 - Core SCB Register
269 - Core SysTick Register
270 - Core Debug Register
271 - Core MPU Register
272 - Core FPU Register
273 ******************************************************************************/
274/** \defgroup CMSIS_core_register Defines and Type Definitions
275 \brief Type definitions and defines for Cortex-M processor based devices.
276*/
277
278/** \ingroup CMSIS_core_register
279 \defgroup CMSIS_CORE Status and Control Registers
280 \brief Core Register type definitions.
281 @{
282 */
283
284/** \brief Union type to access the Application Program Status Register (APSR).
285 */
286typedef union
287{
288 struct
289 {
290 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
291 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
292 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
293 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
294 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
295 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
296 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
297 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
298 } b; /*!< Structure used for bit access */
299 uint32_t w; /*!< Type used for word access */
300} APSR_Type;
301
302/* APSR Register Definitions */
303#define APSR_N_Pos 31 /*!< APSR: N Position */
304#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
305
306#define APSR_Z_Pos 30 /*!< APSR: Z Position */
307#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
308
309#define APSR_C_Pos 29 /*!< APSR: C Position */
310#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
311
312#define APSR_V_Pos 28 /*!< APSR: V Position */
313#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
314
315#define APSR_Q_Pos 27 /*!< APSR: Q Position */
316#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
317
318#define APSR_GE_Pos 16 /*!< APSR: GE Position */
319#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
320
321
322/** \brief Union type to access the Interrupt Program Status Register (IPSR).
323 */
324typedef union
325{
326 struct
327 {
328 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
329 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
330 } b; /*!< Structure used for bit access */
331 uint32_t w; /*!< Type used for word access */
332} IPSR_Type;
333
334/* IPSR Register Definitions */
335#define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
336#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
337
338
339/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
340 */
341typedef union
342{
343 struct
344 {
345 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
346 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
347 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
348 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
349 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
350 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
351 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
352 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
353 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
354 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
355 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
356 } b; /*!< Structure used for bit access */
357 uint32_t w; /*!< Type used for word access */
358} xPSR_Type;
359
360/* xPSR Register Definitions */
361#define xPSR_N_Pos 31 /*!< xPSR: N Position */
362#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
363
364#define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
365#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
366
367#define xPSR_C_Pos 29 /*!< xPSR: C Position */
368#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
369
370#define xPSR_V_Pos 28 /*!< xPSR: V Position */
371#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
372
373#define xPSR_Q_Pos 27 /*!< xPSR: Q Position */
374#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
375
376#define xPSR_IT_Pos 25 /*!< xPSR: IT Position */
377#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
378
379#define xPSR_T_Pos 24 /*!< xPSR: T Position */
380#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
381
382#define xPSR_GE_Pos 16 /*!< xPSR: GE Position */
383#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
384
385#define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
386#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
387
388
389/** \brief Union type to access the Control Registers (CONTROL).
390 */
391typedef union
392{
393 struct
394 {
395 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
396 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
397 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
398 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
399 } b; /*!< Structure used for bit access */
400 uint32_t w; /*!< Type used for word access */
401} CONTROL_Type;
402
403/* CONTROL Register Definitions */
404#define CONTROL_FPCA_Pos 2 /*!< CONTROL: FPCA Position */
405#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
406
407#define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
408#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
409
410#define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
411#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
412
413/*@} end of group CMSIS_CORE */
414
415
416/** \ingroup CMSIS_core_register
417 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
418 \brief Type definitions for the NVIC Registers
419 @{
420 */
421
422/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
423 */
424typedef struct
425{
426 __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
427 uint32_t RESERVED0[24];
428 __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
429 uint32_t RSERVED1[24];
430 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
431 uint32_t RESERVED2[24];
432 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
433 uint32_t RESERVED3[24];
434 __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
435 uint32_t RESERVED4[56];
436 __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
437 uint32_t RESERVED5[644];
438 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
439} NVIC_Type;
440
441/* Software Triggered Interrupt Register Definitions */
442#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
443#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
444
445/*@} end of group CMSIS_NVIC */
446
447
448/** \ingroup CMSIS_core_register
449 \defgroup CMSIS_SCB System Control Block (SCB)
450 \brief Type definitions for the System Control Block Registers
451 @{
452 */
453
454/** \brief Structure type to access the System Control Block (SCB).
455 */
456typedef struct
457{
458 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
459 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
460 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
461 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
462 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
463 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
464 __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
465 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
466 __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
467 __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
468 __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
469 __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
470 __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
471 __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
472 __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
473 __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
474 __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
475 __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
476 __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
477 uint32_t RESERVED0[5];
478 __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
479} SCB_Type;
480
481/* SCB CPUID Register Definitions */
482#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
483#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
484
485#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
486#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
487
488#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
489#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
490
491#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
492#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
493
494#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
495#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
496
497/* SCB Interrupt Control State Register Definitions */
498#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
499#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
500
501#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
502#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
503
504#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
505#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
506
507#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
508#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
509
510#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
511#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
512
513#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
514#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
515
516#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
517#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
518
519#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
520#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
521
522#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
523#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
524
525#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
526#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
527
528/* SCB Vector Table Offset Register Definitions */
529#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
530#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
531
532/* SCB Application Interrupt and Reset Control Register Definitions */
533#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
534#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
535
536#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
537#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
538
539#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
540#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
541
542#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
543#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
544
545#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
546#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
547
548#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
549#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
550
551#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
552#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
553
554/* SCB System Control Register Definitions */
555#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
556#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
557
558#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
559#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
560
561#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
562#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
563
564/* SCB Configuration Control Register Definitions */
565#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
566#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
567
568#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
569#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
570
571#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
572#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
573
574#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
575#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
576
577#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
578#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
579
580#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
581#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
582
583/* SCB System Handler Control and State Register Definitions */
584#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
585#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
586
587#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
588#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
589
590#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
591#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
592
593#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
594#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
595
596#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
597#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
598
599#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
600#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
601
602#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
603#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
604
605#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
606#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
607
608#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
609#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
610
611#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
612#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
613
614#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
615#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
616
617#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
618#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
619
620#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
621#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
622
623#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
624#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
625
626/* SCB Configurable Fault Status Registers Definitions */
627#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
628#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
629
630#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
631#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
632
633#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
634#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
635
636/* SCB Hard Fault Status Registers Definitions */
637#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
638#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
639
640#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
641#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
642
643#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
644#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
645
646/* SCB Debug Fault Status Register Definitions */
647#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
648#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
649
650#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
651#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
652
653#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
654#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
655
656#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
657#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
658
659#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
660#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
661
662/*@} end of group CMSIS_SCB */
663
664
665/** \ingroup CMSIS_core_register
666 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
667 \brief Type definitions for the System Control and ID Register not in the SCB
668 @{
669 */
670
671/** \brief Structure type to access the System Control and ID Register not in the SCB.
672 */
673typedef struct
674{
675 uint32_t RESERVED0[1];
676 __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
677 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
678} SCnSCB_Type;
679
680/* Interrupt Controller Type Register Definitions */
681#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
682#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
683
684/* Auxiliary Control Register Definitions */
685#define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */
686#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
687
688#define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */
689#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
690
691#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
692#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
693
694#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
695#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
696
697#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
698#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
699
700/*@} end of group CMSIS_SCnotSCB */
701
702
703/** \ingroup CMSIS_core_register
704 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
705 \brief Type definitions for the System Timer Registers.
706 @{
707 */
708
709/** \brief Structure type to access the System Timer (SysTick).
710 */
711typedef struct
712{
713 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
714 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
715 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
716 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
717} SysTick_Type;
718
719/* SysTick Control / Status Register Definitions */
720#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
721#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
722
723#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
724#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
725
726#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
727#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
728
729#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
730#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
731
732/* SysTick Reload Register Definitions */
733#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
734#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
735
736/* SysTick Current Register Definitions */
737#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
738#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
739
740/* SysTick Calibration Register Definitions */
741#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
742#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
743
744#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
745#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
746
747#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
748#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
749
750/*@} end of group CMSIS_SysTick */
751
752
753/** \ingroup CMSIS_core_register
754 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
755 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
756 @{
757 */
758
759/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
760 */
761typedef struct
762{
763 __O union
764 {
765 __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
766 __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
767 __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
768 } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
769 uint32_t RESERVED0[864];
770 __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
771 uint32_t RESERVED1[15];
772 __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
773 uint32_t RESERVED2[15];
774 __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
775 uint32_t RESERVED3[29];
776 __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
777 __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
778 __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
779 uint32_t RESERVED4[43];
780 __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
781 __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
782 uint32_t RESERVED5[6];
783 __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
784 __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
785 __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
786 __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
787 __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
788 __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
789 __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
790 __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
791 __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
792 __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
793 __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
794 __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
795} ITM_Type;
796
797/* ITM Trace Privilege Register Definitions */
798#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
799#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
800
801/* ITM Trace Control Register Definitions */
802#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
803#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
804
805#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
806#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
807
808#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
809#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
810
811#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
812#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
813
814#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
815#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
816
817#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
818#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
819
820#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
821#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
822
823#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
824#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
825
826#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
827#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
828
829/* ITM Integration Write Register Definitions */
830#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
831#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
832
833/* ITM Integration Read Register Definitions */
834#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
835#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
836
837/* ITM Integration Mode Control Register Definitions */
838#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
839#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
840
841/* ITM Lock Status Register Definitions */
842#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
843#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
844
845#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
846#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
847
848#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
849#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
850
851/*@}*/ /* end of group CMSIS_ITM */
852
853
854/** \ingroup CMSIS_core_register
855 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
856 \brief Type definitions for the Data Watchpoint and Trace (DWT)
857 @{
858 */
859
860/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
861 */
862typedef struct
863{
864 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
865 __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
866 __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
867 __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
868 __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
869 __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
870 __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
871 __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
872 __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
873 __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
874 __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
875 uint32_t RESERVED0[1];
876 __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
877 __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
878 __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
879 uint32_t RESERVED1[1];
880 __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
881 __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
882 __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
883 uint32_t RESERVED2[1];
884 __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
885 __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
886 __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
887} DWT_Type;
888
889/* DWT Control Register Definitions */
890#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
891#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
892
893#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
894#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
895
896#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
897#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
898
899#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
900#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
901
902#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
903#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
904
905#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
906#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
907
908#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
909#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
910
911#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
912#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
913
914#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
915#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
916
917#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
918#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
919
920#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
921#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
922
923#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
924#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
925
926#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
927#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
928
929#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
930#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
931
932#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
933#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
934
935#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
936#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
937
938#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
939#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
940
941#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
942#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
943
944/* DWT CPI Count Register Definitions */
945#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
946#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
947
948/* DWT Exception Overhead Count Register Definitions */
949#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
950#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
951
952/* DWT Sleep Count Register Definitions */
953#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
954#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
955
956/* DWT LSU Count Register Definitions */
957#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
958#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
959
960/* DWT Folded-instruction Count Register Definitions */
961#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
962#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
963
964/* DWT Comparator Mask Register Definitions */
965#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
966#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
967
968/* DWT Comparator Function Register Definitions */
969#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
970#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
971
972#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
973#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
974
975#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
976#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
977
978#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
979#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
980
981#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
982#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
983
984#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
985#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
986
987#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
988#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
989
990#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
991#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
992
993#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
994#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
995
996/*@}*/ /* end of group CMSIS_DWT */
997
998
999/** \ingroup CMSIS_core_register
1000 \defgroup CMSIS_TPI Trace Port Interface (TPI)
1001 \brief Type definitions for the Trace Port Interface (TPI)
1002 @{
1003 */
1004
1005/** \brief Structure type to access the Trace Port Interface Register (TPI).
1006 */
1007typedef struct
1008{
1009 __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
1010 __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
1011 uint32_t RESERVED0[2];
1012 __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
1013 uint32_t RESERVED1[55];
1014 __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
1015 uint32_t RESERVED2[131];
1016 __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
1017 __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
1018 __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
1019 uint32_t RESERVED3[759];
1020 __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
1021 __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
1022 __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
1023 uint32_t RESERVED4[1];
1024 __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
1025 __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
1026 __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
1027 uint32_t RESERVED5[39];
1028 __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
1029 __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
1030 uint32_t RESERVED7[8];
1031 __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
1032 __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
1033} TPI_Type;
1034
1035/* TPI Asynchronous Clock Prescaler Register Definitions */
1036#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
1037#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
1038
1039/* TPI Selected Pin Protocol Register Definitions */
1040#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
1041#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
1042
1043/* TPI Formatter and Flush Status Register Definitions */
1044#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
1045#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
1046
1047#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
1048#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
1049
1050#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
1051#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
1052
1053#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
1054#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
1055
1056/* TPI Formatter and Flush Control Register Definitions */
1057#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
1058#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
1059
1060#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
1061#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
1062
1063/* TPI TRIGGER Register Definitions */
1064#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
1065#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
1066
1067/* TPI Integration ETM Data Register Definitions (FIFO0) */
1068#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
1069#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
1070
1071#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
1072#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
1073
1074#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
1075#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
1076
1077#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
1078#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
1079
1080#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
1081#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
1082
1083#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
1084#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
1085
1086#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
1087#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
1088
1089/* TPI ITATBCTR2 Register Definitions */
1090#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
1091#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
1092
1093/* TPI Integration ITM Data Register Definitions (FIFO1) */
1094#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
1095#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
1096
1097#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
1098#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
1099
1100#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
1101#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
1102
1103#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
1104#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
1105
1106#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
1107#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
1108
1109#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
1110#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
1111
1112#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
1113#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
1114
1115/* TPI ITATBCTR0 Register Definitions */
1116#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
1117#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
1118
1119/* TPI Integration Mode Control Register Definitions */
1120#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
1121#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
1122
1123/* TPI DEVID Register Definitions */
1124#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
1125#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
1126
1127#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
1128#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
1129
1130#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
1131#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
1132
1133#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
1134#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
1135
1136#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
1137#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
1138
1139#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
1140#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
1141
1142/* TPI DEVTYPE Register Definitions */
1143#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
1144#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
1145
1146#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
1147#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
1148
1149/*@}*/ /* end of group CMSIS_TPI */
1150
1151
1152#if (__MPU_PRESENT == 1)
1153/** \ingroup CMSIS_core_register
1154 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
1155 \brief Type definitions for the Memory Protection Unit (MPU)
1156 @{
1157 */
1158
1159/** \brief Structure type to access the Memory Protection Unit (MPU).
1160 */
1161typedef struct
1162{
1163 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
1164 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
1165 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
1166 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
1167 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
1168 __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
1169 __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
1170 __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
1171 __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
1172 __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
1173 __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
1174} MPU_Type;
1175
1176/* MPU Type Register */
1177#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
1178#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
1179
1180#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
1181#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
1182
1183#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
1184#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
1185
1186/* MPU Control Register */
1187#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
1188#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
1189
1190#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
1191#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
1192
1193#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
1194#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
1195
1196/* MPU Region Number Register */
1197#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
1198#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
1199
1200/* MPU Region Base Address Register */
1201#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
1202#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
1203
1204#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
1205#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
1206
1207#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
1208#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
1209
1210/* MPU Region Attribute and Size Register */
1211#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
1212#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
1213
1214#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
1215#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
1216
1217#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
1218#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
1219
1220#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
1221#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
1222
1223#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
1224#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
1225
1226#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
1227#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
1228
1229#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
1230#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
1231
1232#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
1233#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
1234
1235#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
1236#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
1237
1238#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
1239#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
1240
1241/*@} end of group CMSIS_MPU */
1242#endif
1243
1244
1245#if (__FPU_PRESENT == 1)
1246/** \ingroup CMSIS_core_register
1247 \defgroup CMSIS_FPU Floating Point Unit (FPU)
1248 \brief Type definitions for the Floating Point Unit (FPU)
1249 @{
1250 */
1251
1252/** \brief Structure type to access the Floating Point Unit (FPU).
1253 */
1254typedef struct
1255{
1256 uint32_t RESERVED0[1];
1257 __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
1258 __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
1259 __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
1260 __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
1261 __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
1262} FPU_Type;
1263
1264/* Floating-Point Context Control Register */
1265#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */
1266#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
1267
1268#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */
1269#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
1270
1271#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */
1272#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
1273
1274#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */
1275#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
1276
1277#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */
1278#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
1279
1280#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */
1281#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
1282
1283#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */
1284#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
1285
1286#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */
1287#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
1288
1289#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */
1290#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
1291
1292/* Floating-Point Context Address Register */
1293#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */
1294#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
1295
1296/* Floating-Point Default Status Control Register */
1297#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */
1298#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
1299
1300#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */
1301#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
1302
1303#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */
1304#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
1305
1306#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */
1307#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
1308
1309/* Media and FP Feature Register 0 */
1310#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */
1311#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
1312
1313#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */
1314#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
1315
1316#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */
1317#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
1318
1319#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */
1320#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
1321
1322#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */
1323#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
1324
1325#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */
1326#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
1327
1328#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */
1329#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
1330
1331#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */
1332#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
1333
1334/* Media and FP Feature Register 1 */
1335#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */
1336#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
1337
1338#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */
1339#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
1340
1341#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */
1342#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
1343
1344#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */
1345#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
1346
1347/*@} end of group CMSIS_FPU */
1348#endif
1349
1350
1351/** \ingroup CMSIS_core_register
1352 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
1353 \brief Type definitions for the Core Debug Registers
1354 @{
1355 */
1356
1357/** \brief Structure type to access the Core Debug Register (CoreDebug).
1358 */
1359typedef struct
1360{
1361 __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
1362 __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
1363 __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
1364 __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
1365} CoreDebug_Type;
1366
1367/* Debug Halting Control and Status Register */
1368#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
1369#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
1370
1371#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
1372#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
1373
1374#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
1375#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
1376
1377#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
1378#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
1379
1380#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
1381#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
1382
1383#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
1384#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
1385
1386#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
1387#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
1388
1389#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
1390#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
1391
1392#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
1393#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
1394
1395#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
1396#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
1397
1398#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
1399#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
1400
1401#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
1402#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
1403
1404/* Debug Core Register Selector Register */
1405#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
1406#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
1407
1408#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
1409#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
1410
1411/* Debug Exception and Monitor Control Register */
1412#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
1413#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
1414
1415#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
1416#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
1417
1418#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
1419#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
1420
1421#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
1422#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
1423
1424#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
1425#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
1426
1427#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
1428#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
1429
1430#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
1431#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
1432
1433#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
1434#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
1435
1436#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
1437#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
1438
1439#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
1440#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
1441
1442#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
1443#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
1444
1445#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
1446#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
1447
1448#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
1449#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
1450
1451/*@} end of group CMSIS_CoreDebug */
1452
1453
1454/** \ingroup CMSIS_core_register
1455 \defgroup CMSIS_core_base Core Definitions
1456 \brief Definitions for base addresses, unions, and structures.
1457 @{
1458 */
1459
1460/* Memory mapping of Cortex-M4 Hardware */
1461#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
1462#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
1463#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
1464#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
1465#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
1466#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
1467#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
1468#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
1469
1470#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
1471#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
1472#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
1473#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
1474#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
1475#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
1476#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
1477#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
1478
1479#if (__MPU_PRESENT == 1)
1480 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
1481 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
1482#endif
1483
1484#if (__FPU_PRESENT == 1)
1485 #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
1486 #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
1487#endif
1488
1489/*@} */
1490
1491
1492
1493/*******************************************************************************
1494 * Hardware Abstraction Layer
1495 Core Function Interface contains:
1496 - Core NVIC Functions
1497 - Core SysTick Functions
1498 - Core Debug Functions
1499 - Core Register Access Functions
1500 ******************************************************************************/
1501/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
1502*/
1503
1504
1505
1506/* ########################## NVIC functions #################################### */
1507/** \ingroup CMSIS_Core_FunctionInterface
1508 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
1509 \brief Functions that manage interrupts and exceptions via the NVIC.
1510 @{
1511 */
1512
1513#ifdef CMSIS_NVIC_VIRTUAL
1514 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
1515 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
1516 #endif
1517 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
1518#else
1519 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
1520 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
1521 #define NVIC_EnableIRQ __NVIC_EnableIRQ
1522 #define NVIC_DisableIRQ __NVIC_DisableIRQ
1523 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
1524 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
1525 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
1526 #define NVIC_GetActive __NVIC_GetActive
1527 #define NVIC_SetPriority __NVIC_SetPriority
1528 #define NVIC_GetPriority __NVIC_GetPriority
1529 #define NVIC_SystemReset __NVIC_SystemReset
1530#endif /* CMSIS_NVIC_VIRTUAL */
1531
1532#ifdef CMSIS_VECTAB_VIRTUAL
1533 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
1534 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
1535 #endif
1536 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
1537#else
1538 #define NVIC_SetVector __NVIC_SetVector
1539 #define NVIC_GetVector __NVIC_GetVector
1540#endif /* CMSIS_VECTAB_VIRTUAL */
1541
1542
1543/** \brief Set Priority Grouping
1544
1545 The function sets the priority grouping field using the required unlock sequence.
1546 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
1547 Only values from 0..7 are used.
1548 In case of a conflict between priority grouping and available
1549 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
1550
1551 \param [in] PriorityGroup Priority grouping field.
1552 */
1553__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
1554{
1555 uint32_t reg_value;
1556 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1557
1558 reg_value = SCB->AIRCR; /* read old register configuration */
1559 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
1560 reg_value = (reg_value |
1561 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
1562 (PriorityGroupTmp << 8) ); /* Insert write key and priorty group */
1563 SCB->AIRCR = reg_value;
1564}
1565
1566
1567/** \brief Get Priority Grouping
1568
1569 The function reads the priority grouping field from the NVIC Interrupt Controller.
1570
1571 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
1572 */
1573__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
1574{
1575 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
1576}
1577
1578
1579/** \brief Enable External Interrupt
1580
1581 The function enables a device-specific interrupt in the NVIC interrupt controller.
1582
1583 \param [in] IRQn External interrupt number. Value cannot be negative.
1584 */
1585__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
1586{
1587 NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
1588}
1589
1590
1591/** \brief Disable External Interrupt
1592
1593 The function disables a device-specific interrupt in the NVIC interrupt controller.
1594
1595 \param [in] IRQn External interrupt number. Value cannot be negative.
1596 */
1597__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
1598{
1599 NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
1600 __DSB();
1601 __ISB();
1602}
1603
1604
1605/** \brief Get Pending Interrupt
1606
1607 The function reads the pending register in the NVIC and returns the pending bit
1608 for the specified interrupt.
1609
1610 \param [in] IRQn Interrupt number.
1611
1612 \return 0 Interrupt status is not pending.
1613 \return 1 Interrupt status is pending.
1614 */
1615__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
1616{
1617 return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1618}
1619
1620
1621/** \brief Set Pending Interrupt
1622
1623 The function sets the pending bit of an external interrupt.
1624
1625 \param [in] IRQn Interrupt number. Value cannot be negative.
1626 */
1627__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
1628{
1629 NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
1630}
1631
1632
1633/** \brief Clear Pending Interrupt
1634
1635 The function clears the pending bit of an external interrupt.
1636
1637 \param [in] IRQn External interrupt number. Value cannot be negative.
1638 */
1639__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
1640{
1641 NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
1642}
1643
1644
1645/** \brief Get Active Interrupt
1646
1647 The function reads the active register in NVIC and returns the active bit.
1648
1649 \param [in] IRQn Interrupt number.
1650
1651 \return 0 Interrupt status is not active.
1652 \return 1 Interrupt status is active.
1653 */
1654__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
1655{
1656 return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1657}
1658
1659
1660/** \brief Set Interrupt Priority
1661
1662 The function sets the priority of an interrupt.
1663
1664 \note The priority cannot be set for every core interrupt.
1665
1666 \param [in] IRQn Interrupt number.
1667 \param [in] priority Priority to set.
1668 */
1669__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
1670{
1671 if((int32_t)IRQn < 0) {
1672 SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
1673 }
1674 else {
1675 NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
1676 }
1677}
1678
1679
1680/** \brief Get Interrupt Priority
1681
1682 The function reads the priority of an interrupt. The interrupt
1683 number can be positive to specify an external (device specific)
1684 interrupt, or negative to specify an internal (core) interrupt.
1685
1686
1687 \param [in] IRQn Interrupt number.
1688 \return Interrupt Priority. Value is aligned automatically to the implemented
1689 priority bits of the microcontroller.
1690 */
1691__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
1692{
1693
1694 if((int32_t)IRQn < 0) {
1695 return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
1696 }
1697 else {
1698 return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS)));
1699 }
1700}
1701
1702
1703/** \brief Encode Priority
1704
1705 The function encodes the priority for an interrupt with the given priority group,
1706 preemptive priority value, and subpriority value.
1707 In case of a conflict between priority grouping and available
1708 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
1709
1710 \param [in] PriorityGroup Used priority group.
1711 \param [in] PreemptPriority Preemptive priority value (starting from 0).
1712 \param [in] SubPriority Subpriority value (starting from 0).
1713 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
1714 */
1715__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
1716{
1717 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1718 uint32_t PreemptPriorityBits;
1719 uint32_t SubPriorityBits;
1720
1721 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
1722 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
1723
1724 return (
1725 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
1726 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
1727 );
1728}
1729
1730
1731/** \brief Decode Priority
1732
1733 The function decodes an interrupt priority value with a given priority group to
1734 preemptive priority value and subpriority value.
1735 In case of a conflict between priority grouping and available
1736 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
1737
1738 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
1739 \param [in] PriorityGroup Used priority group.
1740 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
1741 \param [out] pSubPriority Subpriority value (starting from 0).
1742 */
1743__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
1744{
1745 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1746 uint32_t PreemptPriorityBits;
1747 uint32_t SubPriorityBits;
1748
1749 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
1750 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
1751
1752 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
1753 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
1754}
1755
1756
1757/** \brief System Reset
1758
1759 The function initiates a system reset request to reset the MCU.
1760 */
1761__STATIC_INLINE void __NVIC_SystemReset(void)
1762{
1763 __DSB(); /* Ensure all outstanding memory accesses included
1764 buffered write are completed before reset */
1765 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
1766 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
1767 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
1768 __DSB(); /* Ensure completion of memory access */
1769 while(1) { __NOP(); } /* wait until reset */
1770}
1771
1772/*@} end of CMSIS_Core_NVICFunctions */
1773
1774
1775
1776/* ################################## SysTick function ############################################ */
1777/** \ingroup CMSIS_Core_FunctionInterface
1778 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
1779 \brief Functions that configure the System.
1780 @{
1781 */
1782
1783#if (__Vendor_SysTickConfig == 0)
1784
1785/** \brief System Tick Configuration
1786
1787 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
1788 Counter is in free running mode to generate periodic interrupts.
1789
1790 \param [in] ticks Number of ticks between two interrupts.
1791
1792 \return 0 Function succeeded.
1793 \return 1 Function failed.
1794
1795 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
1796 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
1797 must contain a vendor-specific implementation of this function.
1798
1799 */
1800__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
1801{
1802 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
1803
1804 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
1805 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
1806 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
1807 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
1808 SysTick_CTRL_TICKINT_Msk |
1809 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
1810 return (0UL); /* Function successful */
1811}
1812
1813#endif
1814
1815/*@} end of CMSIS_Core_SysTickFunctions */
1816
1817
1818
1819/* ##################################### Debug In/Output function ########################################### */
1820/** \ingroup CMSIS_Core_FunctionInterface
1821 \defgroup CMSIS_core_DebugFunctions ITM Functions
1822 \brief Functions that access the ITM debug interface.
1823 @{
1824 */
1825
1826extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
1827#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
1828
1829
1830/** \brief ITM Send Character
1831
1832 The function transmits a character via the ITM channel 0, and
1833 \li Just returns when no debugger is connected that has booked the output.
1834 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
1835
1836 \param [in] ch Character to transmit.
1837
1838 \returns Character to transmit.
1839 */
1840__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
1841{
1842 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
1843 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
1844 {
1845 while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
1846 ITM->PORT[0].u8 = (uint8_t)ch;
1847 }
1848 return (ch);
1849}
1850
1851
1852/** \brief ITM Receive Character
1853
1854 The function inputs a character via the external variable \ref ITM_RxBuffer.
1855
1856 \return Received character.
1857 \return -1 No character pending.
1858 */
1859__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
1860 int32_t ch = -1; /* no character available */
1861
1862 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
1863 ch = ITM_RxBuffer;
1864 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
1865 }
1866
1867 return (ch);
1868}
1869
1870
1871/** \brief ITM Check Character
1872
1873 The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
1874
1875 \return 0 No character available.
1876 \return 1 Character available.
1877 */
1878__STATIC_INLINE int32_t ITM_CheckChar (void) {
1879
1880 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
1881 return (0); /* no character available */
1882 } else {
1883 return (1); /* character available */
1884 }
1885}
1886
1887/*@} end of CMSIS_core_DebugFunctions */
1888
1889
1890
1891
1892#ifdef __cplusplus
1893}
1894#endif
1895
1896#endif /* __CORE_CM4_H_DEPENDANT */
1897
1898#endif /* __CMSIS_GENERIC */
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