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source: anotherchoice/tags/jsp-1.4.4-full-UTF8/pdic/simple_sio/upd72001.c@ 26

Last change on this file since 26 was 26, checked in by ykominami, 12 years ago
initial
File size: 11.9 KB

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1	/*
2	* TOPPERS/JSP Kernel
3	* Toyohashi Open Platform for Embedded Real-Time Systems/
4	* Just Standard Profile Kernel
5	*
6	* Copyright (C) 2000-2003 by Embedded and Real-Time Systems Laboratory
7	* Toyohashi Univ. of Technology, JAPAN
8	*
9	* ä¸è¨èä½æ¨©è
10	ã¯ï¼ä»¥ä¸ã® (1)ã(4) ã®æ¡ä»¶ãï¼Free Software Foundation
11	* ã«ãã£ã¦å
12	¬è¡¨ããã¦ãã GNU General Public License ã® Version 2 ã«è¨
13	* è¿°ããã¦ããæ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§ã¢ï¼æ¬ã½ããã¦ã§ã¢
14	* ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹å¤ã»åé
15	å¸ï¼ä»¥ä¸ï¼
16	* å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
17	* (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
18	* æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
19	* ã¹ã³ã¼ãä¸ã«å«ã¾ãã¦ãããã¨ï¼
20	* (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
21	* ç¨ã§ããå½¢ã§åé
22	å¸ããå ´åã«ã¯ï¼åé
23	å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨
24	* è
25	ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
26	* ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
27	* (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
28	* ç¨ã§ããªãå½¢ã§åé
29	å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
30	* ã¨ï¼
31	* (a) åé
32	å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨è
33	ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
34	* ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
35	* (b) åé
36	å¸ã®å½¢æ
37	ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSããã¸ã§ã¯ãã«
38	* å ±åãããã¨ï¼
39	* (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
40	* å®³ãããï¼ä¸è¨èä½æ¨©è
41	ããã³TOPPERSããã¸ã§ã¯ããå
42	è²¬ãããã¨ï¼
43	*
44	* æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
45	ã
46	* ãã³TOPPERSããã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ãã®é©ç¨å¯è½æ§ã
47	* å«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´
48	* æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ãã®è²¬ä»»ãè² ããªãï¼
49	*
50	* @(#) $Id: upd72001.c,v 1.4 2003/12/13 06:21:49 hiro Exp $
51	*/
52
53	/*
54	* Î¼PD72001ç¨ ç°¡æSIOãã©ã¤ã
55	*/
56
57	#include <s_services.h>
58	#include <upd72001.h>
59
60	/*
61	* ããã¤ã¹ã¬ã¸ã¹ã¿ã®ã¢ã¯ã»ã¹ééæéï¼nsecåä½ï¼
62	*
63	* 200ã¨ããå¤ã«ãã¾ãæ ¹æ ã¯ãªãï¼
64	*/
65	#define UPD72001_DELAY 200
66
67	/*
68	* Î¼PD72001ã®ã¬ã¸ã¹ã¿ã®çªå·
69	*/
70	#define UPD72001_CR0 0x00u /* ã³ã³ããã¼ã«ã¬ã¸ã¹ã¿ */
71	#define UPD72001_CR1 0x01u
72	#define UPD72001_CR2 0x02u
73	#define UPD72001_CR3 0x03u
74	#define UPD72001_CR4 0x04u
75	#define UPD72001_CR5 0x05u
76	#define UPD72001_CR10 0x0au
77	#define UPD72001_CR12 0x0cu
78	#define UPD72001_CR14 0x0eu
79	#define UPD72001_CR15 0x0fu
80
81	#define UPD72001_SR0 0x00u /* ã¹ãã¼ã¿ã¹ã¬ã¸ã¹ã¿ */
82
83	/*
84	* ã³ã³ããã¼ã«ã¬ã¸ã¹ã¿ã®è¨å®å¤
85	*/
86	#define CR_RESET 0x18u /* ãã¼ããªã»ããã³ãã³ã */
87
88	#define CR0_EOI 0x38u /* EOIï¼End of Interruptï¼*/
89
90	#define CR1_DOWN 0x00u /* å
91	¨å²è¾¼ã¿ãç¦æ¢ */
92	#define CR1_RECV 0x10u /* åä¿¡å²è¾¼ã¿è¨±å¯ããã */
93	#define CR1_SEND 0x02u /* éä¿¡å²è¾¼ã¿è¨±å¯ããã */
94
95	#define CR3_DEF 0xc1u /* ãã¼ã¿ 8bitï¼åä¿¡ã¤ãã¼ãã« */
96	#define CR4_DEF 0x44u /* ã¹ãããããã 1bitï¼ããªãã£ãªã */
97	#define CR5_DEF 0xeau /* ãã¼ã¿ 8bitï¼éä¿¡ã¤ãã¼ãã« */
98
99	#define CR10_DEF 0x00u /* NRZ */
100	#define CR14_DEF 0x07u /* ãã¼ã¬ã¼ãã¸ã§ãã¬ã¼ã¿ã¤ãã¼ãã« */
101	#define CR15_DEF 0x56u /* ãã¼ã¬ã¼ãã¸ã§ãã¬ã¼ã¿ä½¿ç¨ */
102
103	#define SR0_RECV 0x01u /* åä¿¡éç¥ããã */
104	#define SR0_SEND 0x04u /* éä¿¡å¯è½ããã */
105
106	/*
107	* ã·ãªã¢ã«I/Oãã¼ãåæåãããã¯ã®å®ç¾©
108	*/
109	typedef struct sio_port_initialization_block {
110	VP data; /* ãã¼ã¿ã¬ã¸ã¹ã¿ã®çªå° */
111	VP ctrl; /* ã³ã³ããã¼ã«ã¬ã¸ã¹ã¿ã®çªå° */
112
113	UB cr3_def; /* CR3ã®è¨å®å¤ï¼åä¿¡ãããæ°ï¼*/
114	UB cr4_def; /* CR4ã®è¨å®å¤ï¼ã¹ããããããï¼ããªãã£ï¼*/
115	UB cr5_def; /* CR5ã®è¨å®å¤ï¼éä¿¡ãããæ°ï¼*/
116	UB brg1_def; /* ãã¼ã¬ã¼ãä¸ä½ã®è¨å®å¤ */
117	UB brg2_def; /* ãã¼ã¬ã¼ãä¸ä½ã®è¨å®å¤ */
118	} SIOPINIB;
119
120	/*
121	* ã·ãªã¢ã«I/Oãã¼ãç®¡çãããã¯ã®å®ç¾©
122	*/
123	struct sio_port_control_block {
124	const SIOPINIB siopinib; / ã·ãªã¢ã«I/Oãã¼ãåæåãããã¯ */
125	VP_INT exinf; /* æ¡å¼µæ
126	å ± */
127	BOOL openflag; /* ãªã¼ãã³æ¸ã¿ãã©ã° */
128	UB cr1; /* CR1ã®è¨å®å¤ï¼å²è¾¼ã¿è¨±å¯ï¼*/
129	BOOL getready; /* æåãåä¿¡ããç¶æ
130	*/
131	BOOL putready; /* æåãéä¿¡ã§ããç¶æ
132	*/
133	};
134
135	/*
136	* ã·ãªã¢ã«I/Oãã¼ãåæåãããã¯
137	*
138	* ID = 1 ããã¼ãBï¼ID = 2 ããã¼ãAã«å¯¾å¿ããã¦ããï¼
139	*/
140	const SIOPINIB siopinib_table[TNUM_SIOP] = {
141	{ (VP) TADR_UPD72001_DATAB, (VP) TADR_UPD72001_CTRLB,
142	CR3_DEF, CR4_DEF, CR5_DEF, BRG1_DEF, BRG2_DEF },
143	#if TNUM_SIOP >= 2
144	{ (VP) TADR_UPD72001_DATAA, (VP) TADR_UPD72001_CTRLA,
145	CR3_DEF, CR4_DEF, CR5_DEF, BRG1_DEF, BRG2_DEF },
146	#endif /* TNUM_SIOP >= 2 */
147	};
148
149	/*
150	* ã·ãªã¢ã«I/Oãã¼ãç®¡çãããã¯ã®ã¨ãªã¢
151	*/
152	SIOPCB siopcb_table[TNUM_SIOP];
153
154	/*
155	* ã·ãªã¢ã«I/Oãã¼ãIDããç®¡çãããã¯ãåãåºãããã®ãã¯ã
156	*/
157	#define INDEX_SIOP(siopid) ((UINT)((siopid) - 1))
158	#define get_siopcb(siopid) (&(siopcb_table[INDEX_SIOP(siopid)]))
159
160	/*
161	* ããã¤ã¹ã¬ã¸ã¹ã¿ã¸ã®ã¢ã¯ã»ã¹é¢æ°
162	*/
163	Inline UB
164	upd72001_read_reg(VP addr)
165	{
166	UB val;
167
168	val = (UB) upd72001_reb_reg(addr);
169	sil_dly_nse(UPD72001_DELAY);
170	return(val);
171	}
172
173	Inline void
174	upd72001_write_reg(VP addr, UB val)
175	{
176	upd72001_wrb_reg(addr, (VB) val);
177	sil_dly_nse(UPD72001_DELAY);
178	}
179
180	Inline UB
181	upd72001_read_ctrl(VP addr, UB reg)
182	{
183	upd72001_write_reg(addr, reg);
184	return(upd72001_read_reg(addr));
185	}
186
187	Inline void
188	upd72001_write_ctrl(VP addr, UB reg, UB val)
189	{
190	upd72001_write_reg(addr, reg);
191	upd72001_write_reg(addr, val);
192	}
193
194	Inline void
195	upd72001_write_brg(VP addr, UB reg, UB val, UB brg2, UB brg1)
196	{
197	upd72001_write_reg(addr, reg);
198	upd72001_write_reg(addr, val);
199	upd72001_write_reg(addr, brg2);
200	upd72001_write_reg(addr, brg1);
201	(void) upd72001_read_reg(addr); /* ããã¼ãªã¼ã */
202	}
203
204	/*
205	* ç¶æ
206	ã®èªåºãï¼SR0ã®èªåºãï¼
207	*
208	* Î¼PD72001ã¯ï¼ç¶æ
209	ï¼SR0ï¼ãä¸åº¦èªãã¨åä¿¡éç¥ããããè½ã¡ã¦ãã¾ãã
210	* ãï¼ç¶æ
211	ãèªã¿åºãé¢æ°ãè¨ãï¼ã·ãªã¢ã«I/Oãã¼ãç®¡çãããã¯ä¸ã®
212	* getready ã«åä¿¡éç¥ç¶æ
213	ï¼putready ã«éä¿¡å¯è½ç¶æ
214	ãä¿åãã¦ããï¼é
215	* ä¿¡å¯è½ç¶æ
216	ã®ä¿åã¯ä¸è¦ãããããªãï¼ï¼
217	* ç¶æ
218	ã¬ã¸ã¹ã¿ãèªãã§ãåä¿¡éç¥ããããè½ã¡ãªãããã¤ã¹ï¼ãã¡ããæ®
219	* éã¨æãããï¼ã§ã¯ï¼ãã®é¢æ°ã¯å¿
220	è¦ãªãï¼
221	*/
222	static void
223	upd72001_get_stat(SIOPCB *siopcb)
224	{
225	UB sr0;
226
227	sr0 = upd72001_read_ctrl(siopcb->siopinib->ctrl, UPD72001_SR0);
228	if ((sr0 & SR0_RECV) != 0) {
229	siopcb->getready = TRUE;
230	}
231	if ((sr0 & SR0_SEND) != 0) {
232	siopcb->putready = TRUE;
233	}
234	}
235
236	/*
237	* æåãåä¿¡ã§ãããï¼
238	*/
239	Inline BOOL
240	upd72001_getready(SIOPCB *siopcb)
241	{
242	upd72001_get_stat(siopcb);
243	return(siopcb->getready);
244	}
245
246	/*
247	* æåãéä¿¡ã§ãããï¼
248	*/
249	Inline BOOL
250	upd72001_putready(SIOPCB *siopcb)
251	{
252	upd72001_get_stat(siopcb);
253	return(siopcb->putready);
254	}
255
256	/*
257	* åä¿¡ããæåã®ååºã
258	*/
259	Inline char
260	upd72001_getchar(SIOPCB *siopcb)
261	{
262	siopcb->getready = FALSE;
263	return((char) upd72001_read_reg(siopcb->siopinib->data));
264	}
265
266	/*
267	* éä¿¡ããæåã®æ¸è¾¼ã¿
268	*/
269	Inline void
270	upd72001_putchar(SIOPCB *siopcb, char c)
271	{
272	siopcb->putready = FALSE;
273	upd72001_write_reg(siopcb->siopinib->data, (UB) c);
274	}
275
276	/*
277	* EOIï¼End Of Interruptï¼çºè¡
278	*/
279	Inline void
280	upd72001_eoi()
281	{
282	upd72001_write_ctrl((VP) TADR_UPD72001_CTRLA, UPD72001_CR0, CR0_EOI);
283	}
284
285	/*
286	* SIOãã©ã¤ãã®åæåã«ã¼ãã³
287	*/
288	void
289	upd72001_initialize()
290	{
291	SIOPCB *siopcb;
292	UINT i;
293
294	/*
295	* ã·ãªã¢ã«I/Oãã¼ãç®¡çãããã¯ã®åæå
296	*/
297	for (siopcb = siopcb_table, i = 0; i < TNUM_SIOP; siopcb++, i++) {
298	siopcb->siopinib = &(siopinib_table[i]);
299	siopcb->openflag = FALSE;
300	}
301	}
302
303	/*
304	* ãªã¼ãã³ãã¦ãããã¼ãããããï¼
305	*/
306	BOOL
307	upd72001_openflag(void)
308	{
309	#if TNUM_SIOP < 2
310	return(siopcb_table[0].openflag);
311	#else /* TNUM_SIOP < 2 */
312	return(siopcb_table[0].openflag \|\| siopcb_table[1].openflag);
313	#endif /* TNUM_SIOP < 2 */
314	}
315
316	/*
317	* ã·ãªã¢ã«I/Oãã¼ãã®ãªã¼ãã³
318	*/
319	SIOPCB *
320	upd72001_opn_por(ID siopid, VP_INT exinf)
321	{
322	SIOPCB *siopcb;
323	const SIOPINIB *siopinib;
324
325	siopcb = get_siopcb(siopid);
326	siopinib = siopcb->siopinib;
327
328	upd72001_write_reg(siopinib->ctrl, CR_RESET);
329	if (!upd72001_openflag()) {
330	upd72001_write_ctrl((VP) TADR_UPD72001_CTRLA,
331	UPD72001_CR2, 0x18);
332	upd72001_write_ctrl((VP) TADR_UPD72001_CTRLB,
333	UPD72001_CR2, 0x00);
334	}
335	siopcb->cr1 = CR1_DOWN;
336	upd72001_write_ctrl(siopinib->ctrl, UPD72001_CR1, siopcb->cr1);
337	upd72001_write_ctrl(siopinib->ctrl, UPD72001_CR4, siopinib->cr4_def);
338	upd72001_write_brg(siopinib->ctrl, UPD72001_CR12,
339	0x01, siopinib->brg2_def, siopinib->brg1_def);
340	upd72001_write_brg(siopinib->ctrl, UPD72001_CR12,
341	0x02, siopinib->brg2_def, siopinib->brg1_def);
342	upd72001_write_ctrl(siopinib->ctrl, UPD72001_CR15, CR15_DEF);
343	upd72001_write_ctrl(siopinib->ctrl, UPD72001_CR14, CR14_DEF);
344	upd72001_write_ctrl(siopinib->ctrl, UPD72001_CR10, CR10_DEF);
345	upd72001_write_ctrl(siopinib->ctrl, UPD72001_CR3, siopinib->cr3_def);
346	upd72001_write_ctrl(siopinib->ctrl, UPD72001_CR5, siopinib->cr5_def);
347	siopcb->exinf = exinf;
348	siopcb->getready = siopcb->putready = FALSE;
349	siopcb->openflag = TRUE;
350	return(siopcb);
351	}
352
353	/*
354	* ã·ãªã¢ã«I/Oãã¼ãã®ã¯ãã¼ãº
355	*/
356	void
357	upd72001_cls_por(SIOPCB *siopcb)
358	{
359	upd72001_write_ctrl(siopcb->siopinib->ctrl, UPD72001_CR1, CR1_DOWN);
360	siopcb->openflag = FALSE;
361	}
362
363	/*
364	* ã·ãªã¢ã«I/Oãã¼ãã¸ã®æåéä¿¡
365	*/
366	BOOL
367	upd72001_snd_chr(SIOPCB *siopcb, char c)
368	{
369	if (upd72001_putready(siopcb)) {
370	upd72001_putchar(siopcb, c);
371	return(TRUE);
372	}
373	return(FALSE);
374	}
375
376	/*
377	* ã·ãªã¢ã«I/Oãã¼ãããã®æååä¿¡
378	*/
379	INT
380	upd72001_rcv_chr(SIOPCB *siopcb)
381	{
382	if (upd72001_getready(siopcb)) {
383	return((INT)(UB) upd72001_getchar(siopcb));
384	}
385	return(-1);
386	}
387
388	/*
389	* ã·ãªã¢ã«I/Oãã¼ãããã®ã³ã¼ã«ããã¯ã®è¨±å¯
390	*/
391	void
392	upd72001_ena_cbr(SIOPCB *siopcb, UINT cbrtn)
393	{
394	UB cr1_bit = 0;
395
396	switch (cbrtn) {
397	case SIO_ERDY_SND:
398	cr1_bit = CR1_SEND;
399	break;
400	case SIO_ERDY_RCV:
401	cr1_bit = CR1_RECV;
402	break;
403	}
404	siopcb->cr1 \|= cr1_bit;
405	upd72001_write_ctrl(siopcb->siopinib->ctrl, UPD72001_CR1, siopcb->cr1);
406	}
407
408	/*
409	* ã·ãªã¢ã«I/Oãã¼ãããã®ã³ã¼ã«ããã¯ã®ç¦æ¢
410	*/
411	void
412	upd72001_dis_cbr(SIOPCB *siopcb, UINT cbrtn)
413	{
414	UB cr1_bit = 0;
415
416	switch (cbrtn) {
417	case SIO_ERDY_SND:
418	cr1_bit = CR1_SEND;
419	break;
420	case SIO_ERDY_RCV:
421	cr1_bit = CR1_RECV;
422	break;
423	}
424	siopcb->cr1 &= ~cr1_bit;
425	upd72001_write_ctrl(siopcb->siopinib->ctrl, UPD72001_CR1, siopcb->cr1);
426	}
427
428	/*
429	* ã·ãªã¢ã«I/Oãã¼ãã«å¯¾ããå²è¾¼ã¿å¦ç
430	*/
431	static void
432	upd72001_isr_siop(SIOPCB *siopcb)
433	{
434	if ((siopcb->cr1 & CR1_RECV) != 0 && upd72001_getready(siopcb)) {
435	/*
436	* åä¿¡éç¥ã³ã¼ã«ããã¯ã«ã¼ãã³ãå¼ã³åºãï¼
437	*/
438	upd72001_ierdy_rcv(siopcb->exinf);
439	}
440	if ((siopcb->cr1 & CR1_SEND) != 0 && upd72001_putready(siopcb)) {
441	/*
442	* éä¿¡å¯è½ã³ã¼ã«ããã¯ã«ã¼ãã³ãå¼ã³åºãï¼
443	*/
444	upd72001_ierdy_snd(siopcb->exinf);
445	}
446	}
447
448	/*
449	* SIOã®å²è¾¼ã¿ãµã¼ãã¹ã«ã¼ãã³
450	*/
451	void
452	upd72001_isr()
453	{
454	if (siopcb_table[0].openflag) {
455	upd72001_isr_siop(&(siopcb_table[0]));
456	}
457	#if TNUM_SIOP >= 2
458	if (siopcb_table[1].openflag) {
459	upd72001_isr_siop(&(siopcb_table[1]));
460	}
461	#endif /* TNUM_SIOP >= 2 */
462	upd72001_eoi();
463	}

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