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tl16pir552.c@ 363

Last change on this file since 363 was 363, checked in by ykominami, 5 years ago
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1	/*
2	* TOPPERS/JSP Kernel
3	* Toyohashi Open Platform for Embedded Real-Time Systems/
4	* Just Standard Profile Kernel
5	*
6	* Copyright (C) 2000-2003 by Embedded and Real-Time Systems Laboratory
7	* Toyohashi Univ. of Technology, JAPAN
8	* Copyright (C) 2000-2003 by Industrial Technology Institute,
9	* Miyagi Prefectural Government, JAPAN
10	*
11	* ä¸è¨èä½æ¨©è
12	ã¯ï¼ä»¥ä¸ã® (1)ã(4) ã®æ¡ä»¶ãï¼Free Software Foundation
13	* ã«ãã£ã¦å
14	¬è¡¨ããã¦ãã GNU General Public License ã® Version 2 ã«è¨
15	* è¿°ããã¦ããæ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§ã¢ï¼æ¬ã½ããã¦ã§ã¢
16	* ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹å¤ã»åé
17	å¸ï¼ä»¥ä¸ï¼
18	* å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
19	* (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
20	* æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
21	* ã¹ã³ã¼ãä¸ã«å«ã¾ãã¦ãããã¨ï¼
22	* (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
23	* ç¨ã§ããå½¢ã§åé
24	å¸ããå ´åã«ã¯ï¼åé
25	å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨
26	* è
27	ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
28	* ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
29	* (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
30	* ç¨ã§ããªãå½¢ã§åé
31	å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
32	* ã¨ï¼
33	* (a) åé
34	å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨è
35	ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
36	* ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
37	* (b) åé
38	å¸ã®å½¢æ
39	ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSããã¸ã§ã¯ãã«
40	* å ±åãããã¨ï¼
41	* (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
42	* å®³ãããï¼ä¸è¨èä½æ¨©è
43	ããã³TOPPERSããã¸ã§ã¯ããå
44	è²¬ãããã¨ï¼
45	*
46	* æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
47	ã
48	* ãã³TOPPERSããã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ãã®é©ç¨å¯è½æ§ã
49	* å«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´
50	* æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ãã®è²¬ä»»ãè² ããªãï¼
51	*
52	*/
53
54	#include <tl16pir552.h>
55
56	/*
57	* TL16PIR552(TI)ç¨ ç°¡æSIOãã©ã¤ã
58	*/
59
60	/*
61	* ã·ãªã¢ã«I/Oãã¼ãåæåãããã¯ã®å®ç¾©
62	*/
63	typedef struct sio_port_initialization_block {
64	VP channel_addr; /* ã·ãªã¢ã«ãã¼ãã®éå§çªå° */
65
66	UB lcr_def; /* LCRè¨å®å¤ b0-b6;
67	(éåä¿¡ãããæ°ãã¹ããããããï¼ããªãã£) */
68	UB scr_def; /* SCRè¨å®å¤ï¼ããªã¹ã±ã¼ã©ï¼ï¼*/
69	UB boud_hi_def; /* DLMè¨å®å¤ï¼ãã¼ã¬ã¼ãä¸ä½ã®è¨å®å¤ï¼ */
70	UB boud_lo_def; /* DLLè¨å®å¤ï¼ãã¼ã¬ã¼ãä¸ä½ã®è¨å®å¤ï¼ */
71	} SIOPINIB;
72
73	/*
74	* ã·ãªã¢ã«I/Oãã¼ãç®¡çãããã¯ã®å®ç¾©
75	*/
76	struct sio_port_control_block {
77	const SIOPINIB siopinib; / ã·ãªã¢ã«I/Oãã¼ãåæåãããã¯ */
78	VP_INT exinf; /* æ¡å¼µæ
79	å ± */
80	BOOL openflag; /* ãªã¼ãã³æ¸ã¿ãã©ã° */
81	BOOL getready; /* æåãåä¿¡ããç¶æ
82	*/
83	BOOL putready; /* æåãéä¿¡ã§ããç¶æ
84	*/
85	};
86
87	/*
88	* ã·ãªã¢ã«I/Oãã¼ãåæåãããã¯
89	* ID = 1 ããã¼ã1ï¼ID = 2 ããã¼ã2ã«å¯¾å¿ããã¦ããï¼
90	*/
91	const SIOPINIB siopinib_table[TNUM_SIOP] = {
92	{ (VP) UART_CH01,
93	(UB) WORD_LENGTH_8 \| STOP_BITS_1 \| PARITY_NON,
94	(UB) PRE_DIVISOR,
95	(UB) HI8(DIVISOR),
96	(UB) LO8(DIVISOR) },
97	#if TNUM_SIOP >= 2
98	{ (VP) UART_CH02,
99	(UB) WORD_LENGTH_8 \| STOP_BITS_1 \| PARITY_NON,
100	(UB) PRE_DIVISOR,
101	(UB) HI8(DIVISOR),
102	(UB) LO8(DIVISOR) },
103	#endif /* TNUM_SIOP >= 2 */
104	};
105
106	/*
107	* ã·ãªã¢ã«I/Oãã¼ãåæåãããã¯ã®ååºã
108	*/
109	#define INDEX_SIOPINIB(siopid) ((UINT)((siopid) - 1))
110	#define get_siopinib(siopid) (&(siopinib_table[INDEX_SIOPINIB(siopid)]))
111
112
113	/*
114	* ã·ãªã¢ã«I/Oãã¼ãç®¡çãããã¯ã®ã¨ãªã¢
115	*/
116	SIOPCB siopcb_table[TNUM_SIOP];
117
118	/*
119	* ã·ãªã¢ã«I/Oãã¼ãIDããç®¡çãããã¯ãåãåºãããã®ãã¯ã
120	*/
121	#define INDEX_SIOP(siopid) ((UINT)((siopid) - 1))
122	#define get_siopcb(siopid) (&(siopcb_table[INDEX_SIOP(siopid)]))
123
124	/*
125	* SIOç¨ã¬ã¸ã¹ã¿æä½é¢æ°
126	*/
127	Inline void
128	tl16pir552_orb( VP addr, UW reg, UB val )
129	{
130	tl16pir552_wrb( addr, reg, tl16pir552_reb( addr, reg ) \| val );
131	}
132
133	Inline void
134	tl16pir552_andb( VP addr, UW reg, UB val )
135	{
136	tl16pir552_wrb( addr, reg, tl16pir552_reb( addr, reg ) & val );
137	}
138
139
140	/*
141	* ç¶æ
142	ã®èªåºãï¼IIRã®èªåºãï¼
143	*/
144	static void
145	tl16pir552_get_stat(SIOPCB *siopcb)
146	{
147	UB iir;
148
149	iir = tl16pir552_reb( siopcb->siopinib->channel_addr, IIR) & INT_MASK;
150
151	switch( iir ) {
152	case INT_TRANS_EMPTY :
153	siopcb->putready = TRUE;
154	break;
155	case INT_RECEIVE_DATA :
156	case INT_CHAR_TIME_OUT :
157	siopcb->getready = TRUE;
158	break;
159	default :
160	break;
161	}
162
163	}
164
165	/*
166	* æåãåä¿¡ã§ãããï¼
167	*/
168	Inline BOOL
169	tl16pir552_getready(SIOPCB *siopcb)
170	{
171	return(siopcb->getready);
172	}
173
174	/*
175	* æåãéä¿¡ã§ãããï¼
176	*/
177	Inline BOOL
178	tl16pir552_putready(SIOPCB *siopcb)
179	{
180	return(siopcb->putready);
181	}
182
183	/*
184	* åä¿¡ããæåã®ååºã
185	*/
186	Inline char
187	tl16pir552_getchar(SIOPCB *siopcb)
188	{
189	siopcb->getready = FALSE;
190	return((char) tl16pir552_reb( siopcb->siopinib->channel_addr, RBR ));
191	/* 1byte åä½ã§ã®æåã®åãåºããè¡ã£ããããããtl16pir552_opn_porå
192	ã®
193	åä¿¡ãããã¡è¨å®ãå¢ãããã¨ãã¦ãæ§è½ã®åä¸ã¯è¦ãããªãã
194	æ§è½ã®åä¸ã«ã¯ããããã¡å
195	¨ä½ã®ãããã¯è»¢éãè¡ããªã©ã®ä¿®æ£ãå¿
196	è¦ã*/
197	}
198
199	/*
200	* éä¿¡ããæåã®æ¸è¾¼ã¿
201	*/
202	Inline void
203	tl16pir552_putchar(SIOPCB *siopcb, char c)
204	{
205	siopcb->putready = FALSE;
206	tl16pir552_wrb( siopcb->siopinib->channel_addr, THR, c );
207	}
208
209	/*
210	* SIOãã©ã¤ãã®åæåã«ã¼ãã³
211	*/
212	void
213	tl16pir552_initialize()
214	{
215	SIOPCB *siopcb;
216	UINT i;
217
218	/*
219	* ã·ãªã¢ã«I/Oãã¼ãç®¡çãããã¯ã®åæå
220	*/
221	for (siopcb = siopcb_table, i = 0; i < TNUM_SIOP; siopcb++, i++) {
222	siopcb->siopinib = &(siopinib_table[i]);
223	siopcb->openflag = FALSE;
224	}
225	}
226
227	/*
228	* SIOã¬ã¸ã¹ã¿åæåã«ã¼ãã³
229	*/
230	void
231	tl16pir552_init_siopinib( const SIOPINIB *siopinib )
232	{
233	/*
234	* SIOã¬ã¸ã¹ã¿ã®åæå
235	*/
236	/* åæå¦ç */
237	tl16pir552_wrb( siopinib->channel_addr, IER, DIS_INT );
238
239	tl16pir552_wrb( siopinib->channel_addr, MCR, ENABLE_EXT_INT );
240
241	/* ãã¼ã¬ã¼ãã®è¨å® */
242	tl16pir552_wrb( siopinib->channel_addr, LCR, siopinib->lcr_def \| DIVISOR_LATCH_ACC );
243
244	tl16pir552_wrb( siopinib->channel_addr, SCR, siopinib->scr_def );
245
246	tl16pir552_wrb( siopinib->channel_addr, DLL, siopinib->boud_lo_def );
247	tl16pir552_wrb( siopinib->channel_addr, DLM, siopinib->boud_hi_def );
248
249	/* ã¢ã¼ãã®è¨å® */
250	tl16pir552_wrb( siopinib->channel_addr, LCR, siopinib->lcr_def );
251
252	/* FIFOã®è¨å® */
253	tl16pir552_wrb( siopinib->channel_addr, FCR, FIFO_ENABLE );
254	tl16pir552_wrb( siopinib->channel_addr, FCR, FIFO_ENABLE \| RECEIVE_FIFO_RESET \| TRANS_FIFO_RESET \| RECEIVE_TRIG_1_BYTE );
255	tl16pir552_wrb( siopinib->channel_addr, FCR, FIFO_ENABLE \| RECEIVE_TRIG_1_BYTE );
256
257	/* çµäºå¦ç */
258	tl16pir552_wrb( siopinib->channel_addr, MCR, DTR \| RTS \| ENABLE_EXT_INT );
259
260	tl16pir552_wrb( siopinib->channel_addr, IER, RECEIVE_DATA_AVAILABLE);
261	}
262
263	/*
264	* ã«ã¼ãã«èµ·åæã®ãã¼ãã¼åºåç¨ã®åæå
265	*/
266	void
267	tl16pir552_init(void)
268	{
269	tl16pir552_init_siopinib( get_siopinib(1) );
270	#if TNUM_SIOP >= 2
271	tl16pir552_init_siopinib( get_siopinib(2) );
272	#endif /* TNUM_SIOP >= 2 */
273	}
274
275	/*
276	* ãªã¼ãã³ãã¦ãããã¼ãããããï¼
277	*/
278	BOOL
279	tl16pir552_openflag(void)
280	{
281	#if TNUM_SIOP < 2
282	return(siopcb_table[0].openflag);
283	#else /* TNUM_SIOP < 2 */
284	return(siopcb_table[0].openflag \|\| siopcb_table[1].openflag);
285	#endif /* TNUM_SIOP < 2 */
286	}
287
288	/*
289	* ã·ãªã¢ã«I/Oãã¼ãã®ãªã¼ãã³
290	*/
291	SIOPCB *
292	tl16pir552_opn_por(ID siopid, VP_INT exinf)
293	{
294	SIOPCB *siopcb = get_siopcb(siopid);
295	const SIOPINIB *siopinib = siopcb->siopinib;
296
297	/* ã·ãªã¢ã«ã³ã³ããã¼ã©ã®åæå */
298	tl16pir552_init_siopinib( siopinib );
299
300	/* å²è¾¼ã¿ã¬ãã«è¨å®ãå²è¾¼ã¿è¦æ±ã¯ãªã¢ã¯ãsio_opn_por(hw_serial.h)ã§è¡ãã */
301
302	siopcb->exinf = exinf;
303	siopcb->getready = siopcb->putready = FALSE;
304	siopcb->openflag = TRUE;
305
306	return(siopcb);
307	}
308
309	/*
310	* ã·ãªã¢ã«I/Oãã¼ãã®ã¯ãã¼ãº
311	*/
312	void
313	tl16pir552_cls_por(SIOPCB *siopcb)
314	{
315	tl16pir552_wrb( siopcb->siopinib->channel_addr, IER, DIS_INT );
316
317	siopcb->openflag = FALSE;
318	}
319
320	/*
321	* ã·ãªã¢ã«I/Oãã¼ãã¸ã®æåéä¿¡
322	*/
323	BOOL
324	tl16pir552_snd_chr(SIOPCB *siopcb, char c)
325	{
326	if (tl16pir552_putready(siopcb)) {
327	tl16pir552_putchar(siopcb, c);
328	return(TRUE);
329	}
330	return(FALSE);
331	}
332
333	/*
334	* ã·ãªã¢ã«I/Oãã¼ãããã®æååä¿¡
335	*/
336	INT
337	tl16pir552_rcv_chr(SIOPCB *siopcb)
338	{
339	if (tl16pir552_getready(siopcb)) {
340	return((INT)(UB) tl16pir552_getchar(siopcb));
341	}
342	return(-1);
343	}
344
345	/*
346	* ã·ãªã¢ã«I/Oãã¼ãããã®ã³ã¼ã«ããã¯ã®è¨±å¯
347	*/
348	void
349	tl16pir552_ena_cbr(SIOPCB *siopcb, UINT cbrtn)
350	{
351	UB ier_bit = 0;
352
353	switch (cbrtn) {
354	case SIO_ERDY_SND:
355	ier_bit = TRANS_REG_EMPTY;
356	break;
357	case SIO_ERDY_RCV:
358	ier_bit = (RECEIVE_DATA_AVAILABLE \| RECEIVE_LINE_STATUS);
359	break;
360	}
361
362	tl16pir552_orb( siopcb->siopinib->channel_addr, IER, ier_bit );
363	}
364
365	/*
366	* ã·ãªã¢ã«I/Oãã¼ãããã®ã³ã¼ã«ããã¯ã®ç¦æ¢
367	*/
368	void
369	tl16pir552_dis_cbr(SIOPCB *siopcb, UINT cbrtn)
370	{
371	UB ier_bit = 0;
372
373	switch (cbrtn) {
374	case SIO_ERDY_SND:
375	ier_bit = TRANS_REG_EMPTY;
376	break;
377	case SIO_ERDY_RCV:
378	ier_bit = (RECEIVE_DATA_AVAILABLE \| RECEIVE_LINE_STATUS);
379	break;
380	}
381
382	tl16pir552_andb( siopcb->siopinib->channel_addr, IER, ~ier_bit );
383	}
384
385	/*
386	* ã·ãªã¢ã«I/Oãã¼ãã«å¯¾ããå²è¾¼ã¿å¦ç
387	*/
388	static void
389	tl16pir552_isr_siop(SIOPCB *siopcb)
390	{
391	tl16pir552_get_stat(siopcb);
392
393	if ( tl16pir552_getready(siopcb) ) {
394	/*
395	* åä¿¡éç¥ã³ã¼ã«ããã¯ã«ã¼ãã³ãå¼ã³åºãï¼
396	*/
397	tl16pir552_ierdy_rcv(siopcb->exinf);
398	} else if ( tl16pir552_putready(siopcb) ) {
399	/*
400	* éä¿¡å¯è½ã³ã¼ã«ããã¯ã«ã¼ãã³ãå¼ã³åºãï¼
401	*/
402	tl16pir552_ierdy_snd(siopcb->exinf);
403	}
404	}
405
406	/*
407	* SIOã®å²è¾¼ã¿ãµã¼ãã¹ã«ã¼ãã³
408	*/
409	void
410	tl16pir552_uart0_isr()
411	{
412	if (siopcb_table[0].openflag) {
413	tl16pir552_isr_siop(&(siopcb_table[0]));
414	}
415	}
416
417	#if TNUM_SIOP >= 2
418	void
419	tl16pir552_uart1_isr()
420	{
421	if (siopcb_table[1].openflag) {
422	tl16pir552_isr_siop(&(siopcb_table[1]));
423	}
424	}
425	#endif /* TNUM_SIOP >= 2 */
426
427	/*
428	* ã·ãªã¢ã«I/Oãã¼ãã¸ã®ãã¼ãªã³ã°ã§ã®åºå
429	*/
430	void
431	tl16pir552_putchar_pol( char val ) {
432
433	const SIOPINIB *siopinib = get_siopinib( LOGTASK_PORTID );
434
435	/* éä¿¡é¨ã¨ã³ããã£ã«ãªãã¾ã§å¾
436	ã¤ã */
437	while( (tl16pir552_reb( siopinib->channel_addr, LSR ) & (TEMT) ) == 0 );
438
439	tl16pir552_wrb( siopinib->channel_addr, THR, val );
440	}

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