[26] | 1 | /*
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| 2 | * TOPPERS/JSP Kernel
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| 3 | * Toyohashi Open Platform for Embedded Real-Time Systems/
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| 4 | * Just Standard Profile Kernel
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| 5 | *
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| 6 | * Copyright (C) 2000-2004 by Embedded and Real-Time Systems Laboratory
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| 7 | * Toyohashi Univ. of Technology, JAPAN
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| 8 | * Copyright (C) 2001-2004 by Industrial Technology Institute,
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| 9 | * Miyagi Prefectural Government, JAPAN
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| 10 | *
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| 11 | * ä¸è¨èä½æ¨©è
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| 12 | ã¯ï¼ä»¥ä¸ã® (1)ã(4) ã®æ¡ä»¶ãï¼Free Software Foundation
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| 13 | * ã«ãã£ã¦å
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| 14 | ¬è¡¨ããã¦ãã GNU General Public License ã® Version 2 ã«è¨
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| 15 | * è¿°ããã¦ããæ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§ã¢ï¼æ¬ã½ããã¦ã§ã¢
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| 16 | * ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ã使ç¨ã»è¤è£½ã»æ¹å¤ã»åé
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| 17 | å¸ï¼ä»¥ä¸ï¼
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| 18 | * å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
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| 19 | * (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
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| 20 | * 権表示ï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
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| 21 | * ã¹ã³ã¼ãä¸ã«å«ã¾ãã¦ãããã¨ï¼
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| 22 | * (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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| 23 | * ç¨ã§ããå½¢ã§åé
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| 24 | å¸ããå ´åã«ã¯ï¼åé
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| 25 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨
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| 26 | * è
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| 27 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
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| 28 | * ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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| 29 | * (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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| 30 | * ç¨ã§ããªãå½¢ã§åé
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| 31 | å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
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| 32 | * ã¨ï¼
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| 33 | * (a) åé
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| 34 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨è
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| 35 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
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| 36 | * ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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| 37 | * (b) åé
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| 38 | å¸ã®å½¢æ
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| 39 | ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSããã¸ã§ã¯ãã«
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| 40 | * å ±åãããã¨ï¼
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| 41 | * (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
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| 42 | * 害ãããï¼ä¸è¨èä½æ¨©è
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| 43 | ããã³TOPPERSããã¸ã§ã¯ããå
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| 44 | 責ãããã¨ï¼
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| 45 | *
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| 46 | * æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
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| 47 | ã
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| 48 | * ãã³TOPPERSããã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ãã®é©ç¨å¯è½æ§ã
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| 49 | * å«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´
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| 50 | * æ¥çã¾ãã¯éæ¥çã«çãããããªãæ害ã«é¢ãã¦ãï¼ãã®è²¬ä»»ãè² ããªãï¼
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| 51 | *
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| 52 | * @(#) $Id: vea_oea_emb.h,v 1.2 2004/10/07 17:10:56 honda Exp $
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| 53 | */
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| 54 |
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| 55 | /*
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| 56 | * PowerPCã¢ã¼ããã¯ãã£VEA,OEAä¾åã®å®ç¾©
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| 57 | * ãThe IBM PowerPC Embedded Environmentã®å ´å
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| 58 | * ããIBMç³»PowerPC40xãã¡ããªãã¡ãã«è©²å½ããã
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| 59 | * ã
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| 60 | * ãPowerPCã¢ã¼ããã¯ãã£ã®å®ç¾©ã¯ä»¥ä¸ã®ï¼ã¤ã®ã¬ãã«ããæã
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| 61 | * ãã»USIA:User Instruction Set Architecture
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| 62 | * ãã»VEA: Virtual Environment Architecture
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| 63 | * ãã»OEA: Operating Environment Architecture
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| 64 | * ã
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| 65 | * ãUSIAã«ã¤ãã¦ã¯å
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| 66 | ¨æ©ç¨®å
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| 67 | ±éã§ããããVEAã¨OEAã«ã¤ãã¦ã¯
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| 68 | * ããªãªã¸ãã«ã®PowerPCã¢ã¼ããã¯ãã£ã¨The IBM PowerPC
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| 69 | * ãEmbedded Environmentããããå¥ã«å®ç¾©ããã¦ããããã
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| 70 | * ãVEAã¨OEAã®å®ç¾©ã¯ãã¡ã¤ã«ãåãã¦ããããã¤ã³ã¯ã«ã¼ã
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| 71 | * ããã¦ããã
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| 72 | */
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| 73 |
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| 74 |
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| 75 | #ifndef _VEA_OEA_EMB_H_
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| 76 | #define _VEA_OEA_EMB_H_
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| 77 |
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| 78 | /*
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| 79 | * ã¬ã¸ã¹ã¿çªå·ã®å®ç¾©
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| 80 | */
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| 81 |
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| 82 | /*
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| 83 | * Special Purpose Registerã®ã¬ã¸ã¹ã¿çªå·
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| 84 | * ãã(*)å°ï¼å
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| 85 | ã®PowerPCã¢ã¼ããã¯ãã£ã§ã¯å®ç¾©ããã¦ããªãã¬ã¸ã¹ã¿
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| 86 | */
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| 87 |
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| 88 | /*
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| 89 | * ä¾å¤å¦çã«é¢ããã¬ã¸ã¹ã¿
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| 90 | */
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| 91 | #define SRR0 26 /* Save/Restore Register0 */
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| 92 | #define SRR1 27 /* Save/Restore Register1 */
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| 93 | #define SRR2 990 /* Save/Restore Register2(*) */
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| 94 | #define SRR3 991 /* Save/Restore Register3(*) */
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| 95 | #define ESR 980 /* Exception Syndrome Register(*) */
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| 96 | #define DEAR 981 /* Data Exception Address Register(*) */
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| 97 | #define EVPR 982 /* Exception Vector Prefix Register(*) */
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| 98 |
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| 99 | #define SPRG0 272 /* SPR General 0 */
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| 100 | #define SPRG1 273 /* SPR General 1 */
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| 101 | #define SPRG2 274 /* SPR General 2 */
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| 102 | #define SPRG3 275 /* SPR General 3 */
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| 103 |
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| 104 | /*
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| 105 | * ãã®ä»ã®ã¬ã¸ã¹ã¿
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| 106 | */
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| 107 | #define DAC 1014 /* Data Address Compare(*) */
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| 108 | #define DBCR 1010 /* Debug Control Register(*) */
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| 109 | #define DBSR 1008 /* Debug Status Register(*) */
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| 110 | #define DCCR 1018 /* Data Cache Cacheability Register(*) */
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| 111 | #define DCWR 954 /* Data Cache Write-thru Register(*) */
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| 112 |
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| 113 | #define IAC 1012 /* Instruction Address Compare(*) */
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| 114 | #define ICCR 1019 /* Instruction Cache Cacheability Register(*) */
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| 115 |
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| 116 | #define PID 945 /* Process ID Register */
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| 117 | #define PIT 987 /* Programmable Interval Timer(*) */
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| 118 | #define PVR 287 /* Processor Version Register */
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| 119 |
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| 120 | #define SGR 953 /* Storage Guarded Register(*) */
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| 121 | #define SLER 955 /* Storage Little-Endian Register(*) */
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| 122 | #define SMR 952 /* Storage Memory-Coherent Register(*) */
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| 123 |
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| 124 | /* VEA */
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| 125 | #define TBL 268 /* Time Base Lower(for read) */
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| 126 | #define TBU 269 /* Time Base Upper(for read) */
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| 127 | /* OEA */
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| 128 | #define TBLw 284 /* Time Base Lower(for write) */
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| 129 | #define TBUw 285 /* Time Base Upper(for write) */
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| 130 |
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| 131 | #define TCR 986 /* Timer Control Registe(*) */
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| 132 | #define TSR 984 /* Timer Status Register(*) */
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| 133 | #define ZPR 944 /* Zone Protection Register(*) */
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| 134 |
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| 135 | /*
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| 136 | * MSRã®ãããé
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| 137 | å
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| 138 | */
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| 139 | /* 0-10:Reserved */
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| 140 | #define MSR_APE BIT11_32 /* Auxiliary Processor Exception Enable */
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| 141 | #define MSR_APA BIT12_32 /* Auxiliary Processor Available */
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| 142 | #define MSR_WE BIT13_32 /* Wait State Enable */
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| 143 | #define MSR_CE BIT14_32 /* Critical Enable */
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| 144 | #define MSR_ILE BIT15_32 /* Interrupt Little Endian */
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| 145 | #define MSR_EE BIT16_32 /* External Enable */
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| 146 | #define MSR_PR BIT17_32 /* Problem State */
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| 147 | #define MSR_FP BIT18_32 /* Floating Point Available */
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| 148 | #define MSR_ME BIT19_32 /* Machine Check Enable */
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| 149 | #define MSR_FE0 BIT20_32 /* Floating Point Exception Mode 0 */
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| 150 | /* 21:Reserved */
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| 151 | #define MSR_DE BIT22_32 /* Debug Interrupts Enable */
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| 152 | #define MSR_FE1 BIT23_32 /* Floating Point Exception Mode 1 */
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| 153 | /* 23-25:Reserved */
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| 154 | #define MSR_IR BIT26_32 /* Instruction Relocate */
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| 155 | #define MSR_DR BIT27_32 /* Data Relocate */
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| 156 | /* 28-30:Reserved */
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| 157 | #define MSR_LE BIT31_32 /* Little Endian */
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| 158 |
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| 159 |
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| 160 | /*
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| 161 | * ESR(Exception Syndrome Register)ã®ãããé
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| 162 | å
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| 163 | */
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| 164 | #define ESR_PIL BIT4_32 /* Program - Illegal Instruction exception */
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| 165 | #define ESR_PPR BIT5_32 /* Program - Privileged Instruction exception */
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| 166 | #define ESR_PTR BIT6_32 /* Program - Trap exception */
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| 167 | #define ESR_PFE BIT7_32 /* Program - Floating Point Enabled exception */
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| 168 | #define ESR_DST BIT8_32 /* Data Storage / Data TLB Miss - Store Operations */
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| 169 | #define ESR_DIZ BIT9_32 /* Data / Instruction Storage - Zone exception */
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| 170 | /* Program - Auxiliary Processor Unavailable exception */
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| 171 | #define ESR_PAU BIT12_32
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| 172 | /* Program - Floating Point Enabled but Unimplemented exception */
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| 173 | #define ESR_PFEU BIT13_32
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| 174 | /* Program - Auxiliary Processor Enabled exception */
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| 175 | #define ESR_PAE BIT14_32
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| 176 |
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| 177 |
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| 178 | /*
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| 179 | * CPUä¾å¤è¦å ã®å®ç¾©
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| 180 | * ãçªå·ãä¸é£ç¶ãªã®ã§CPUä¾å¤æ¬ä¼¼ãã¯ã¿ãã¼ãã«ã«ä¸é¨ç¡é§ãå
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| 181 | ¥ããã
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| 182 | * ãPowerPCã¢ã¼ããã¯ãã£ã®å®ç¾©ã«åãããæ¹ãåªå
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| 183 | ããã
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| 184 | */
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| 185 | #define EXC_NO_CRITICAL_INPUT 0x1
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| 186 | #define EXC_NO_MACHINE_CHECK 0x2
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| 187 | #define EXC_NO_DATA_STORAGE 0x3
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| 188 | #define EXC_NO_INSTRUCTION_STORAGE 0x4
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| 189 | #define EXC_NO_EXTERNAL_INTERRUPT 0x5 /* å¤é¨å²è¾¼ã¿ */
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| 190 | #define EXC_NO_ALIGNMENT 0x6
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| 191 | /* ããã°ã©ã ä¾å¤ï¼è¦å ï¼ç¨®ï¼*/
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| 192 | #define EXC_NO_PROGRAM 0x7
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| 193 | #define EXC_NO_FLOATING_POINT_UNAVAILABLE 0x8
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| 194 | /* ï¼APUãæã¤PowerPC405ã440ã®ã¿ï¼ */
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| 195 |
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| 196 | /* 0x900ï¼Reserved */
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| 197 | /* 0xa00ï¼Reserved */
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| 198 | /* 0xb00ï¼Reserved */
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| 199 | #define EXC_NO_SYSTEM_CALL 0xc /* ã·ã¹ãã ã³ã¼ã« */
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| 200 | /* 0xd00ï¼Reserved */
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| 201 | /* 0xe00ï¼Reserved */
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| 202 | /* 0xe10-0xff0ï¼Reserved */
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| 203 | /* 0x1000ï¼Programmable Interval Timer */
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| 204 | /* 0x1010ï¼Fixed Interval Timer */
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| 205 | /* 0x1020ï¼Watchdog Timer */
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| 206 | /* 0x1030-0x10f0ï¼Reserved */
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| 207 | /* 0x1100ï¼Data TLB miss */
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| 208 | /* 0x1110-0x11f0ï¼Reserved */
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| 209 | /* 0x1200ï¼Instruction TLB miss */
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| 210 | /* 0x1210-0x1ff0ï¼Reserved */
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| 211 | /* 0x2000ï¼Debugï¼è¦å ï¼ç¨®ï¼ */
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| 212 | /* 0x2010-0x2ff0ï¼Implementation Specific */
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| 213 |
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| 214 | /*
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| 215 | * ä¾å¤ã®ç¨®å¥æ°
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| 216 | * ãå¤é¨å²è¾¼ã¿ãï¼ã¤ã¨æ°ãã
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| 217 | * ãã0çªã¯æªä½¿ç¨
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| 218 | * ãããã»ä¾å¤ãã¯ã¿ã®ãªãã»ããã¨å¯¾å¿
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| 219 | * ãããã»å¤é¨å²ãè¾¼ã¿ãï¼ã¤ã¨æ°ãã
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| 220 | * ãããã»é
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| 221 | å宣è¨ã®ããã+1ãã¦ãã
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| 222 | */
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| 223 |
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| 224 | #define TMAX_EXCNO ( 0x20 + 1 + NUM_IMPLEMENT_EXCEPTION )
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| 225 |
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| 226 |
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| 227 | /*
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| 228 | * DCRã¸ã®ã¢ã¯ã»ã¹
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| 229 | * DCR:Device Control Register
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| 230 | * 以ä¸ã®ã«ã¼ãã³ã¯ããã¤ã¹ãã©ã¤ãåãã«ä½æãã¦ããã
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| 231 | * DCRã®å
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| 232 | ·ä½çãªå称ãæ©è½ã¯ããã¤ã¹ä¾åã§ããã
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| 233 | *
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| 234 | * åè
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| 235 | * ãmfdcr,mtdcrå½ä»¤ã¯DCRã®çªå·ãæ±ç¨ã¬ã¸ã¹ã¿ã§ã¯ãªãã
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| 236 | * ãå³å¤ã§æå®ãããããã¤ã³ã©ã¤ã³é¢æ°ã«ã§ããªãã
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| 237 | */
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| 238 |
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| 239 | /*
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| 240 | * DCRã®ç¾å¨å¤ã®èªåºã
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| 241 | * reg:ã¬ã¸ã¹ã¿çªå·ï¼æ´æ°å®æ°ï¼
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| 242 | * val:èªã¿åºããå¤ãæ ¼ç´ããå¤æ°ï¼UWåï¼
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| 243 | */
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| 244 | #define _sil_rew_dcr(reg, val) Asm("mfdcr %0," #reg : "=r"(val))
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| 245 | #define sil_rew_dcr(reg, val) _sil_rew_dcr(reg, val)
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| 246 |
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| 247 | /*
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| 248 | * DCRã®ç¾å¨å¤ã®å¤æ´
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| 249 | * reg:ã¬ã¸ã¹ã¿çªå·ï¼æ´æ°å®æ°ï¼
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| 250 | * val:è¨å®ããå¤ãæ ¼ç´ãããå¤æ°ï¼UWåï¼
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| 251 | */
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| 252 | #define _sil_wrw_dcr(reg, val) Asm("mtdcr "#reg",%0" : : "r"(val) )
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| 253 | #define sil_wrw_dcr(reg, val) _sil_wrw_dcr(reg, val)
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| 254 |
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| 255 |
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| 256 | #endif /* _VEA_OEA_EMB_H_ */
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| 257 | /* end of file */
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