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mpc860_sil.h@ 363

Last change on this file since 363 was 363, checked in by ykominami, 5 years ago
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1	/*
2	* TOPPERS/JSP Kernel
3	* Toyohashi Open Platform for Embedded Real-Time Systems/
4	* Just Standard Profile Kernel
5	*
6	* Copyright (C) 2000-2004 by Embedded and Real-Time Systems Laboratory
7	* Toyohashi Univ. of Technology, JAPAN
8	* Copyright (C) 2001-2004 by Industrial Technology Institute,
9	* Miyagi Prefectural Government, JAPAN
10	*
11	* ä¸è¨èä½æ¨©è
12	ã¯ï¼ä»¥ä¸ã® (1)ã(4) ã®æ¡ä»¶ãï¼Free Software Foundation
13	* ã«ãã£ã¦å
14	¬è¡¨ããã¦ãã GNU General Public License ã® Version 2 ã«è¨
15	* è¿°ããã¦ããæ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§ã¢ï¼æ¬ã½ããã¦ã§ã¢
16	* ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹å¤ã»åé
17	å¸ï¼ä»¥ä¸ï¼
18	* å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
19	* (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
20	* æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
21	* ã¹ã³ã¼ãä¸ã«å«ã¾ãã¦ãããã¨ï¼
22	* (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
23	* ç¨ã§ããå½¢ã§åé
24	å¸ããå ´åã«ã¯ï¼åé
25	å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨
26	* è
27	ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
28	* ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
29	* (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
30	* ç¨ã§ããªãå½¢ã§åé
31	å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
32	* ã¨ï¼
33	* (a) åé
34	å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨è
35	ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
36	* ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
37	* (b) åé
38	å¸ã®å½¢æ
39	ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSããã¸ã§ã¯ãã«
40	* å ±åãããã¨ï¼
41	* (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
42	* å®³ãããï¼ä¸è¨èä½æ¨©è
43	ããã³TOPPERSããã¸ã§ã¯ããå
44	è²¬ãããã¨ï¼
45	*
46	* æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
47	ã
48	* ãã³TOPPERSããã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ãã®é©ç¨å¯è½æ§ã
49	* å«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´
50	* æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ãã®è²¬ä»»ãè² ããªãï¼
51	*
52	* @(#) $Id: mpc860_sil.h,v 1.2 2004/10/07 17:10:56 honda Exp $
53	*/
54
55	#include <sil.h>
56
57	/*
58	* MPC860å
59	èµã®å¶å¾¡ã¬ã¸ã¹ã¿ã¸ã®ã¢ã¯ã»ã¹ã»ã¦ã¼ãã£ãªãã£
60	*
61	* powerpc.hã«è¨è¿°ããã®ãã¨ã¬ã¬ã³ãã ããsil.hã¨ã®ã¤ã³ã¯ã«ã¼ãã®
62	* é çªã®é¢ä¿ã§ç¬ç«ãããã¡ã¤ã«ã¨ããã
63	* t_config.hãç´æ¥ã¤ã³ã¯ã«ã¼ãããã¨ãã«sil.hããå
64	ã«powerpc.hã
65	* ã¤ã³ã¯ã«ã¼ããããå¯è½æ§ãããã
66	*
67	* ã³ã³ãã¤ã©ã®åãã§ãã¯æ©è½ãæå¹ã«ããããããã¤ã³ã¿åã¯
68	* VB ãVH ãVW *ãç¨ãã¦ããã
69	*
70	*/
71
72	#ifndef _MPC860_SIL_H_
73	#define _MPC860_SIL_H_
74
75	#ifndef _MACRO_ONLY
76
77	/*
78	* SILã¨åçã®ã¢ã¯ã»ã¹é¢æ°ï¼åãã§ãã¯æ©è½ä»ãï¼
79	*/
80
81	#ifndef SIL_DEBUG
82
83	/*
84	* 8ãããåä½ã®èªåºãï¼æ¸è¾¼ã¿
85	*/
86	Inline VB
87	mpc860_reb_mem(VB *mem)
88	{
89	VB reg = sil_reb_mem((VP)mem);
90	return(reg);
91	}
92
93	Inline void
94	mpc860_wrb_mem(VB *mem, VB data)
95	{
96	sil_wrb_mem((VP)mem, data);
97	}
98
99	/*
100	* 16ãããåä½ã®èªåºãï¼æ¸è¾¼ã¿
101	*/
102	Inline VH
103	mpc860_reh_mem(VH *mem)
104	{
105	VH reg = sil_reh_mem((VP)mem);
106	return(reg);
107	}
108
109	Inline void
110	mpc860_wrh_mem(VH *mem, VH data)
111	{
112	sil_wrh_mem((VP)mem, data);
113	}
114
115	/*
116	* 32ãããåä½ã®èªåºãï¼æ¸è¾¼ã¿
117	*/
118	Inline VW
119	mpc860_rew_mem(VW *mem)
120	{
121	VW reg = sil_rew_mem((VP)mem);
122	return(reg);
123	}
124
125	Inline void
126	mpc860_wrw_mem(VW *mem, VW data)
127	{
128	sil_wrw_mem((VP)mem, data);
129	}
130
131
132
133	/*
134	* ãããæ¼ç®
135	*/
136
137	/*
138	* 8ãããã¬ã¸ã¹ã¿ã®ANDæ¼ç®
139	*/
140	Inline void
141	mpc860_andb_mem(VB *mem, VB data)
142	{
143	VB reg = mpc860_reb_mem((VP)mem);
144	reg &= data;
145	mpc860_wrb_mem(mem, reg);
146	}
147
148	/*
149	* 8ãããã¬ã¸ã¹ã¿ã®ORæ¼ç®
150	*/
151	Inline void
152	mpc860_orb_mem(VB *mem, VB data)
153	{
154	VB reg = mpc860_reb_mem(mem);
155	reg \|= data;
156	mpc860_wrb_mem(mem, reg);
157	}
158
159
160	/*
161	* 16ãããã¬ã¸ã¹ã¿ã®ANDæ¼ç®
162	*/
163	Inline void
164	mpc860_andh_mem(VH *mem, VH data)
165	{
166	VH reg = mpc860_reh_mem(mem);
167	reg &= data;
168	mpc860_wrh_mem(mem, reg);
169	}
170
171	/*
172	* 16ãããã¬ã¸ã¹ã¿ã®ORæ¼ç®
173	*/
174	Inline void
175	mpc860_orh_mem(VH *mem, VH data)
176	{
177	VH reg = mpc860_reh_mem(mem);
178	reg \|= data;
179	mpc860_wrh_mem(mem, reg);
180	}
181
182	/*
183	* 32ãããã¬ã¸ã¹ã¿ã®ANDæ¼ç®
184	*/
185	Inline void
186	mpc860_andw_mem(VW *mem, VW data)
187	{
188	VW reg = mpc860_rew_mem(mem);
189	reg &= data;
190	mpc860_wrw_mem(mem, reg);
191	}
192
193	/*
194	* 32ãããã¬ã¸ã¹ã¿ã®ORæ¼ç®
195	*/
196	Inline void
197	mpc860_orw_mem(VW *mem, VW data)
198	{
199	VW reg = mpc860_rew_mem(mem);
200	reg \|= data;
201	mpc860_wrw_mem(mem, reg);
202	}
203
204	#else /* SIL_DEBUG */
205
206	extern UW sil_log_id;
207	extern BOOL sil_debug_on;
208
209	/*
210	* SILã®ãã°åºåãå²ãå½ã¦ããã°éè¦åº¦ã®å®ç¾©
211	*ãï¼user.txtã®ã4.4 ãã°æ
212	å ±ã®éè¦åº¦ãåç
213	§ï¼
214	*/
215	#ifndef LOG_SIL
216	#define LOG_SIL LOG_EMERG
217	#endif /* LOG_SIL */
218
219
220	/*
221	* 8ãããåä½ã®èªåºã
222	*/
223	#define mpc860_reb_mem(mem) mpc860_reb_mem_deb(#mem, mem)
224
225	Inline VB
226	mpc860_reb_mem_deb(char str, VB mem)
227	{
228	BOOL sil_debug_tmp, is_end_of_line;
229	SYSUTIM sysutim;
230	VB reg;
231	ER err;
232	SIL_PRE_LOC;
233
234	sil_debug_tmp = sil_debug_on;
235	if (sil_debug_on) {
236	SIL_LOC_INT();
237	sil_debug_on = FALSE;
238	++sil_log_id;
239	SIL_UNL_INT();
240	err = vxget_tim(&sysutim);
241	if (err != E_OK) {
242	sysutim = 0;
243	}
244	SIL_LOC_INT();
245	}
246
247	reg = sil_reb_mem((VP)mem);
248
249	if (sil_debug_tmp) {
250	sil_debug_on = TRUE;
251	SIL_UNL_INT();
252	is_end_of_line = (reg == '\n') \|\| (reg == '\r');
253	if (!is_end_of_line) {
254	syslog(LOG_SIL,
255	"%d time:%08d read VB %s(0x%08x) data=0x%02x(%c)",
256	sil_log_id, (UW)sysutim, str,
257	(UW)mem, (UW)(UB)reg, (UW)(UB)reg);
258	} else {
259	syslog(LOG_SIL,
260	"%d time:%08d read VB %s(0x%08x) data=0x%02x(%s)",
261	sil_log_id, (UW)sysutim, str,
262	(UW)mem, (UW)(UB)reg,
263	(reg == '\n') ? "\\n" : "\\r");
264	}
265	}
266
267	return(reg);
268	}
269
270
271	/*
272	* 8ãããåä½ã®æ¸ãè¾¼ã¿
273	*/
274	#define mpc860_wrb_mem(mem, data) mpc860_wrb_mem_deb(#mem, mem, data)
275
276	Inline void
277	mpc860_wrb_mem_deb(char str, VB mem, VB data)
278	{
279	BOOL sil_debug_tmp, is_end_of_line;
280	SYSUTIM sysutim;
281	ER err;
282	SIL_PRE_LOC;
283
284	sil_debug_tmp = sil_debug_on;
285	if (sil_debug_on) {
286	SIL_LOC_INT();
287	sil_debug_on = FALSE;
288	++sil_log_id;
289	SIL_UNL_INT();
290	err = vxget_tim(&sysutim);
291	if (err != E_OK) {
292	sysutim = 0;
293	}
294	SIL_LOC_INT();
295	}
296
297	sil_wrb_mem((VP)mem, data);
298
299	if (sil_debug_tmp) {
300	sil_debug_on = TRUE;
301	SIL_UNL_INT();
302	is_end_of_line = (data == '\n') \|\| (data == '\r');
303	if (!is_end_of_line) {
304	syslog(LOG_SIL,
305	"%d time:%08d write VB %s(0x%08x) data=0x%02x(%c)",
306	sil_log_id, (UW)sysutim, str,
307	(UW)mem, (UW)(UB)data, (UW)(UB)data);
308	} else {
309	syslog(LOG_SIL,
310	"%d time:%08d write VB %s(0x%08x) data=0x%02x(%s)",
311	sil_log_id, (UW)sysutim, str,
312	(UW)mem, (UW)(UB)data,
313	(data == '\n') ? "\\n" : "\\r");
314	}
315	}
316	}
317
318	/*
319	* 16ãããåä½ã®èªåºã
320	*/
321	#define mpc860_reh_mem(mem) mpc860_reh_mem_deb(#mem, mem)
322
323	Inline VH
324	mpc860_reh_mem_deb(char str, VH mem)
325	{
326	BOOL sil_debug_tmp;
327	SYSUTIM sysutim;
328	VH reg;
329	ER err;
330	SIL_PRE_LOC;
331
332	sil_debug_tmp = sil_debug_on;
333	if (sil_debug_on) {
334	SIL_LOC_INT();
335	sil_debug_on = FALSE;
336	++sil_log_id;
337	SIL_UNL_INT();
338	err = vxget_tim(&sysutim);
339	if (err != E_OK) {
340	sysutim = 0;
341	}
342	SIL_LOC_INT();
343	}
344
345	reg = sil_reh_mem((VP)mem);
346
347	if (sil_debug_tmp) {
348	sil_debug_on = TRUE;
349	SIL_UNL_INT();
350	syslog(LOG_SIL,
351	"%d time:%08d read VH %s(0x%08x) data=0x%04x",
352	sil_log_id, (UW)sysutim, str,
353	(UW)mem, (UW)(UH)reg);
354	}
355
356	return(reg);
357	}
358
359	/*
360	* 16ãããåä½ã®æ¸ãè¾¼ã¿
361	*/
362	#define mpc860_wrh_mem(mem, data) mpc860_wrh_mem_deb(#mem, mem, data)
363
364	Inline void
365	mpc860_wrh_mem_deb(char str, VH mem, VH data)
366	{
367	BOOL sil_debug_tmp;
368	SYSUTIM sysutim;
369	ER err;
370	SIL_PRE_LOC;
371
372	sil_debug_tmp = sil_debug_on;
373	if (sil_debug_on) {
374	SIL_LOC_INT();
375	sil_debug_on = FALSE;
376	++sil_log_id;
377	SIL_UNL_INT();
378	err = vxget_tim(&sysutim);
379	if (err != E_OK) {
380	sysutim = 0;
381	}
382	SIL_LOC_INT();
383	}
384
385	sil_wrh_mem((VP)mem, data);
386
387	if (sil_debug_tmp) {
388	sil_debug_on = TRUE;
389	SIL_UNL_INT();
390	syslog(LOG_SIL,
391	"%d time:%08d write VH %s(0x%08x) data=0x%04x",
392	sil_log_id, (UW)sysutim, str,
393	(UW)mem, (UW)(UH)data);
394	}
395	}
396
397
398	/*
399	* 32ãããåä½ã®èªåºã
400	*/
401	#define mpc860_rew_mem(mem) mpc860_rew_mem_deb(#mem, mem)
402
403	Inline VW
404	mpc860_rew_mem_deb(char str, VW mem)
405	{
406	BOOL sil_debug_tmp;
407	SYSUTIM sysutim;
408	VW reg;
409	ER err;
410	SIL_PRE_LOC;
411
412	sil_debug_tmp = sil_debug_on;
413	if (sil_debug_on) {
414	SIL_LOC_INT();
415	sil_debug_on = FALSE;
416	++sil_log_id;
417	SIL_UNL_INT();
418	err = vxget_tim(&sysutim);
419	if (err != E_OK) {
420	sysutim = 0;
421	}
422	SIL_LOC_INT();
423	}
424
425	reg = sil_rew_mem((VP)mem);
426
427	if (sil_debug_tmp) {
428	sil_debug_on = TRUE;
429	SIL_UNL_INT();
430	syslog(LOG_SIL,
431	"%d time:%08d read VW %s(0x%08x) data=0x%08x",
432	sil_log_id, (UW)sysutim, str,
433	(UW)mem, (UW)reg);
434	}
435
436	return(reg);
437	}
438
439
440	/*
441	* 32ãããåä½ã®æ¸ãè¾¼ã¿
442	*/
443	#define mpc860_wrw_mem(mem, data) mpc860_wrw_mem_deb(#mem, mem, data)
444
445	Inline void
446	mpc860_wrw_mem_deb(char str, VW mem, VW data)
447	{
448	BOOL sil_debug_tmp;
449	SYSUTIM sysutim;
450	ER err;
451	SIL_PRE_LOC;
452
453	sil_debug_tmp = sil_debug_on;
454	if (sil_debug_on) {
455	SIL_LOC_INT();
456	sil_debug_on = FALSE;
457	++sil_log_id;
458	SIL_UNL_INT();
459	err = vxget_tim(&sysutim);
460	if (err != E_OK) {
461	sysutim = 0;
462	}
463	SIL_LOC_INT();
464	}
465
466	sil_wrw_mem((VP)mem, data);
467
468	if (sil_debug_tmp) {
469	sil_debug_on = TRUE;
470	SIL_UNL_INT();
471	syslog(LOG_SIL,
472	"%d time:%08d write VW %s(0x%08x) data=0x%08x",
473	sil_log_id, (UW)sysutim, str,
474	(UW)mem, (UW)data);
475	}
476	}
477
478
479	/*
480	* ãããæ¼ç®
481	*/
482
483	/*
484	* 8ãããã¬ã¸ã¹ã¿ã®ANDæ¼ç®
485	*/
486	#define mpc860_andb_mem(mem, data) \
487	if (sil_debug_on) { \
488	syslog(LOG_SIL, "%s & 0x%02x", \
489	#mem, (UW)(UB)data); \
490	} \
491	mpc860_andb_mem_deb(mem, data)
492
493	Inline void
494	mpc860_andb_mem_deb(VB *mem, VB data)
495	{
496	VB reg = mpc860_reb_mem((VP)mem);
497	reg &= data;
498	mpc860_wrb_mem(mem, reg);
499	}
500
501	/*
502	* 8ãããã¬ã¸ã¹ã¿ã®ORæ¼ç®
503	*/
504	#define mpc860_orb_mem(mem, data) \
505	if (sil_debug_on) { \
506	syslog(LOG_SIL, "%s \| 0x%02x", \
507	#mem, (UW)(UB)data); \
508	} \
509	mpc860_orb_mem_deb(mem, data)
510
511	Inline void
512	mpc860_orb_mem_deb(VB *mem, VB data)
513	{
514	VB reg = mpc860_reb_mem(mem);
515	reg \|= data;
516	mpc860_wrb_mem(mem, reg);
517	}
518
519
520	/*
521	* 16ãããã¬ã¸ã¹ã¿ã®ANDæ¼ç®
522	*/
523	#define mpc860_andh_mem(mem, data) \
524	if (sil_debug_on) { \
525	syslog(LOG_SIL, "%s & 0x%04x", \
526	#mem, (UW)(UH)data); \
527	} \
528	mpc860_andh_mem_deb(mem, data)
529
530	Inline void
531	mpc860_andh_mem_deb(VH *mem, VH data)
532	{
533	VH reg = mpc860_reh_mem(mem);
534	reg &= data;
535	mpc860_wrh_mem(mem, reg);
536	}
537
538	/*
539	* 16ãããã¬ã¸ã¹ã¿ã®ORæ¼ç®
540	*/
541	#define mpc860_orh_mem(mem, data) \
542	if (sil_debug_on) { \
543	syslog(LOG_SIL, "%s \| 0x%04x", \
544	#mem, (UW)(UH)data); \
545	} \
546	mpc860_orh_mem_deb(mem, data)
547
548	Inline void
549	mpc860_orh_mem_deb(VH *mem, VH data)
550	{
551	VH reg = mpc860_reh_mem(mem);
552	reg \|= data;
553	mpc860_wrh_mem(mem, reg);
554	}
555
556	/*
557	* 32ãããã¬ã¸ã¹ã¿ã®ANDæ¼ç®
558	*/
559	#define mpc860_andw_mem(mem, data) \
560	if (sil_debug_on) { \
561	syslog(LOG_SIL, "%s & 0x%08x", \
562	#mem, (UW)data); \
563	} \
564	mpc860_andw_mem_deb(mem, data)
565
566	Inline void
567	mpc860_andw_mem_deb(VW *mem, VW data)
568	{
569	VW reg = mpc860_rew_mem(mem);
570	reg &= data;
571	mpc860_wrw_mem(mem, reg);
572	}
573
574	/*
575	* 32ãããã¬ã¸ã¹ã¿ã®ORæ¼ç®
576	*/
577	#define mpc860_orw_mem(mem, data) \
578	if (sil_debug_on) { \
579	syslog(LOG_SIL, "%s \| 0x%08x", \
580	#mem, (UW)data); \
581	} \
582	mpc860_orw_mem_deb(mem, data)
583
584	Inline void
585	mpc860_orw_mem_deb(VW *mem, VW data)
586	{
587	VW reg = mpc860_rew_mem(mem);
588	reg \|= data;
589	mpc860_wrw_mem(mem, reg);
590	}
591
592
593	#endif /* SIL_DEBUG */
594
595	/*
596	* CPã³ãã³ããçºè¡å¯è½ã«ãªãã¾ã§å¾
597	ã¤
598	*/
599	Inline void
600	mpc860_wait_ready_CP_command(void)
601	{
602	UH cpcr;
603	do {
604	cpcr = mpc860_reh_mem(CPCR);
605	} while(cpcr & CPCR_FLG);
606	}
607
608
609	/*
610	* CPã³ãã³ããçºè¡ãã
611	* å¼æ°
612	* ãUW opcodeï¼ã³ãã³ãç¨®å¥
613	* ãUW ch_numï¼ãã£ãã«çªå·ï¼ããã¤ã¹çªå·ï¼
614	*/
615	Inline void
616	mpc860_CP_command(UW opcode, UW ch_num)
617	{
618	UH cpcr;
619
620	/* ä»ã®CPã³ãã³ãçµäºå¾
621	ã¡ */
622	mpc860_wait_ready_CP_command();
623
624	/* CPã³ãã³ãçºè¡ */
625	cpcr = (UH)((opcode << 8) \| (ch_num << 4) \| CPCR_FLG);
626	mpc860_wrh_mem(CPCR, cpcr);
627
628	/* CPã³ãã³ãçµäºå¾
629	ã¡ */
630	mpc860_wait_ready_CP_command();
631
632	}
633
634
635
636	#endif /* _MACRO_ONLY */
637	#endif /* _MPC860_SIL_H_ */
638	/* end of file */

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source: anotherchoice/tags/jsp-1.4.4-full-UTF8/config/powerpc32/mpc860t/mpc860_sil.h@ 363

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