1 | /*
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2 | * TOPPERS/JSP Kernel
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3 | * Toyohashi Open Platform for Embedded Real-Time Systems/
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4 | * Just Standard Profile Kernel
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5 | *
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6 | * Copyright (C) 2005 by Embedded and Real-Time Systems Laboratory
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7 | * Graduate School of Information Science, Nagoya Univ., JAPAN
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8 | *
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9 | * ä¸è¨è使¨©è
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10 | ã¯ï¼ä»¥ä¸ã® (1)ã(4) ã®æ¡ä»¶ãï¼Free Software Foundation
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11 | * ã«ãã£ã¦å
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12 | ¬è¡¨ããã¦ãã GNU General Public License ã® Version 2 ã«è¨
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13 | * è¿°ããã¦ããæ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§ã¢ï¼æ¬ã½ããã¦ã§ã¢
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14 | * ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ã使ç¨ã»è¤è£½ã»æ¹å¤ã»åé
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15 | å¸ï¼ä»¥ä¸ï¼
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16 | * å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
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17 | * (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
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18 | * 権表示ï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
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19 | * ã¹ã³ã¼ãä¸ã«å«ã¾ãã¦ãããã¨ï¼
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20 | * (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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21 | * ç¨ã§ããå½¢ã§åé
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22 | å¸ããå ´åã«ã¯ï¼åé
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23 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨
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24 | * è
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25 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è使¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
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26 | * ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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27 | * (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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28 | * ç¨ã§ããªãå½¢ã§åé
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29 | å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
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30 | * ã¨ï¼
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31 | * (a) åé
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32 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨è
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33 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
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34 | * 使¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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35 | * (b) åé
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36 | å¸ã®å½¢æ
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37 | ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSããã¸ã§ã¯ãã«
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38 | * å ±åãããã¨ï¼
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39 | * (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
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40 | * 害ãããï¼ä¸è¨è使¨©è
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41 | ããã³TOPPERSããã¸ã§ã¯ããå
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42 | 責ãããã¨ï¼
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43 | *
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44 | * æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨è使¨©è
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45 | ã
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46 | * ãã³TOPPERSããã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ãã®é©ç¨å¯è½æ§ã
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47 | * å«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´
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48 | * æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ãã®è²¬ä»»ãè² ããªãï¼
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49 | *
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50 | * @(#) $Id: nios2.h,v 1.5 2005/03/11 07:37:57 honda Exp $
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51 | */
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52 |
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53 | #ifndef _NIOSII_H_
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54 | #define _NIOSII_H_
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55 |
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56 | #ifndef _MACRO_ONLY
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57 | #include <itron.h>
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58 | #endif /* _MACRO_ONLY */
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59 |
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60 | /*
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61 | * å²è¾¼ã¿ããã
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62 | */
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63 | #define STATUS_U 0x02
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64 | #define STATUS_PIE 0x01
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65 |
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66 | /*
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67 | * å²è¾¼ã¿ã®æ°
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68 | */
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69 | #define MAX_INT_NUM 32
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70 |
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71 | /*
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72 | * ä¾å¤ã®åæ°
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73 | */
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74 | #define MAX_EXC_NUM 32
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75 |
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76 |
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77 | /*
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78 | * Timer
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79 | * Full-featuredãµãã¼ã
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80 | */
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81 |
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82 | /*
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83 | * ãªãã»ããå¤
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84 | */
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85 | #define TIM_STATUS_OFFSET 0x00
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86 | #define TIM_CONTROL_OFFSET 0x04
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87 | #define TIM_PERIODL_OFFSET 0x08
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88 | #define TIM_PERIODH_OFFSET 0x0C
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89 | #define TIM_SNAPL_OFFSET 0x10
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90 | #define TIM_SNAPH_OFFSET 0x14
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91 |
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92 | #define TIM_STATUS_RUN 0x02
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93 | #define TIM_STATUS_TO 0x01
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94 |
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95 | #define TIM_CONTROL_STOP 0x08
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96 | #define TIM_CONTROL_START 0x04
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97 | #define TIM_CONTROL_COUNT 0x02
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98 | #define TIM_CONTROL_ITO 0x01
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99 |
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100 | /*
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101 | *
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102 | */
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103 | #define TIM_STATUS (TIM_BASE + TIM_STATUS_OFFSET)
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104 | #define TIM_CONTROL (TIM_BASE + TIM_CONTROL_OFFSET)
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105 | #define TIM_PERIODL (TIM_BASE + TIM_PERIODL_OFFSET)
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106 | #define TIM_PERIODH (TIM_BASE + TIM_PERIODH_OFFSET)
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107 | #define TIM_SNAPL (TIM_BASE + TIM_SNAPL_OFFSET)
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108 | #define TIM_SNAPH (TIM_BASE + TIM_SNAPH_OFFSET)
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109 |
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110 |
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111 | /*
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112 | * UART
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113 | */
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114 | #define UART_RXDATA_OFFSET 0x00
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115 | #define UART_TXDATA_OFFSET 0x04
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116 | #define UART_STATUS_OFFSET 0x08
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117 | #define UART_CONTROL_OFFSET 0x0C
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118 | #define UART_DIVISOR_OFFSET 0x10
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119 | #define UART_ENDOFPACKET_OFFSET 0x1C
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120 |
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121 | #define UART_STATUS_EOP 0x1000
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122 | #define UART_STATUS_CTS 0x0800
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123 | #define UART_STATUS_DCTS 0x0400
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124 | #define UART_STATUS_E 0x0100
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125 | #define UART_STATUS_RRDY 0x0080
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126 | #define UART_STATUS_TRDY 0x0040
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127 | #define UART_STATUS_TMT 0x0020
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128 | #define UART_STATUS_TOE 0x0010
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129 | #define UART_STATUS_ROE 0x0008
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130 | #define UART_STATUS_BRK 0x0004
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131 | #define UART_STATUS_FE 0x0002
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132 | #define UART_STATUS_PE 0x0001
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133 |
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134 | #define UART_CONTROL_IEOP 0x1000
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135 | #define UART_CONTROL_RTS 0x0800
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136 | #define UART_CONTROL_IDCTS 0x0400
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137 | #define UART_CONTROL_TRDK 0x0200
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138 | #define UART_CONTROL_IE 0x0100
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139 | #define UART_CONTROL_IRRDY 0x0080
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140 | #define UART_CONTROL_ITRD 0x0040
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141 | #define UART_CONTROL_ITMT 0x0020
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142 | #define UART_CONTROL_ITOE 0x0010
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143 | #define UART_CONTROL_IROE 0x0008
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144 | #define UART_CONTROL_IBRK 0x0004
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145 | #define UART_CONTROL_IFE 0x0002
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146 | #define UART_CONTROL_IPE 0x0001
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147 |
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148 | #define UART_RXDATA (UART_BASE + UART_RXDATA_OFFSET)
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149 | #define UART_TXDATA (UART_BASE + UART_TXDATA_OFFSET)
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150 | #define UART_STATUS (UART_BASE + UART_STATUS_OFFSET)
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151 | #define UART_CONTROL (UART_BASE + UART_CONTROL_OFFSET)
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152 | #define UART_DIVISOR (UART_BASE + UART_DIVISOR_OFFSET)
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153 | #define UART_ENDOFPACKET (UART_BASE + UART_ENDOFPACKET_OFFSET)
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154 |
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155 |
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156 | /*
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157 | * JTAG UARTé¢é£
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158 | */
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159 | #define JTAG_UART_DATA_OFFSET 0x00
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160 | #define JTAG_UART_CONTROL_OFFSET 0x04
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161 |
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162 | #define JTAG_UART_DATA_RVALID 0x8000
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163 |
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164 | #define JTAG_UART_CONTROL_RIE 0x01
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165 | #define JTAG_UART_CONTROL_WIE 0x02
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166 | #define JTAG_UART_CONTROL_RIP 0x04
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167 | #define JTAG_UART_CONTROL_WIP 0x08
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168 | #define JTAG_UART_CONTROL_WSAPCE 0x0ffff0000
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169 |
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170 | #define JTAG_UART_DATA (UART_BASE + JTAG_UART_DATA_OFFSET)
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171 | #define JTAG_UART_CONTROL (UART_BASE + JTAG_UART_CONTROL_OFFSET)
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172 |
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173 |
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174 | #ifndef _MACRO_ONLY
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175 |
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176 | /*
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177 | * å
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178 | èµUARTç¨ ç°¡æSIOãã©ã¤ã
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179 | */
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180 |
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181 | /*
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182 | * ã·ãªã¢ã«I/Oãã¼ãåæåãããã¯
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183 | */
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184 | typedef struct sio_port_initialization_block {
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185 |
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186 | } SIOPINIB;
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187 |
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188 | /*
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189 | * ã·ãªã¢ã«I/Oãã¼ã管çãããã¯
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190 | */
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191 | typedef struct sio_port_control_block {
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192 | const SIOPINIB *siopinib; /* ã·ãªã¢ã«I/Oãã¼ãåæåããã㯠*/
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193 | VP_INT exinf; /* æ¡å¼µæ
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194 | å ± */
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195 | BOOL openflag; /* ãªã¼ãã³æ¸ã¿ãã©ã° */
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196 | BOOL sendflag; /* éä¿¡å²è¾¼ã¿ã¤ãã¼ãã«ãã©ã° */
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197 | BOOL getready; /* æåãåä¿¡ããç¶æ
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198 | */
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199 | BOOL putready; /* æåãéä¿¡ã§ããç¶æ
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200 | */
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201 | } SIOPCB;
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202 |
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203 | extern SIOPCB siopcb_table[];
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204 |
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205 | #define uart_openflag (siopcb_table[0].openflag)
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206 |
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207 | Inline void
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208 | uart_putc(unsigned char c){
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209 | #ifndef USE_JTAG_UART
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210 | while(!(sil_rew_mem((VP)UART_STATUS) & UART_STATUS_TRDY));
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211 | sil_wrw_mem((VP)UART_TXDATA, c);
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212 | #else
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213 | while(!((sil_rew_mem((VP)JTAG_UART_CONTROL) & JTAG_UART_CONTROL_WSAPCE) > 0));
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214 | sil_wrw_mem((VP)JTAG_UART_DATA, c);
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215 | #endif /* USE_JTAG_UART */
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216 | }
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217 |
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218 | Inline unsigned char
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219 | uart_getc(void){
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220 | #ifndef USE_JTAG_UART
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221 | while(!(sil_rew_mem((VP)UART_STATUS) & UART_STATUS_RRDY));
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222 | return (char)(sil_rew_mem((VP)UART_RXDATA));
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223 | #else
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224 | int tmp;
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225 | do{
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226 | tmp = sil_rew_mem((VP)JTAG_UART_DATA);
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227 | }while((tmp &JTAG_UART_DATA_RVALID) == 0);
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228 |
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229 | return (char)tmp;
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230 | #endif /* USE_JTAG_UART */
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231 | }
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232 |
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233 | /*
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234 | * ã³ã¼ã«ããã¯ã«ã¼ãã³ã®èå¥çªå·
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235 | * OPB_UARTLITE ã¯ï¼éåä¿¡å²è¾¼ã¿ãåããã¦ããªãããï¼æå³ã¯ãªãï¼
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236 | */
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237 | #define SIO_ERDY_SND 1u /* éä¿¡å¯è½ã³ã¼ã«ãã㯠*/
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238 | #define SIO_ERDY_RCV 2u /* åä¿¡éç¥ã³ã¼ã«ãã㯠*/
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239 |
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240 |
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241 | /*
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242 | * SIOãã©ã¤ãã®åæåã«ã¼ãã³
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243 | */
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244 | extern void uart_initialize(void);
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245 |
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246 |
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247 | /*
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248 | * ã·ãªã¢ã«I/Oãã¼ãã®ãªã¼ãã³
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249 | */
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250 | extern SIOPCB *uart_opn_por(ID siopid, VP_INT exinf);
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251 |
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252 | /*
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253 | * ã·ãªã¢ã«I/Oãã¼ãã®ã¯ãã¼ãº
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254 | */
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255 | extern void uart_cls_por(SIOPCB *siopcb);
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256 |
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257 | /*
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258 | * ã·ãªã¢ã«I/Oãã¼ãã¸ã®æåéä¿¡
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259 | */
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260 | extern BOOL uart_snd_chr(SIOPCB *siopcb, INT chr);
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261 |
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262 | /*
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263 | * ã·ãªã¢ã«I/Oãã¼ãããã®æååä¿¡
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264 | */
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265 | extern INT uart_rcv_chr(SIOPCB *siopcb);
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266 |
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267 |
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268 | /*
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269 | * ã·ãªã¢ã«I/Oãã¼ãããã®ã³ã¼ã«ããã¯ã®è¨±å¯
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270 | */
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271 | extern void uart_ena_cbr(SIOPCB *siopcb, UINT cbrtn);
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272 |
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273 |
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274 | /*
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275 | * ã·ãªã¢ã«I/Oãã¼ãããã®ã³ã¼ã«ããã¯ã®ç¦æ¢
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276 | */
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277 | extern void uart_dis_cbr(SIOPCB *siopcb, UINT cbrtn);
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278 |
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279 |
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280 | /*
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281 | * SIOã®å²è¾¼ã¿ãµã¼ãã¹ã«ã¼ãã³
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282 | */
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283 | extern void uart_isr(void);
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284 |
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285 |
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286 | /*
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287 | * ã·ãªã¢ã«I/Oãã¼ãããã®éä¿¡å¯è½ã³ã¼ã«ããã¯
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288 | */
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289 | extern void uart_ierdy_snd(VP_INT exinf);
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290 |
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291 |
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292 | /*
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293 | * ã·ãªã¢ã«I/Oãã¼ãããã®åä¿¡éç¥ã³ã¼ã«ããã¯
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294 | */
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295 | extern void uart_ierdy_rcv(VP_INT exinf);
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296 |
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297 | #endif /* _MACRO_ONLY */
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298 |
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299 | #endif /* _NIOSII_H_ */
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300 |
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