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sys_support.S@ 26

Last change on this file since 26 was 26, checked in by ykominami, 12 years ago
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File size: 11.0 KB

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1	/*
2	* TOPPERS/JSP Kernel
3	* Toyohashi Open Platform for Embedded Real-Time Systems/
4	* Just Standard Profile Kernel
5	*
6	* Copyright (C) 2000-2003 by Embedded and Real-Time Systems Laboratory
7	* Toyohashi Univ. of Technology, JAPAN
8	* Copyright (C) 2000-2003 by Industrial Technology Institute,
9	* Miyagi Prefectural Government, JAPAN
10	*
11	* ä¸è¨èä½æ¨©è
12	ã¯ï¼ä»¥ä¸ã® (1)ã(4) ã®æ¡ä»¶ãï¼Free Software Foundation
13	* ã«ãã£ã¦å
14	¬è¡¨ããã¦ãã GNU General Public License ã® Version 2 ã«è¨
15	* è¿°ããã¦ããæ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§ã¢ï¼æ¬ã½ããã¦ã§ã¢
16	* ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹å¤ã»åé
17	å¸ï¼ä»¥ä¸ï¼
18	* å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
19	* (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
20	* æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
21	* ã¹ã³ã¼ãä¸ã«å«ã¾ãã¦ãããã¨ï¼
22	* (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
23	* ç¨ã§ããå½¢ã§åé
24	å¸ããå ´åã«ã¯ï¼åé
25	å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨
26	* è
27	ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
28	* ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
29	* (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
30	* ç¨ã§ããªãå½¢ã§åé
31	å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
32	* ã¨ï¼
33	* (a) åé
34	å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨è
35	ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
36	* ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
37	* (b) åé
38	å¸ã®å½¢æ
39	ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSããã¸ã§ã¯ãã«
40	* å ±åãããã¨ï¼
41	* (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
42	* å®³ãããï¼ä¸è¨èä½æ¨©è
43	ããã³TOPPERSããã¸ã§ã¯ããå
44	è²¬ãããã¨ï¼
45	*
46	* æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
47	ã
48	* ãã³TOPPERSããã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ãã®é©ç¨å¯è½æ§ã
49	* å«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´
50	* æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ãã®è²¬ä»»ãè² ããªãï¼
51	*/
52
53	#define _MACRO_ONLY
54
55	#include "jsp_kernel.h"
56	#include "offset.h" /* INT_TABLE_intmaskã®ããã«å¿
57	è¦ */
58
59	.set noreorder
60	.align 2
61
62	/*
63	* ã¿ã¼ã²ãããã¼ãã¦ã§ã¢ä¾åããåæåå¦ç
64	*/
65	#ifndef GDB_STUB
66
67	.section .reset
68	.global hardware_init_hook
69
70	hardware_init_hook:
71
72	/*
73	* ãã£ãã·ã¥ã®åæå
74	*/
75	mtc0 zero, TagLo
76	mtc0 zero, TagHi
77
78	li t0, 0x80003fe0
79	li t1, 0x80000000
80	loop_I_cache_clear:
81	cache Index_Store_Tag_I, +0(t0)
82	cache Index_Store_Tag_I, +1(t0)
83	bne t0, t1, loop_I_cache_clear
84	addiu t0, t0, -I_CACHE_LINE_SIZE
85
86	li t0, 0x80003fe0
87	li t1, 0x80000000
88	loop_D_cache_clear:
89	cache Index_Store_Tag_D, +0(t0)
90	cache Index_Store_Tag_D, +1(t0)
91	bne t0, t1, loop_D_cache_clear
92	addiu t0, t0, -D_CACHE_LINE_SIZE
93
94	/*
95	* TLBã®åæå
96	*/
97	mtc0 zero, PageMask
98	mtc0 zero, EntryLo0
99	mtc0 zero, EntryLo1
100
101	li t0, TMAX_TLB
102	li t1, 0xA8000000 /* kseg1 ã®ä¸ã®DRAMã®æãä½¿ç¨ */
103	loop_TLB_clear:
104	mtc0 t0, Index
105	mtc0 t1, EntryHi
106	addiu t0, t0, -1
107	addiu t1, t1, TLB_VPN2 /* 1ãã¼ã¸ã4kãã¤ãã§ã2ãã¼ã¸åã
108	ãããã³ã°ãããã */
109	tlbwi
110	bgez t0, loop_TLB_clear
111	nop
112
113	/*
114	* ãã¼ãã®åæå
115	*/
116
117	/* SDRAM ã³ã³ããã¼ã©ã®åæå */
118	li t0, 0x00
119	sb t0, 0xb8006000 /* SRAMC_SWAIT */
120
121	li t0, 0x02
122	sb t0, 0xb8005000 /* DRAMC_RCD */
123	li t0, 0x02
124	sb t0, 0xb8005010 /* DRAMC_RP */
125	li t0, 0x05
126	sb t0, 0xb8005020 /* DRAMC_RC */
127	li t0, 0x06
128	sb t0, 0xb8005030 /* DRAMC_RRC */
129	li t0, 0x04
130	sb t0, 0xb8005040 /* DRAMC_RAS */
131	li t0, 0x02
132	sb t0, 0xb8005050 /* DRAMC_LAT */
133	li t0, 0x02
134	sb t0, 0xb8005060 /* DRAMC_RSC */
135	li t0, 0x01
136	sb t0, 0xb8005070 /* DRAMC_AP */
137
138	li t0, 0x00
139	sb t0, 0xb8004000 /* DRAM_INIT */
140
141	/* DRAMãªãã¬ãã·ã¥ç¨ã¿ã¤ãã®åæå */
142	li t0, 0xb4
143	sb t0, 0xb9005030 /* PCNTL */
144	li t0, 0x1f
145	sb t0, 0xb9005020 /* PCNT2 */
146	li t0, 0x00
147	sb t0, 0xb9005020 /* PCNT2 */
148
149	/* SRAMã®åæå */
150
151	/* SRAMã®å
152	¨é åã«å¯¾ãã¦ãä¸åº¦æ¸ãè¾¼ã¿ãè¡ãå¦çãå¿
153	è¦ */
154	la t0, 0xa0000000
155	li t1, 0x00100000-4
156	loop_sram_clear:
157	add t2, t1, t0
158	sw zero, (t2)
159	bgez t1, loop_sram_clear
160	addiu t1, t1, -4
161
162	/* å²ãè¾¼ã¿ã³ã³ããã¼ã©ã®è¨å® */
163	sb zero, 0xb9000000 /* PIC_INT0Mï¼å
164	¨å²è¾¼ã¿ã®ãã¹ã¯ */
165	sb zero, 0xb9000010 /* PIC_INT1Mï¼å
166	¨å²è¾¼ã¿ã®ãã¹ã¯ */
167	sb zero, 0xb9000020 /* PIC_INTR ï¼å²è¾¼ã¿è¦æ±ã®ã¯ãªã¢ */
168	li t0, 0x01 /* å²è¾¼ã¿ç·ã¯çæ¹ã®ã¿ä½¿ã */
169	sb t0, 0xb9000030 /* PIC_INTEN */
170
171	/----------/
172
173	j ra /* å¼ã³åºãå
174	ã¸ãªã¿ã¼ã³ */
175	nop
176
177	#endif /* GDB_STUB */
178
179	/============================================================================/
180
181	/* å²è¾¼ã¿å¦çã«é¢ãããå²è¾¼ã¿è¦å ã®å¤æåå²å¦çã®ã·ã¹ãã ä¾åé¨ */
182
183	.align 2
184	.section .text
185	.global proc_interrupt_sys
186	.global int_table /* å²è¾¼ã¿ãã³ãã©ã®æ¬ä¼¼ãã¯ã¿ãã¼ãã«
187	cpu_config.h, cpu_config.cã§å®ç¾© */
188
189	/* å¼ã³åºãããã¨ãã */
190	/* a1ã«ã¹ãã¼ã¿ã¹ã¬ã¸ã¹ã¿ */
191	/* a2ã«åå ã¬ã¸ã¹ã¿ */
192	/* ã®å¤ãå
193	¥ã£ã¦ãã */
194
195	proc_interrupt_sys:
196	and t2, a2, a1 /* å²è¾¼ã¿è¦æ±ãããã«ãã¹ã¯ãããã */
197	andi t3, t2, Cause_IP0 /* IP0ãããåãåºã */
198	bne t3, zero, proc_IP0
199	andi t4, t2, Cause_IP1 /* IP1ãããåãåºã */
200	bne t4, zero, proc_IP1
201	andi t5, t2, Cause_IP2 /* IP2ãããåãåºã */
202	bne t5, zero, proc_IP2
203	andi t6, t2, Cause_IP3 /* IP3ãããåãåºã */
204	bne t6, zero, proc_IP3
205	andi t7, t2, Cause_IP4 /* IP4ãããåãåºã */
206	bne t7, zero, proc_IP4
207	andi t8, t2, Cause_IP5 /* IP5ãããåãåºã */
208	bne t8, zero, proc_IP5
209	andi t9, t2, Cause_IP6 /* IP6ãããåãåºã */
210	bne t9, zero, proc_IP6
211	nop
212
213	/* ãªãããã®åå ã§åå²ã§ããªãå ´å */
214	j join_interrupt_and_exception
215	nop
216
217	/* MIPS3ã³ã¢ã¬ãã«ã§åå²ããã¬ãã«ã§ã®å¦ç */
218	/* å²è¾¼ã¿è¦å çªå·ãt0ã«å
219	¥ãã¦ */
220	/* å²è¾¼ã¿è¦æ±ã¯ãªã¢ã®ããã®å®æ°ãt1ã«å
221	¥ãã¦ */
222	/* set_ICU_IPMã¸é£ã¶ */
223	proc_IP7: /* å²è¾¼ã¿è¦å IP7ï¼ã¿ã¤ãï¼ã®å ´å */
224	xori t1, zero, Cause_IP7
225	j set_ICU_IPM
226	ori t0, zero, INTNO_IP7
227
228	proc_IP0: /* å²è¾¼ã¿è¦å IP0ï¼ã½ããã¦ã§ã¢å²è¾¼ã¿0ï¼ã®å ´å */
229	xori t1, zero, Cause_IP0
230	j set_ICU_IPM
231	ori t0, zero, INTNO_IP0
232
233	proc_IP1: /* å²è¾¼ã¿è¦å IP1ï¼ã½ããã¦ã§ã¢å²è¾¼ã¿1ï¼ã®å ´å */
234	xori t1, zero, Cause_IP1
235	j set_ICU_IPM
236	ori t0, zero, INTNO_IP1
237
238	proc_IP2: /* å²è¾¼ã¿è¦å IP2ã®å ´å */
239	/* å²è¾¼ã¿ã³ã³ããã¼ã©ä¾åã®å®ç¾©ãããã°ããã¡ããå®è¡ãã */
240	#ifdef PROC_INT0
241	PROC_INT0 /* ã·ã¹ãã ä¾åé¨ã§å®ç¾©ãããã¯ã */
242	xori t1, zero, Cause_IP2
243	j set_ICU_IPM
244	nop
245	#else /* PROC_INT0 */
246	xori t1, zero, Cause_IP2
247	j set_ICU_IPM
248	ori t0, zero, INTNO_IP2
249	#endif /* PROC_INT0 */
250
251	proc_IP3: /* å²è¾¼ã¿è¦å IP3ã®å ´å */
252	/* å²è¾¼ã¿ã³ã³ããã¼ã©ä¾åã®å®ç¾©ãããã°ããã¡ããå®è¡ãã */
253	#ifdef PROC_INT1
254	PROC_INT1 /* ã·ã¹ãã ä¾åé¨ã§å®ç¾©ãããã¯ã */
255	xori t1, zero, Cause_IP3
256	j set_ICU_IPM
257	nop
258	#else /* PROC_INT1 */
259	xori t1, zero, Cause_IP3
260	j set_ICU_IPM
261	ori t0, zero, INTNO_IP3
262	#endif /* PROC_INT1 */
263
264	proc_IP4: /* å²è¾¼ã¿è¦å IP4ã®å ´å */
265	/* å²è¾¼ã¿ã³ã³ããã¼ã©ä¾åã®å®ç¾©ãããã°ããã¡ããå®è¡ãã */
266	#ifdef PROC_INT2
267	PROC_INT2 /* ã·ã¹ãã ä¾åé¨ã§å®ç¾©ãããã¯ã */
268	xori t1, zero, Cause_IP4
269	j set_ICU_IPM
270	nop
271	#else /* PROC_INT2 */
272	xori t1, zero, Cause_IP4
273	j set_ICU_IPM
274	ori t0, zero, INTNO_IP4
275	#endif /* PROC_INT2 */
276
277	proc_IP5: /* å²è¾¼ã¿è¦å IP5ã®å ´å */
278	/* å²è¾¼ã¿ã³ã³ããã¼ã©ä¾åã®å®ç¾©ãããã°ããã¡ããå®è¡ãã */
279	#ifdef PROC_INT3
280	PROC_INT3 /* ã·ã¹ãã ä¾åé¨ã§å®ç¾©ãããã¯ã */
281	xori t1, zero, Cause_IP5
282	j set_ICU_IPM
283	nop
284	#else /* PROC_INT3 */
285	xori t1, zero, Cause_IP5
286	j set_ICU_IPM
287	ori t0, zero, INTNO_IP5
288	#endif /* PROC_INT3 */
289
290	proc_IP6: /* å²è¾¼ã¿è¦å IP6ã®å ´å */
291	/* å²è¾¼ã¿ã³ã³ããã¼ã©ä¾åã®å®ç¾©ãããã°ããã¡ããå®è¡ãã */
292	#ifdef PROC_INT4
293	PROC_INT4 /* ã·ã¹ãã ä¾åé¨ã§å®ç¾©ãããã¯ã */
294	xori t1, zero, Cause_IP6
295	#else /* PROC_INT4 */
296	xori t1, zero, Cause_IP6
297	ori t0, zero, INTNO_IP6
298	#endif /* PROC_INT4 */
299
300	/* å²è¾¼ã¿ã³ã³ããã¼ã©ä¾åã®ãã¹ã¯è¨å® */
301	set_ICU_IPM:
302
303	#ifdef SET_ICU_IPM
304	SET_ICU_IPM /* å²è¾¼ã¿ãã¹ã¯ãè¨å®ãããã¯ã */
305	/* å®è£
306	ãè¡ãã¨ãã«ã¯ãä¸è¨ã«ã¦t0ãt1ã¯å©ç¨ããã® */
307	/* ã§ç ´å£ããªãããã«ãæ³¨æããªããã°ãªããªãã */
308	#endif /* SET_ICU_IPM */
309
310	/*
311	* åå ã¬ã¸ã¹ã¿IPãããã«ä¿æããã¦ããåç¨®å²è¾¼ã¿ã®å²è¾¼ã¿è¦æ±ãã¯ãªã¢ããã
312	* t1ã«ã¯ãå²è¾¼ã¿è¦æ±ããããåè»¢ãããã®ãå
313	¥ã£ã¦ããã
314	*/
315	mfc0 t8, Cause
316	and t8, t8, t1
317	mtc0 t8, Cause
318
319	/* ã¹ãã¼ã¿ã¹ã¬ã¸ã¹ã¿ã®ãã¹ã¯è¨å®ã¨Cè¨èªã«ã¼ãã³å¼ã³åºã */
320	/* t0ã«å²è¾¼ã¿è¦å çªå·ãè¨å®ãããç¶æ
321	ã§ããã«æ¥ã */
322	la t3, int_table /* æ¬ä¼¼ãã¯ã¿ã¢ãã¬ã¹ */
323	sll t4, t0, 3 /* å²è¾¼ã¿è¦å çªå·ã8å
324	TNT_TABLEåã¯ã
325	ãã³ãã©ã®ã¢ãã¬ã¹(4ãã¤ã)
326	ï¼MIPS3ã³ã¢ã®å²è¾¼ã¿ãã¹ã¯(4ãã¤ã)
327	ã®ãåè¨8ãã¤ãã */
328	add t5, t3, t4 /* ãã¯ã¿ã¢ãã¬ã¹ãç®åº */
329	lw t6, INT_TABLE_intmask(t5)
330	/* IPM(å²è¾¼ã¿è¨±å¯ããã)èªã¿åºãã
331	å²è¾¼ã¿ãã¹ã¯ä»¥å¤ã®å¤ã¯ã
332	IEãããã¯ã»ãã
333	EXLãããã¯ãªã»ãã
334	ç¶æ
335	ã«ãªã£ã¦ããã*/
336	lw t7, (t5) /* Cè¨èªã«ã¼ãã³å
337	é ã¢ãã¬ã¹èªã¿åºã */
338
339	jalr ra, t7 /* Cè¨èªã«ã¼ãã³å¼ã³åºã */
340	mtc0 t6, Status /* å²è¾¼ã¿è¨±å¯ï¼ã¹ãã¼ã¿ã¹ã¬ã¸ã¹ã¿ã®ãã¹ã¯è¨å®*/
341
342	mfc0 t0, Status
343	ori t0, t0, SR_EXL /* å²è¾¼ã¿ç¦æ¢ï¼IEãããã®å¤ã¯ä¿æããªããã°ãªã
344	ãªãã®ã§EXLããããç¨ããã*/
345	mtc0 t0, Status
346
347	/* CP0ãã¶ã¼ãã®ããã®æéç¨¼ã */
348	#ifdef NOP_FOR_CP0_HAZARD
349	NOP_FOR_CP0_HAZARD
350	#endif /* NOP_FOR_CP0_HAZARD */
351
352	j join_interrupt_and_exception
353	nop
354

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