[363] | 1 | /*
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| 2 | * TOPPERS/JSP Kernel
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| 3 | * Toyohashi Open Platform for Embedded Real-Time Systems/
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| 4 | * Just Standard Profile Kernel
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| 5 | *
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| 6 | * Copyright (C) 2000-2003 by Embedded and Real-Time Systems Laboratory
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| 7 | * Toyohashi Univ. of Technology, JAPAN
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| 8 | * Copyright (C) 2000-2003 by Industrial Technology Institute,
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| 9 | * Miyagi Prefectural Government, JAPAN
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| 10 | *
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| 11 | * ä¸è¨èä½æ¨©è
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| 12 | ã¯ï¼ä»¥ä¸ã® (1)ã(4) ã®æ¡ä»¶ãï¼Free Software Foundation
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| 13 | * ã«ãã£ã¦å
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| 14 | ¬è¡¨ããã¦ãã GNU General Public License ã® Version 2 ã«è¨
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| 15 | * è¿°ããã¦ããæ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§ã¢ï¼æ¬ã½ããã¦ã§ã¢
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| 16 | * ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ã使ç¨ã»è¤è£½ã»æ¹å¤ã»åé
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| 17 | å¸ï¼ä»¥ä¸ï¼
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| 18 | * å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
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| 19 | * (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
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| 20 | * 権表示ï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
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| 21 | * ã¹ã³ã¼ãä¸ã«å«ã¾ãã¦ãããã¨ï¼
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| 22 | * (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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| 23 | * ç¨ã§ããå½¢ã§åé
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| 24 | å¸ããå ´åã«ã¯ï¼åé
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| 25 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨
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| 26 | * è
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| 27 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
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| 28 | * ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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| 29 | * (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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| 30 | * ç¨ã§ããªãå½¢ã§åé
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| 31 | å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
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| 32 | * ã¨ï¼
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| 33 | * (a) åé
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| 34 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨è
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| 35 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
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| 36 | * ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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| 37 | * (b) åé
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| 38 | å¸ã®å½¢æ
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| 39 | ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSããã¸ã§ã¯ãã«
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| 40 | * å ±åãããã¨ï¼
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| 41 | * (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
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| 42 | * 害ãããï¼ä¸è¨èä½æ¨©è
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| 43 | ããã³TOPPERSããã¸ã§ã¯ããå
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| 44 | 責ãããã¨ï¼
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| 45 | *
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| 46 | * æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
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| 47 | ã
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| 48 | * ãã³TOPPERSããã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ãã®é©ç¨å¯è½æ§ã
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| 49 | * å«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´
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| 50 | * æ¥çã¾ãã¯éæ¥çã«çãããããªãæ害ã«é¢ãã¦ãï¼ãã®è²¬ä»»ãè² ããªãï¼
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| 51 | */
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| 52 |
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| 53 | #ifndef _PIC_ICU_H_
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| 54 | #define _PIC_ICU_H_
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| 55 |
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| 56 | #ifndef _MACRO_ONLY
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| 57 | #include <sil.h>
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| 58 | #endif /* _MACRO_ONLY */
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| 59 |
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| 60 | #include <rte_vr5500_cb.h> /* ICU_BASE_ADDR */
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| 61 |
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| 62 | /*
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| 63 | * å²è¾¼ã¿ã³ã³ããã¼ã©(Programable Interrupt Controler)é¢ä¿ã®å®ç¾©
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| 64 | */
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| 65 |
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| 66 | /* å²è¾¼ã¿çªå·ã®å®ç¾©ï¼0-7ã¯mips3.hã§ä½¿ç¨ã8以éãæå®ãããï¼ */
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| 67 | #define INTNO_TIMER0 8 /* ã¿ã¤ãï¼ */
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| 68 | #define INTNO_SERIAL0 9 /* ã·ãªã¢ã«ï¼ */
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| 69 | #define INTNO_GBUS 10 /* GBUS-INT0- */
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| 70 | #define INTNO_BUS_ERR 11 /* BUS_ERROR */
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| 71 | #define INTNO_TIMER1 12 /* ã¿ã¤ãï¼ */
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| 72 | #define INTNO_SERIAL1 13 /* ã·ãªã¢ã«ï¼ */
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| 73 | #define INTNO_PARALEL 14 /* ãã©ã¬ã« */
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| 74 | #define INTNO_DMAC 15 /* DMAC_INTREQ- */
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| 75 |
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| 76 | /* å²è¾¼ã¿ã³ã³ããã¼ã©ã管çããå²è¾¼ã¿ã®æ¬æ° */
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| 77 | #define TMAX_ICU_INTNO 8u
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| 78 |
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| 79 | /* å²è¾¼ã¿ã³ã³ããã¼ã©ã®ã¬ã¸ã¹ã¿ã®ã¢ãã¬ã¹å®ç¾© */
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| 80 | /* 以ä¸ã®xxx_offsetã¯ãã¢ã»ã³ãã©ã§ä½¿ãã */
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| 81 | #define INT0M_offset 0x00
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| 82 | #define INT1M_offset 0x10
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| 83 | #define INTR_offset 0x20
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| 84 | #define INTEN_offset 0x30
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| 85 |
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| 86 | #define ICU_INT0M INT0M_offset
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| 87 | #define ICU_INT1M INT1M_offset
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| 88 | #define ICU_INTR INTR_offset
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| 89 | #define ICU_INTEN INTEN_offset
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| 90 |
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| 91 | /* å²è¾¼ã¿è¦å ããããã¿ã¼ã³ (ä¸è¨ãã¢ã»ã³ãã©é¨åã§ãå©ç¨ãã¦ããã) */
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| 92 | #define TIMER0 BIT0
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| 93 | #define SERIAL0 BIT1
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| 94 | #define GBUS BIT2
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| 95 | #define BUS_ERR BIT3
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| 96 | #define TIMER1 BIT4
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| 97 | #define SERIAL1 BIT5
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| 98 | #define PARALEL BIT6
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| 99 | #define DMAC BIT7
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| 100 |
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| 101 | /* ICUå
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| 102 | ã®ã¬ã¸ã¹ã¿ã¢ã¯ã»ã¹ç¨ã®é¢æ° */
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| 103 | #define icu_reb( addr ) sil_reb_mem( (VP)(ICU_BASE_ADDR + addr) )
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| 104 | #define icu_wrb( addr, val ) sil_wrb_mem( (VP)(ICU_BASE_ADDR + addr), val )
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| 105 |
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| 106 | #define icu_orb( mem, val ) icu_wrb( mem, icu_reb( mem ) | val )
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| 107 | #define icu_andb( mem, val ) icu_wrb( mem, icu_reb( mem ) & val )
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| 108 |
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| 109 | /*
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| 110 | * å²è¾¼ã¿ã³ã³ããã¼ã©ã®å²è¾¼ã¿ãã¹ã¯é¢ä¿
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| 111 | */
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| 112 |
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| 113 | /* æ§é ä½ICU_IPMå
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| 114 | ã®ãªãã»ãããæ±ããããã®ãã¯ãï¼makeoffset.cã§ç¨ããï¼
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| 115 | ãªãããã®ãã¯ãã§å®ç¾©ããå¤ã¯ãç¹ã«å©ç¨ãã¦ããªãã*/
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| 116 | #define OFFSET_DEF_ICU_IPM OFFSET_DEF(ICU_IPM, int1m)
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| 117 |
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| 118 | /* å²è¾¼ã¿ã³ã³ããã¼ã©ã«è¨å®å¯è½ãªå²è¾¼ã¿ãã¹ã¯ããããã¿ã¼ã³ï¼æé«å¤ï¼*/
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| 119 | #define MAX_ICU_IPM 0xff
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| 120 |
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| 121 | /* å²è¾¼ã¿ã³ã³ããã¼ã©ã«è¨å®ããå²è¾¼ã¿ãã¹ã¯ã®ãã§ã㯠*/
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| 122 | #define CHECK_ICU_IPM(ipm) \
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| 123 | CHECK_PAR( 0 < (ipm.int0m) && (ipm.int0m) <= MAX_ICU_IPM ); \
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| 124 | CHECK_PAR( 0 < (ipm.int1m) && (ipm.int1m) <= MAX_ICU_IPM )
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| 125 |
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| 126 | #ifndef _MACRO_ONLY
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| 127 |
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| 128 | /* å²è¾¼ã¿ã³ã³ããã¼ã©ã«å¯¾ããå²è¾¼ã¿ãã¹ã¯ã®æ¬ä¼¼ãã¼ãã« */
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| 129 | extern ICU_IPM icu_intmask_table[];
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| 130 |
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| 131 | /* å²è¾¼ã¿ã³ã³ããã¼ã©ã®intmaskãã¼ãã«ã®è¨å® */
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| 132 | Inline void icu_set_ilv(INTNO intno, ICU_IPM *ipm) {
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| 133 | /* CHECK_ICU_IPM(ipm) ã¯ãä¸ä½ã«ã¼ãã³ã§å®è¡æ¸ã¿ */
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| 134 | icu_intmask_table[intno].int0m = ipm->int0m;
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| 135 | icu_intmask_table[intno].int1m = ipm->int1m;
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| 136 | }
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| 137 |
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| 138 | /* å²ãè¾¼ã¿ã³ã³ããã¼ã©ã®ãã¹ã¯è¨å® */
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| 139 | Inline void icu_set_ipm(ICU_IPM *ipm) {
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| 140 | /* CHECK_ICU_IPM(ipm) ã¯ãä¸ä½ã«ã¼ãã³ã§å®è¡æ¸ã¿ */
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| 141 | icu_wrb( (VP) ICU_INT0M, ipm->int0m );
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| 142 | icu_wrb( (VP) ICU_INT1M, ipm->int1m );
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| 143 | }
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| 144 |
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| 145 | /* å²ãè¾¼ã¿ã³ã³ããã¼ã©ã®ãã¹ã¯åå¾ */
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| 146 | Inline void icu_get_ipm(ICU_IPM *ipm) {
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| 147 | ipm->int0m = icu_reb( (VP) ICU_INT0M );
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| 148 | ipm->int1m = icu_reb( (VP) ICU_INT1M );
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| 149 | }
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| 150 |
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| 151 | #endif /* _MACRO_ONLY */
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| 152 |
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| 153 | /*============================================================================*/
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| 154 | /* ã¢ã»ã³ãã©å¦çé¢ä¿ */
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| 155 |
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| 156 | /* å²è¾¼ã¿è¨±å¯ãããã®å¾
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| 157 | é¿ã¨å¾©å
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| 158 | */
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| 159 | /* å²è¾¼ã¿ã³ã³ããã¼ã©ICUã®IPMãã¹ã¿ãã¯ã«ä¿å */
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| 160 | /* ã¯ã¼ãå¢çã®é¢ä¿ã§ãæ¬æ¥ã¯1ãã¤ãã®ãã¹ã¯ã§ã¯ããããã©ãã
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| 161 | ã¯ã¼ãå¢çã®ããã«2ãã¤ãåä½ã§æ±ãå¿
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| 162 | è¦ãããã */
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| 163 | #define PUSH_ICU_IPM \
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| 164 | li t1, ICU_BASE_ADDR; \
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| 165 | addi sp, sp, -2*2; \
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| 166 | lb t3, INT0M_offset(t1); /* t3 = INT0M */ \
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| 167 | lb t4, INT1M_offset(t1); /* t4 = INT1M */ \
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| 168 | sh t3, (sp); \
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| 169 | sh t4, 2(sp)
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| 170 |
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| 171 | /* å²è¾¼ã¿ã³ã³ããã¼ã©ICUã®IPMãã¹ã¿ãã¯ãã復å
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| 172 | */
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| 173 | #define POP_ICU_IPM \
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| 174 | li t1, ICU_BASE_ADDR; \
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| 175 | lh t3, (sp); \
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| 176 | lh t4, 2(sp); \
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| 177 | sb t3, INT0M_offset(t1); /* INT0M = t3 */ \
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| 178 | sb t4, INT1M_offset(t1); /* INT1M = t4 */ \
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| 179 | addi sp, sp, 2*2
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| 180 |
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| 181 | /* å²è¾¼ã¿ã³ã³ããã¼ã©ICUã®IPMãè¨å® */
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| 182 | /* t0ã«å²è¾¼ã¿è¦å çªå·ãå
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| 183 | ¥ã£ãç¶æ
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| 184 | ã§å¼ã°ãã */
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| 185 | /* t0ã®å
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| 186 | 容ãå£ãã¦ã¯ãããªã */
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| 187 | /* t1ã«å²è¾¼ã¿è¦æ±ã¯ãªã¢ã®å®æ°ãå
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| 188 | ¥ã£ã¦ããã®ã§ç ´å£ãã¦ã¯ãªããªãã */
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| 189 | #define SET_ICU_IPM \
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| 190 | la t4, icu_intmask_table; /* ãã¼ã¿ãã¼ãã«ã®å
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| 191 | é ã¢ãã¬ã¹ */ \
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| 192 | sll t2, t0, 1; /* ãªãã»ããï¼å²è¾¼ã¿è¦å çªå·Ã2å \
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| 193 | (ãã¹ã¯ã¯ã2ãã¤ã) */ \
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| 194 | li t3, ICU_BASE_ADDR; \
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| 195 | add t4, t4, t2; /* å
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| 196 | é ã¢ãã¬ã¹ï¼ãªãã»ãã */ \
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| 197 | lh t5, (t4); /* t5 = INT0M:INT1M */ \
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| 198 | /* 注æï¼ãªãã«ã¨ã³ãã£ã¢ã³ä¾å */ \
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| 199 | sb t5, INT0M_offset(t3); /* INT0M=t5ã®ä¸ä½1ãã¤ã */ \
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| 200 | srl t6, t5, 8; \
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| 201 | sb t6, INT1M_offset(t3); /* INT1M=t5ã®ä¸ä½1ãã¤ã */
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| 202 |
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| 203 | /* ããã¤ã¹åããåå¥å¦çãå±éãããã¯ã */
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| 204 | /* å²è¾¼ã¿è¦å ãt0ã«å
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| 205 | ¥ã㦠proc_END ã«é£ã¶ */
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| 206 | #define MAKE_PROC(device) \
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| 207 | proc_##device: \
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| 208 | li t0, INTNO_##device; \
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| 209 | j proc_END; \
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| 210 | nop;
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| 211 |
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| 212 | /* å²è¾¼ã¿è¦å ã®å¤å¥ */
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| 213 | /* å²è¾¼ã¿ã³ã³ããã¼ã©ã¯MIPS3ã³ã¢ã®Int0ã«æ¥ç¶ããã¦ãã */
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| 214 | /* ãã¹ã¯ã®ãã§ãã¯*/
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| 215 | #define PROC_INT0 \
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| 216 | li t2, ICU_BASE_ADDR; \
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| 217 | lb t3, INTR_offset(t2); \
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| 218 | lb t4, INT0M_offset(t2); \
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| 219 | and t5, t3, t4; /* INT0M ã¨ãã¹ã¯ */ \
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| 220 | beq t5, zero, proc_END; \
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| 221 | nop; \
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| 222 | \
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| 223 | proc_BIT0: \
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| 224 | andi t4, t3, TIMER0; \
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| 225 | beq t4, zero, proc_BIT1; \
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| 226 | nop; \
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| 227 | MAKE_PROC(TIMER0) \
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| 228 | \
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| 229 | proc_BIT1: \
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| 230 | andi t4, t3, SERIAL0; \
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| 231 | beq t4, zero, proc_BIT2; \
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| 232 | nop; \
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| 233 | MAKE_PROC(SERIAL0) \
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| 234 | \
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| 235 | proc_BIT2: \
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| 236 | andi t4, t3, GBUS; \
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| 237 | beq t4, zero, proc_BIT3; \
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| 238 | nop; \
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| 239 | MAKE_PROC(GBUS) \
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| 240 | \
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| 241 | proc_BIT3: \
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| 242 | andi t4, t3, BUS_ERR; \
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| 243 | beq t4, zero, proc_BIT4; \
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| 244 | nop; \
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| 245 | MAKE_PROC(BUS_ERR) \
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| 246 | \
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| 247 | proc_BIT4: \
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| 248 | andi t4, t3, TIMER1; \
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| 249 | beq t4, zero, proc_BIT5; \
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| 250 | nop; \
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| 251 | MAKE_PROC(TIMER1) \
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| 252 | \
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| 253 | proc_BIT5: \
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| 254 | andi t4, t3, SERIAL1; \
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| 255 | beq t4, zero, proc_BIT6; \
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| 256 | nop; \
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| 257 | MAKE_PROC(SERIAL1) \
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| 258 | \
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| 259 | proc_BIT6: \
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| 260 | andi t4, t3, PARALEL; \
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| 261 | beq t4, zero, proc_BIT7; \
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| 262 | nop; \
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| 263 | MAKE_PROC(PARALEL) \
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| 264 | \
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| 265 | proc_BIT7: \
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| 266 | andi t4, t3, DMAC; \
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| 267 | beq t4, zero, proc_END; \
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| 268 | nop; \
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| 269 | MAKE_PROC(DMAC) \
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| 270 | \
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| 271 | proc_END:
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| 272 |
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| 273 | #endif /* _PIC_ICU_H_ */
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