[363] | 1 | /*
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| 2 | * TOPPERS/JSP Kernel
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| 3 | * Toyohashi Open Platform for Embedded Real-Time Systems/
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| 4 | * Just Standard Profile Kernel
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| 5 | *
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| 6 | * Copyright (C) 2000-2003 by Embedded and Real-Time Systems Laboratory
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| 7 | * Toyohashi Univ. of Technology, JAPAN
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| 8 | * Copyright (C) 2000-2003 by Industrial Technology Institute,
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| 9 | * Miyagi Prefectural Government, JAPAN
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| 10 | *
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| 11 | * ä¸è¨èä½æ¨©è
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| 12 | ã¯ï¼ä»¥ä¸ã® (1)ã(4) ã®æ¡ä»¶ãï¼Free Software Foundation
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| 13 | * ã«ãã£ã¦å
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| 14 | ¬è¡¨ããã¦ãã GNU General Public License ã® Version 2 ã«è¨
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| 15 | * è¿°ããã¦ããæ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§ã¢ï¼æ¬ã½ããã¦ã§ã¢
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| 16 | * ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ã使ç¨ã»è¤è£½ã»æ¹å¤ã»åé
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| 17 | å¸ï¼ä»¥ä¸ï¼
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| 18 | * å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
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| 19 | * (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
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| 20 | * 権表示ï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
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| 21 | * ã¹ã³ã¼ãä¸ã«å«ã¾ãã¦ãããã¨ï¼
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| 22 | * (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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| 23 | * ç¨ã§ããå½¢ã§åé
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| 24 | å¸ããå ´åã«ã¯ï¼åé
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| 25 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨
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| 26 | * è
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| 27 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
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| 28 | * ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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| 29 | * (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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| 30 | * ç¨ã§ããªãå½¢ã§åé
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| 31 | å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
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| 32 | * ã¨ï¼
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| 33 | * (a) åé
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| 34 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨è
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| 35 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
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| 36 | * ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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| 37 | * (b) åé
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| 38 | å¸ã®å½¢æ
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| 39 | ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSããã¸ã§ã¯ãã«
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| 40 | * å ±åãããã¨ï¼
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| 41 | * (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
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| 42 | * 害ãããï¼ä¸è¨èä½æ¨©è
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| 43 | ããã³TOPPERSããã¸ã§ã¯ããå
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| 44 | 責ãããã¨ï¼
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| 45 | *
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| 46 | * æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
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| 47 | ã
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| 48 | * ãã³TOPPERSããã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ãã®é©ç¨å¯è½æ§ã
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| 49 | * å«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´
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| 50 | * æ¥çã¾ãã¯éæ¥çã«çãããããªãæ害ã«é¢ãã¦ãï¼ãã®è²¬ä»»ãè² ããªãï¼
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| 51 | */
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| 52 |
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| 53 | #define _MACRO_ONLY
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| 54 |
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| 55 | #include "jsp_kernel.h"
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| 56 |
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| 57 | .set noreorder
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| 58 | .align 2
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| 59 |
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| 60 | /*
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| 61 | * ã¿ã¼ã²ãããã¼ãã¦ã§ã¢ä¾åããåæåå¦ç (reset.S ããå¼ã³åºããã)
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| 62 | */
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| 63 | #ifndef GDB_STUB
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| 64 |
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| 65 | .section .reset
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| 66 | .global hardware_init_hook
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| 67 |
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| 68 | hardware_init_hook:
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| 69 |
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| 70 | /*
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| 71 | * ãã¹ã³ã³ããã¼ã«ã¦ããã(BCU)é¢ä¿ã®åæè¨å®
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| 72 | */
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| 73 | li t0, ASM_SIL( ROMSIZEREG )
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| 74 | lh t1, (t0)
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| 75 | ori t1, t1, (SIZE3_4 | SIZE2_4 | SIZE1_4 | SIZE0_4)
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| 76 | sh t1, (t0)
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| 77 |
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| 78 | li t0, ASM_SIL( ROMSPEEDREG )
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| 79 | lh t1, (t0)
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| 80 | ori t1, t1, (ROM4_WAIT_5VTClock | ROM2_WAIT_8VTClock)
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| 81 | sh t1, (t0)
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| 82 |
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| 83 | li t0, ASM_SIL( BCUCNTREG3 )
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| 84 | lh t1, (t0)
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| 85 | ori t1, t1, (EXT_ROMCS_3ROM_2ROM | IO32 | LCDSEL1_BUFFER | LCDSEL0_BUFFER)
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| 86 | sh t1, (t0)
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| 87 |
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| 88 | /*
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| 89 | * SDRAMã³ã³ããã¼ã«ã¦ããã(SDRAMU)é¢ä¿ã®åæè¨å®
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| 90 | */
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| 91 |
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| 92 | li t0, ASM_SIL( SDRAMMODEREG )
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| 93 | lh t1, (t0)
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| 94 | ori t1, t1, (SCLK | LTMODE_2)
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| 95 | sh t1, (t0)
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| 96 |
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| 97 | li t0, ASM_SIL( SDRAMCNTREG )
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| 98 | lh t1, (t0)
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| 99 | ori t1, t1, (TRC_3VTClock | TDAL_2VTClock | TRCD_2VTClock)
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| 100 | sh t1, (t0)
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| 101 |
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| 102 | li t0, ASM_SIL( BCURFCNTREG )
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| 103 | lh t1, (t0)
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| 104 | ori t1, t1, 0x3ec
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| 105 | sh t1, (t0)
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| 106 |
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| 107 | li t0, ASM_SIL( BCURFCNTREG )
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| 108 | lh t1, (t0)
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| 109 | ori t1, t1, 0x3ec
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| 110 | sh t1, (t0)
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| 111 |
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| 112 | li t0, ASM_SIL( RAMSIZEREG )
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| 113 | lh t1, (t0)
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| 114 | ori t1, t1, (SIZE3_64 | SIZE2_64 | SIZE1_64 | SIZE0_64)
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| 115 | sh t1, (t0)
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| 116 |
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| 117 | /*
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| 118 | * ãã¹ã³ã³ããã¼ã«ã¦ããã(BCU)é¢ä¿ã®åæè¨å®
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| 119 | */
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| 120 | li t0, ASM_SIL( IO0SPEEDREG )
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| 121 | lh t1, (t0)
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| 122 | ori t1, t1, IO0_1_WAIT_4
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| 123 | sh t1, (t0)
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| 124 |
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| 125 | li t0, ASM_SIL( IO1SPEEDREG )
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| 126 | lh t1, (t0)
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| 127 | ori t1, t1, IO1_3_WAIT_11
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| 128 | sh t1, (t0)
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| 129 |
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| 130 | /*
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| 131 | * HALTimerã·ã£ãããã¦ã³ã®ã¯ãªã¢
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| 132 | * CPUèµ·åå¾ã4ç§ä»¥å
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| 133 | ã«è¡ããªããã°ãªããªã
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| 134 | * PMUã³ã³ããã¼ã«ã¬ã¸ã¹ã¿ã®HALTimerãªã»ãããããã«ï¼ãæ¸ãè¾¼ã
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| 135 | */
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| 136 | li t0, ASM_SIL( PMUCNTREG )
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| 137 | lh t1, (t0)
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| 138 | ori t1, t1, HALTIMERRST
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| 139 | sh t1, (t0)
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| 140 |
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| 141 | /*
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| 142 | * HALTimerãªã»ããã®ã¯ãªã¢
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| 143 | * PMUå²è¾¼ã¿ï¼ã¹ãã¼ã¿ã¹ã¬ã¸ã¹ã¿ã®TIMOUTRSTãããã«ï¼ãæ¸ãè¾¼ã
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| 144 | */
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| 145 | li t0, ASM_SIL( PMUINTREG )
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| 146 | lh t1, (t0)
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| 147 | ori t1, t1, TIMOUTRST
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| 148 | sh t1, (t0)
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| 149 |
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| 150 | /*
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| 151 | * TLBã®åæå
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| 152 | */
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| 153 | tlb_initialize:
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| 154 | mtc0 zero, PageMask
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| 155 | mtc0 zero, EntryLo0
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| 156 | mtc0 zero, EntryLo1
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| 157 |
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| 158 | li t0, TMAX_TLB
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| 159 | li t1, 0xA0000000 /* kseg1 ã®ä¸ã®DRAMã®æãä½¿ç¨ */
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| 160 | loop_TLB_clear:
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| 161 | mtc0 t0, Index
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| 162 | mtc0 t1, EntryHi
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| 163 | addiu t0, t0, -1
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| 164 | addiu t1, t1, TLB_VPN2 /* 1ãã¼ã¸ã4kãã¤ãã§ã2ãã¼ã¸åãããã
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| 165 | ã³ã°ãããã */
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| 166 | tlbwi
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| 167 | bgez t0, loop_TLB_clear
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| 168 | nop
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| 169 |
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| 170 | /*
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| 171 | * ãã£ãã·ã¥ã®åæå
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| 172 | */
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| 173 | cache_initialize:
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| 174 | mtc0 zero, TagLo
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| 175 | mtc0 zero, TagHi
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| 176 |
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| 177 | li t0, 0x80001ff0 /* 512 line å (1 line = 16 byte) */
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| 178 | li t1, 0x80000000
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| 179 | loop_I_cache_clear:
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| 180 | cache Index_Invalidate_I, 0x0000(t0)
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| 181 | cache Index_Invalidate_I, 0x2000(t0)
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| 182 | bne t0, t1, loop_I_cache_clear
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| 183 | addiu t0, t0, -I_CACHE_LINE_SIZE
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| 184 |
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| 185 | li t0, 0x80001ff0 /* 512 line å (1 line = 16 byte) */
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| 186 | li t1, 0x80000000
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| 187 | loop_D_cache_clear:
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| 188 | cache Index_Store_Tag_D, 0x0000(t0)
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| 189 | cache Index_Store_Tag_D, 0x2000(t0)
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| 190 | bne t0, t1, loop_D_cache_clear
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| 191 | addiu t0, t0, -D_CACHE_LINE_SIZE
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| 192 |
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| 193 | /*
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| 194 | * å¼ã³åºãå
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| 195 | ã¸ãªã¿ã¼ã³
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| 196 | */
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| 197 | return_to_common:
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| 198 | j ra
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| 199 | nop
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| 200 |
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| 201 | #endif /* GDB_STUB */
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