[363] | 1 | /*
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| 2 | * TOPPERS/JSP Kernel
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| 3 | * Toyohashi Open Platform for Embedded Real-Time Systems/
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| 4 | * Just Standard Profile Kernel
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| 5 | *
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| 6 | * Copyright (C) 2000-2003 by Embedded and Real-Time Systems Laboratory
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| 7 | * Toyohashi Univ. of Technology, JAPAN
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| 8 | *
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| 9 | * ä¸è¨èä½æ¨©è
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| 10 | ã¯ï¼ä»¥ä¸ã® (1)ã(4) ã®æ¡ä»¶ãï¼Free Software Foundation
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| 11 | * ã«ãã£ã¦å
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| 12 | ¬è¡¨ããã¦ãã GNU General Public License ã® Version 2 ã«è¨
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| 13 | * è¿°ããã¦ããæ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§ã¢ï¼æ¬ã½ããã¦ã§ã¢
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| 14 | * ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ã使ç¨ã»è¤è£½ã»æ¹å¤ã»åé
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| 15 | å¸ï¼ä»¥ä¸ï¼
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| 16 | * å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
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| 17 | * (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
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| 18 | * 権表示ï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
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| 19 | * ã¹ã³ã¼ãä¸ã«å«ã¾ãã¦ãããã¨ï¼
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| 20 | * (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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| 21 | * ç¨ã§ããå½¢ã§åé
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| 22 | å¸ããå ´åã«ã¯ï¼åé
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| 23 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨
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| 24 | * è
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| 25 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
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| 26 | * ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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| 27 | * (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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| 28 | * ç¨ã§ããªãå½¢ã§åé
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| 29 | å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
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| 30 | * ã¨ï¼
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| 31 | * (a) åé
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| 32 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨è
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| 33 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
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| 34 | * ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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| 35 | * (b) åé
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| 36 | å¸ã®å½¢æ
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| 37 | ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSããã¸ã§ã¯ãã«
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| 38 | * å ±åãããã¨ï¼
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| 39 | * (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
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| 40 | * 害ãããï¼ä¸è¨èä½æ¨©è
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| 41 | ããã³TOPPERSããã¸ã§ã¯ããå
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| 42 | 責ãããã¨ï¼
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| 43 | *
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| 44 | * æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
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| 45 | ã
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| 46 | * ãã³TOPPERSããã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ãã®é©ç¨å¯è½æ§ã
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| 47 | * å«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´
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| 48 | * æ¥çã¾ãã¯éæ¥çã«çãããããªãæ害ã«é¢ãã¦ãï¼ãã®è²¬ä»»ãè² ããªãï¼
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| 49 | *
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| 50 | * @(#) $Id: lm32.h,v 1.14 2007/07/27 11:28:44 honda Exp $
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| 51 | */
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| 52 |
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| 53 | #ifndef _LM32_H_
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| 54 | #define _LM32_H_
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| 55 |
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| 56 | #define MICO32_CPU_CLOCK_HZ (25000000)
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| 57 | //#define MICO32_CPU_CLOCK_HZ (100000000)
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| 58 |
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| 59 | #define DEFAULT_UART_BAUDRATE (115200)
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| 60 |
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| 61 | #define TIMER_BASE_REG (0x80000100)
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| 62 | #define UART1_BASE_REG (0x80000180)
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| 63 |
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| 64 | /*
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| 65 | * Timer Registers
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| 66 | */
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| 67 | #define TIMER_STATUS (TIMER_BASE_REG)
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| 68 | #define TIMER_CONTROL (TIMER_BASE_REG + 0x04)
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| 69 | #define TIMER_PERIOD (TIMER_BASE_REG + 0x08)
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| 70 | #define TIMER_SNAPSHOT (TIMER_BASE_REG + 0x0C)
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| 71 |
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| 72 | #define TIMER_STATUS_TO (0x01)
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| 73 | #define TIMER_CONTROL_ITO (0x01)
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| 74 | #define TIMER_CONTROL_CONT (0x02)
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| 75 | #define TIMER_CONTROL_START (0x04)
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| 76 | #define TIMER_CONTROL_STOP (0x08)
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| 77 |
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| 78 | /*
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| 79 | * UART0 Registers
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| 80 | */
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| 81 | #define UART1_RX_TX (UART1_BASE_REG)
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| 82 | #define UART1_IER (UART1_BASE_REG + 0x04)
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| 83 | #define UART1_IIR (UART1_BASE_REG + 0x08)
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| 84 | #define UART1_LCR (UART1_BASE_REG + 0x0C)
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| 85 | #define UART1_MCR (UART1_BASE_REG + 0x10)
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| 86 | #define UART1_LSR (UART1_BASE_REG + 0x14)
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| 87 | #define UART1_MSR (UART1_BASE_REG + 0x18)
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| 88 | #define UART1_DIV (UART1_BASE_REG + 0x1C)
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| 89 |
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| 90 | /*
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| 91 | * UART1 Registers
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| 92 | */
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| 93 | #define UART2_RX_TX (UART2_BASE_REG)
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| 94 | #define UART2_IER (UART2_BASE_REG + 0x04)
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| 95 | #define UART2_IIR (UART2_BASE_REG + 0x08)
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| 96 | #define UART2_LCR (UART2_BASE_REG + 0x0C)
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| 97 | #define UART2_MCR (UART2_BASE_REG + 0x10)
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| 98 | #define UART2_LSR (UART2_BASE_REG + 0x14)
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| 99 | #define UART2_MSR (UART2_BASE_REG + 0x18)
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| 100 | #define UART2_DIV (UART2_BASE_REG + 0x1C)
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| 101 |
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| 102 | #define UART_IER_RX_INT_MASK (0x01)
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| 103 | #define UART_IER_TX_INT_MASK (0x02)
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| 104 | #define UART_LSR_RX_RDY_MASK (0x01)
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| 105 | #define UART_LSR_TX_RDY_MASK (0x20)
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| 106 | #define UART_IIR_RXRDY (0x04)
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| 107 | #define UART_IIR_TXRDY (0x02)
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| 108 |
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| 109 | #define MAX_INT_NUM 32
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| 110 |
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| 111 | #define INHNO_TIMER 0
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| 112 | #define INHNO_SIO1 1
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| 113 |
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| 114 | #define TNUM_PORT 1
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| 115 | #define TNUM_SIOP 1
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| 116 |
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| 117 | #ifndef _MACRO_ONLY
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| 118 |
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| 119 | extern void uart1_isr(void);
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| 120 | extern void uart2_isr(void);
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| 121 |
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| 122 | typedef struct sio_port_initialization_block
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| 123 | {
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| 124 | volatile VP rxtx;
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| 125 | volatile VP ier;
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| 126 | volatile VP iir;
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| 127 | volatile VP lcr;
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| 128 | volatile VP mcr;
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| 129 | volatile VP lsr;
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| 130 | volatile VP msr;
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| 131 | volatile VP div;
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| 132 | }
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| 133 | SIOPINIB;
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| 134 |
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| 135 | typedef struct sio_port_control_block
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| 136 | {
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| 137 | const SIOPINIB *siopinib;
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| 138 | VP_INT exinf;
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| 139 | BOOL openflag;
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| 140 | BOOL sendflag;
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| 141 | BOOL getready;
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| 142 | BOOL putready;
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| 143 | UW ier_snapshot;
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| 144 | }SIOPCB;
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| 145 |
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| 146 | #define SIO_ERDY_SND 1u
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| 147 | #define SIO_ERDY_RCV 2u
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| 148 |
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| 149 | extern void uart_putc(char c);
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| 150 | extern void uart_initialize(void);
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| 151 | extern BOOL uart_openflag(void);
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| 152 | extern SIOPCB *uart_opn_por(ID siopid, VP_INT exinf);
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| 153 | extern void uart_cls_por(SIOPCB *siopcb);
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| 154 | extern BOOL uart_snd_chr(SIOPCB *siopcb, char c);
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| 155 | extern INT uart_rcv_chr(SIOPCB *siopcb);
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| 156 | extern void uart_ena_cbr(SIOPCB *siopcb, UINT cbrtn);
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| 157 | extern void uart_dis_cbr(SIOPCB *siopcb, UINT cbrtn);
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| 158 | extern void uart_in_isr(void);
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| 159 | extern void uart_out_isr(void);
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| 160 | extern void uart_ierdy_snd(VP_INT exinf);
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| 161 | extern void uart_ierdy_rcv(VP_INT exinf);
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| 162 |
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| 163 | #endif /* _MACRO_ONLY */
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| 164 | #endif /* _LM32_H_ */
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