1 | /*
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2 | * TOPPERS/JSP Kernel
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3 | * Toyohashi Open Platform for Embedded Real-Time Systems/
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4 | * Just Standard Profile Kernel
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5 | *
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6 | * Copyright (C) 2000-2004 by Embedded and Real-Time Systems Laboratory
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7 | * Toyohashi Univ. of Technology, JAPAN
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8 | * Copyright (C) 2001-2004 by Dep. of Computer Science and Engineering
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9 | * Tomakomai National College of Technology, JAPAN
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10 | * Copyright (C) 2001-2007 by Industrial Technology Institute,
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11 | * Miyagi Prefectural Government, JAPAN
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12 | *
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13 | * ä¸è¨è使¨©è
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14 | ã¯ï¼ä»¥ä¸ã® (1)ã(4) ã®æ¡ä»¶ãï¼Free Software Foundation
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15 | * ã«ãã£ã¦å
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16 | ¬è¡¨ããã¦ãã GNU General Public License ã® Version 2 ã«è¨
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17 | * è¿°ããã¦ããæ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§ã¢ï¼æ¬ã½ããã¦ã§ã¢
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18 | * ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ã使ç¨ã»è¤è£½ã»æ¹å¤ã»åé
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19 | å¸ï¼ä»¥ä¸ï¼
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20 | * å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
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21 | * (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
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22 | * 権表示ï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
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23 | * ã¹ã³ã¼ãä¸ã«å«ã¾ãã¦ãããã¨ï¼
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24 | * (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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25 | * ç¨ã§ããå½¢ã§åé
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26 | å¸ããå ´åã«ã¯ï¼åé
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27 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨
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28 | * è
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29 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è使¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
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30 | * ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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31 | * (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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32 | * ç¨ã§ããªãå½¢ã§åé
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33 | å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
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34 | * ã¨ï¼
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35 | * (a) åé
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36 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨è
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37 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
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38 | * 使¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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39 | * (b) åé
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40 | å¸ã®å½¢æ
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41 | ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSããã¸ã§ã¯ãã«
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42 | * å ±åãããã¨ï¼
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43 | * (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
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44 | * 害ãããï¼ä¸è¨è使¨©è
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45 | ããã³TOPPERSããã¸ã§ã¯ããå
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46 | 責ãããã¨ï¼
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47 | *
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48 | * æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨è使¨©è
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49 | ã
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50 | * ãã³TOPPERSããã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ãã®é©ç¨å¯è½æ§ã
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51 | * å«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´
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52 | * æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ãã®è²¬ä»»ãè² ããªãï¼
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53 | */
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54 |
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55 | /*
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56 | * ããã»ããµä¾åã¢ã¸ã¥ã¼ã«(H8Sç¨)
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57 | */
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58 |
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59 | #include "jsp_kernel.h"
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60 | #include "check.h"
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61 | #include "task.h"
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62 |
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63 | /*
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64 | * ã¿ã¹ã¯ã³ã³ããã¹ãã§ã®å²è¾¼ã¿ãã¹ã¯
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65 | */
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66 | #ifdef SUPPORT_CHG_IPM
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67 | volatile IPM task_intmask = 0; /* IPM -> UBï¼ç¬¦å·ç¡ã8ããã */
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68 | #endif /* SUPPORT_CHG_IPM */
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69 |
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70 | /*
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71 | * éã¿ã¹ã¯ã³ã³ããã¹ãã§ã®å²è¾¼ã¿ãã¹ã¯
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72 | */
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73 | volatile IPM int_intmask = 0;
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74 |
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75 | /*
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76 | * å²è¾¼ã¿ãã¹ãã«ã¦ã³ã¿
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77 | */
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78 | volatile UB intnest = 1;
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79 |
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80 | /*
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81 | * CPUããã¯ç¶æ
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82 | ã表ããã©ã°
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83 | * ãã»å²è¾¼ã¿ç¦æ¢ï¼ã«ã¼ãã«ç®¡çä¸ã®å²è¾¼ã¿ã®ã¿ï¼
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84 | * ããããã¤
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85 | * ãã»iscpulocked == TRUE
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86 | * ãããã®ã¨ãCPUããã¯ç¶æ
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87 | ã¨ããã
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88 | */
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89 | volatile BOOL iscpulocked = TRUE;
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90 |
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91 | /*
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92 | * ããã»ããµä¾åã®åæå
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93 | */
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94 | void cpu_initialize(void) {
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95 |
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96 | /*
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97 | * 以ä¸ã®4ã¤ã¯ã¹ã¿ã¼ãã¢ããã«ã¼ãã³ã§åæåãæ¸ãã§ããã
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98 | * ããã»å²è¾¼ã¿ãã¹ãã«ã¦ã³ã¿ intnest = 1;
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99 | * ããã»éã¿ã¹ã¯ã³ã³ããã¹ãã®å²è¾¼ã¿ãã¹ã¯ int_intmask = 0;
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100 | * ããã»ã¿ã¹ã¯ã³ã³ããã¹ãã®å²è¾¼ã¿ãã¹ã¯ task_intmask = 0;
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101 | * ããããï¼chg_ipmããµãã¼ãããå ´åï¼
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102 | * ããã»CPUããã¯ãã©ã° iscpulocked = TRUE;
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103 | */
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104 |
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105 | /* å²è¾¼ã¿å¶å¾¡ã¢ã¼ãã®è¨å® */
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106 | h8s_wrb_reg(SYSCR, SYS_SYSCR);
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107 |
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108 | /* å²è¾¼ã¿ã¬ãã«ã®åæå */
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109 | h8s_wrb_reg(IPRA, 0);
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110 | h8s_wrb_reg(IPRB, 0);
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111 | h8s_wrb_reg(IPRC, 0);
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112 | h8s_wrb_reg(IPRD, 0);
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113 | h8s_wrb_reg(IPRE, 0);
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114 | h8s_wrb_reg(IPRF, 0);
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115 | h8s_wrb_reg(IPRG, 0);
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116 | h8s_wrb_reg(IPRH, 0);
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117 | h8s_wrb_reg(IPRI, 0);
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118 | h8s_wrb_reg(IPRJ, 0);
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119 | h8s_wrb_reg(IPRK, 0);
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120 | }
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121 |
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122 | /*
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123 | * ããã»ããµä¾åã®çµäºå¦ç
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124 | */
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125 | void cpu_terminate(void) {
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126 | }
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127 |
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128 | /*
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129 | * 微尿éå¾
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130 | ã¡
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131 | * ããæ³¨æäºé
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132 | ï¼
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133 | * ãããæ¨æºã§ã¯dlytimã¯UINTåã ã16ããããããªãã®ã§ã
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134 | * ãããUWåã«å¤æ´ãã¦ããã
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135 | * ãããsil_dly_nse()ã¯å
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136 | é¨ã§sil_dly_nse_long()ãå¼ã³åºãã
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137 | */
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138 | void sil_dly_nse(UINT dlytim) {
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139 | sil_dly_nse_long((UW)dlytim);
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140 | }
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141 |
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142 | #ifdef SUPPORT_CHG_IPM
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143 |
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144 | /*
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145 | * å²è¾¼ã¿ãã¹ã¯ã®å¤æ´
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146 | *
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147 | *ãIPMã«è¨å®ã§ããå¤ã¯0ãMAX_IPMã§ããã
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148 | *ãå²è¾¼ã¿ãã©ã¤ãªãªãã£ã¬ãã«ã(MAX_IPM+1)以ä¸ã®å²è¾¼ã¿ã¯ã«ã¼ãã«ç®¡çå¤
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149 | *ãæ±ãã§ããã
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150 | *
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151 | * IPM ã 0 以å¤ã®æã«ãï¼ã¿ã¹ã¯ãã£ã¹ãããã¯ä¿çãããªãï¼
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152 | * ãã£ã¹ããããç¦æ¢ãããå ´åã«ã¯ï¼loc_cpu ã«ããCPUããã¯ç¶æ
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153 | ã«
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154 | * ããã°ããï¼IPM ã¯ï¼
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155 | * ã¿ã¹ã¯ãã£ã¹ãããã«ãã£ã¦ï¼æ°ããå®è¡ç¶æ
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156 | ã«ãªã£ãã¿ã¹ã¯ã¸å¼ãç¶ã
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157 | * ããï¼ãã®ããï¼ã¿ã¹ã¯ãå®è¡ä¸ã«ï¼å¥ã®ã¿ã¹ã¯ã«ãã£ã¦ IPM ã夿´ã
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158 | * ããå ´åãããï¼JSPã«ã¼ãã«ã§ã¯ï¼IPM ã®å¤æ´ã¯ã¿ã¹ã¯ä¾å¤å¦çã«ã¼ã
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159 | * ã³ã«ãã£ã¦ãèµ·ããã®ãï¼ããã«ãã£ã¦æ±ããé£ãããªãç¶æ³ã¯å°ãªãã¨
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160 | * æãããï¼
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161 | *ãIPM ã®å¤ã«ãã£ã¦ã¿ã¹ã¯ãã£ã¹ããããç¦æ¢ãããå ´åã«ã¯ï¼dis_dspã
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162 | * ä½µç¨ããã°ããï¼
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163 | */
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164 | SYSCALL ER
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165 | chg_ipm(IPM ipm)
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166 | {
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167 | ER ercd = E_OK;
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168 |
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169 | LOG_CHG_IPM_ENTER(ipm);
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170 | CHECK_TSKCTX_UNL();
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171 | CHECK_PAR(ipm <= MAX_IPM);
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172 |
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173 | t_lock_cpu();
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174 | task_intmask = ipm;
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175 | t_unlock_cpu();
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176 |
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177 | exit:
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178 | LOG_CHG_IPM_LEAVE(ercd)
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179 | return(ercd);
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180 | }
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181 |
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182 | /*
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183 | * å²è¾¼ã¿ãã¹ã¯ã®åç
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184 | §
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185 | */
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186 | SYSCALL ER
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187 | get_ipm(IPM *p_ipm)
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188 | {
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189 | ER ercd = E_OK;
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190 |
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191 | LOG_GET_IPM_ENTER(p_ipm);
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192 | CHECK_TSKCTX_UNL();
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193 |
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194 | t_lock_cpu();
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195 | *p_ipm = task_intmask;
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196 | t_unlock_cpu();
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197 |
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198 | exit:
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199 | LOG_GET_IPM_LEAVE(ercd, *p_ipm);
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200 | return(ercd);
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201 | }
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202 |
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203 |
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204 | #endif /* SUPPORT_CHG_IPM */
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205 |
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206 | /*============================================================================*/
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207 | /* å
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208 | ±éããã¥ã¡ã³ãã«ã¯ãªããç¬èªã®é¨å */
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209 |
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210 | /*
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211 | * ç»é²ããã¦ããªãå²ãè¾¼ã¿ãçºçããã¨å¼ã³åºããã
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212 | */
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213 | void
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214 | cpu_experr(EXCSTACK *sp)
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215 | {
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216 | UW sp2, pc, ccr, tmp;
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217 |
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218 | sp2 = (UW)sp + OFFSET_SP;
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219 | tmp = sp->pc;
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220 | ccr = (tmp >> 24U) & 0xff; /* ä¸ä½1ãã¤ã */
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221 | pc = tmp & 0x00ffffffUL; /* ä¸ä½3ãã¤ã */
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222 |
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223 | syslog(LOG_EMERG, "Unexpected interrupt.");
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224 | syslog(LOG_EMERG, "PC = 0x%08lx SP = 0x%08lx CCR = 0x%02x",
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225 | (VP)pc, (VP)sp2, (INT)ccr);
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226 | syslog(LOG_EMERG, "EXR = 0x%02x", (INT)(sp->exr));
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227 | syslog(LOG_EMERG, "ER0 = 0x%08lx ER1 = 0x%08lx ER2 = 0x%08lx ER3 = 0x%08lx",
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228 | (VP)(sp->er0), (VP)(sp->er1), (VP)(sp->er2), (VP)(sp->er3));
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229 | syslog(LOG_EMERG, "ER4 = 0x%08lx ER5 = 0x%08lx ER6 = 0x%08lx",
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230 | (VP)(sp->er4), (VP)(sp->er5), (VP)(sp->er6));
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231 | while(1)
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232 | ;
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233 | }
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234 |
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235 |
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236 | /*============================================================================*/
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237 | /* ãããã°ç¨ã³ã¼ã */
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238 |
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239 | #ifdef TEST_CPU_INSN
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240 |
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241 | volatile UB ccr, exr;
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242 | volatile IPM intmask;
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243 |
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244 | void test_cpu_insn(void)
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245 | {
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246 | ccr = current_ccr();
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247 | set_ccr(0xf);
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248 | ccr = current_ccr();
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249 |
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250 | exr = current_exr();
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251 | set_exr(0x7);
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252 | exr = current_exr();
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253 |
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254 | intmask = current_intmask();
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255 | set_intmask(0x3);
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256 | intmask = current_intmask();
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257 |
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258 | disint();
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259 | enaint();
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260 |
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261 | _disint_();
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262 | }
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263 |
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264 | #endif /* TEST_CPU_INSN */
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265 |
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266 |
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267 | #ifdef TEST_CPU_CONFIG
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268 |
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269 | volatile BOOL b;
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270 | volatile ER err;
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271 | volatile IPM ipm;
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272 |
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273 | void dummy(void)
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274 | {
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275 | }
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276 |
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277 | void test_cpu_config(void)
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278 | {
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279 | b = sense_context();
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280 | dummy();
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281 | intnest = 1;
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282 | dummy();
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283 | b = sense_context();
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284 | dummy();
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285 | intnest = 0;
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286 | dummy();
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287 | b = sense_context();
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288 | dummy();
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289 |
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290 | b = t_sense_lock();
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291 | dummy();
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292 | t_lock_cpu();
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293 | dummy();
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294 | b = t_sense_lock();
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295 | dummy();
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296 | t_unlock_cpu();
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297 | dummy();
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298 | b = t_sense_lock();
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299 | dummy();
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300 |
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301 | i_lock_cpu();
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302 | dummy();
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303 | b = i_sense_lock();
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304 | dummy();
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305 | i_unlock_cpu();
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306 | dummy();
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307 | b = i_sense_lock();
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308 | dummy();
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309 |
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310 | err = chg_ipm(6);
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311 | dummy();
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312 | err = get_ipm(&ipm);
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313 | dummy();
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314 | err = chg_ipm(3);
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315 | dummy();
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316 | err = get_ipm(&ipm);
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317 | dummy();
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318 | err = chg_ipm(8);
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319 | dummy();
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320 | }
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321 |
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322 | #endif /* TEST_CPU_CONFIG */
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323 |
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324 | #ifdef TEST_H8S_SIL
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325 |
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326 | volatile UB ddr;
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327 |
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328 | void test_h8s_sil(void)
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329 | {
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330 | ddr = sil_reb_ddr(IO_PORT7);
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331 | sil_wrb_ddr(IO_PORT7, 0xff);
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332 | ddr = sil_reb_ddr(IO_PORT7);
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333 | sil_anb_ddr(IO_PORT7, 0xf);
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334 | ddr = sil_reb_ddr(IO_PORT7);
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335 | sil_orb_ddr(IO_PORT7, 0x80);
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336 | ddr = sil_reb_ddr(IO_PORT7);
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337 | }
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338 |
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339 | #endif /* TEST_H8S_SIL */
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340 |
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341 |
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342 |
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