source: anotherchoice/tags/jsp-1.4.4-full-UTF8/config/h8/h8_3052f.h@ 26

Last change on this file since 26 was 26, checked in by ykominami, 10 years ago

initial

File size: 17.5 KB
Line 
1/*
2 * TOPPERS/JSP Kernel
3 * Toyohashi Open Platform for Embedded Real-Time Systems/
4 * Just Standard Profile Kernel
5 *
6 * Copyright (C) 2000-2004 by Embedded and Real-Time Systems Laboratory
7 * Toyohashi Univ. of Technology, JAPAN
8 * Copyright (C) 2001-2010 by Industrial Technology Institute,
9 * Miyagi Prefectural Government, JAPAN
10 * Copyright (C) 2001-2004 by Dep. of Computer Science and Engineering
11 * Tomakomai National College of Technology, JAPAN
12 *
13 * 上記著作権者
14は,以下の (1)〜(4) の条件か,Free Software Foundation
15 * によってå…
16¬è¡¨ã•ã‚Œã¦ã„ã‚‹ GNU General Public License の Version 2 に記
17 * 述されている条件を満たす場合に限り,本ソフトウェア(本ソフトウェア
18 * を改変したものを含む.以下同じ)を使用・複製・改変・再é…
19å¸ƒï¼ˆä»¥ä¸‹ï¼Œ
20 * 利用と呼ぶ)することを無償で許諾する.
21 * (1) 本ソフトウェアをソースコードの形で利用する場合には,上記の著作
22 * 権表示,この利用条件および下記の無保証規定が,そのままの形でソー
23 * スコード中に含まれていること.
24 * (2) 本ソフトウェアを,ライブラリ形式など,他のソフトウェア開発に使
25 * 用できる形で再é…
26å¸ƒã™ã‚‹å ´åˆã«ã¯ï¼Œå†é…
27å¸ƒã«ä¼´ã†ãƒ‰ã‚­ãƒ¥ãƒ¡ãƒ³ãƒˆï¼ˆåˆ©ç”¨
28 * 者
29マニュアルなど)に,上記の著作権表示,この利用条件および下記
30 * の無保証規定を掲載すること.
31 * (3) 本ソフトウェアを,機器に組み込むなど,他のソフトウェア開発に使
32 * 用できない形で再é…
33å¸ƒã™ã‚‹å ´åˆã«ã¯ï¼Œæ¬¡ã®ã„ずれかの条件を満たすこ
34 * と.
35 * (a) 再é…
36å¸ƒã«ä¼´ã†ãƒ‰ã‚­ãƒ¥ãƒ¡ãƒ³ãƒˆï¼ˆåˆ©ç”¨è€…
37マニュアルなど)に,上記の著
38 * 作権表示,この利用条件および下記の無保証規定を掲載すること.
39 * (b) 再é…
40å¸ƒã®å½¢æ…
41‹ã‚’,別に定める方法によって,TOPPERSプロジェクトに
42 * 報告すること.
43 * (4) 本ソフトウェアの利用により直接的または間接的に生じるいかなる損
44 * 害からも,上記著作権者
45およびTOPPERSプロジェクトをå…
46è²¬ã™ã‚‹ã“と.
47 *
48 * 本ソフトウェアは,無保証で提供されているものである.上記著作権者
49お
50 * よびTOPPERSプロジェクトは,本ソフトウェアに関して,その適用可能性も
51 * 含めて,いかなる保証も行わない.また,本ソフトウェアの利用により直
52 * 接的または間接的に生じたいかなる損害に関しても,その責任を負わない.
53 *
54 * @(#) $Id: h8_3052f.h,v 1.4 2007/03/23 07:22:15 honda Exp $
55 */
56
57#ifndef _H8_3052F_H_
58#define _H8_3052F_H_
59
60/*
61 * H8/3052F 用定義
62 */
63
64/* Interrupt numbers */
65
66#define IRQ_NMI 7 /* NMI */
67
68#define IRQ_EXT0 12 /* IRQ0 */
69#define IRQ_EXT1 13 /* IRQ1 */
70#define IRQ_EXT2 14 /* IRQ2 */
71#define IRQ_EXT3 15 /* IRQ3 */
72#define IRQ_EXT4 16 /* IRQ4 */
73#define IRQ_EXT5 17 /* IRQ5 */
74
75#define IRQ_WOVI 20 /* Watch Doc Timer */
76
77#define IRQ_CMI 21 /* Compare Match */
78
79#define IRQ_IMIA0 24 /* ITU0 IMIA0 */
80#define IRQ_IMIB0 25 /* ITU0 IMIB0 */
81#define IRQ_OVI0 26 /* ITU0 OVI0 */
82
83#define IRQ_IMIA1 28 /* ITU1 IMIA1 */
84#define IRQ_IMIB1 29 /* ITU1 IMIB1 */
85#define IRQ_OVI1 30 /* ITU1 OVI1 */
86
87#define IRQ_IMIA2 32 /* ITU2 IMIA2 */
88#define IRQ_IMIB2 33 /* ITU2 IMIB2 */
89#define IRQ_OVI2 34 /* ITU2 OVI2 */
90
91#define IRQ_IMIA3 36 /* ITU3 IMIA3 */
92#define IRQ_IMIB3 37 /* ITU3 IMIB3 */
93#define IRQ_OVI3 38 /* ITU3 OVI3 */
94
95#define IRQ_IMIA4 40 /* ITU4 IMIA4 */
96#define IRQ_IMIB4 41 /* ITU4 IMIB4 */
97#define IRQ_OVI4 42 /* ITU4 OVI4 */
98
99#define IRQ_DEND0A 44 /* DMAC */
100#define IRQ_DEND0B 45 /* DMAC */
101#define IRQ_DEND1A 46 /* DMAC */
102#define IRQ_DEND1B 47 /* DMAC */
103
104#define IRQ_ERI0 52 /* SCI0 ERI */
105#define IRQ_RXI0 53 /* SCI0 RXI */
106#define IRQ_TXI0 54 /* SCI0 TXI */
107#define IRQ_TEI0 55 /* SCI0 TEI */
108
109#define IRQ_ERI1 56 /* SCI1 ERI */
110#define IRQ_RXI1 57 /* SCI1 RXI */
111#define IRQ_TXI1 58 /* SCI1 TXI */
112#define IRQ_TEI1 59 /* SCI1 TEI */
113
114#define IRQ_ADI 60 /* A/D */
115
116/* register address */
117
118/* I/O ports */
119
120/* port1: A0 - A7 */
121
122#define H8P1DDR 0xffffc0
123#define H8P1DR 0xffffc2
124
125/* port2: A8 - A15 */
126
127#define H8P2DDR 0xffffc1
128#define H8P2DR 0xffffc3
129#define H8P2PCR 0xffffd8
130
131/* port3: D8 - D15 */
132
133#define H8P3DDR 0xffffc4
134#define H8P3DR 0xffffc6
135
136/* port4: D0 - D7 */
137
138#define H8P4DDR 0xffffc5
139#define H8P4DR 0xffffc7
140#define H8P4PCR 0xffffda
141
142/* port5: A16 - A19 */
143
144#define H8P5DDR 0xffffc8
145#define H8P5DR 0xffffca
146#define H8P5PCR 0xffffdb
147
148#define H8P5DDR_A19_BIT 3
149#define H8P5DDR_A18_BIT 2
150#define H8P5DDR_A17_BIT 1
151#define H8P5DDR_A16_BIT 0
152
153#define H8P5DDR_A19 (1<<H8P5DDR_A19_BIT)
154#define H8P5DDR_A18 (1<<H8P5DDR_A18_BIT)
155#define H8P5DDR_A17 (1<<H8P5DDR_A17_BIT)
156#define H8P5DDR_A16 (1<<H8P5DDR_A16_BIT)
157
158/* port6 */
159
160#define H8P6DDR 0xffffc9
161#define H8P6DR 0xffffcb
162
163#define H8P6DDR_HWR_BIT 6
164#define H8P6DDR_LWR_BIT 5
165#define H8P6DDR_RD_BIT 4
166#define H8P6DDR_AS_BIT 3
167#define H8P6DDR_BACK_BIT 2
168#define H8P6DDR_BREQ_BIT 1
169#define H8P6DDR_WAIT_BIT 0
170
171#define H8P6DDR_HWR (1<<H8P6DDR_HWR_BIT)
172#define H8P6DDR_LWR (1<<H8P6DDR_LWR_BIT)
173#define H8P6DDR_RD (1<<H8P6DDR_RD_BIT)
174#define H8P6DDR_AS (1<<H8P6DDR_AS_BIT)
175#define H8P6DDR_BACK (1<<H8P6DDR_BACK_BIT)
176#define H8P6DDR_BREQ (1<<H8P6DDR_BREQ_BIT)
177#define H8P6DDR_WAIT (1<<H8P6DDR_WAIT_BIT)
178
179/* port7 */
180
181#define H8P7DR 0xffffce
182
183/* port8 */
184
185#define H8P8DDR 0xffffcd
186#define H8P8DR 0xffffcf
187
188#define H8P8DDR_CS0_BIT 4
189#define H8P8DDR_CS1_BIT 3
190#define H8P8DDR_CS2_BIT 2
191#define H8P8DDR_CS3_BIT 1
192#define H8P8DDR_RFSH_BIT 0
193
194#define H8P8DDR_CS0 (1<<H8P8DDR_CS0_BIT)
195#define H8P8DDR_CS1 (1<<H8P8DDR_CS1_BIT)
196#define H8P8DDR_CS2 (1<<H8P8DDR_CS2_BIT)
197#define H8P8DDR_CS3 (1<<H8P8DDR_CS3_BIT)
198#define H8P8DDR_RFSH (1<<H8P8DDR_RFSH_BIT)
199
200#define H8P8DDR_IRQ3_BIT 3
201#define H8P8DDR_IRQ2_BIT 2
202#define H8P8DDR_IRQ1_BIT 1
203#define H8P8DDR_IRQ0_BIT 0
204
205#define H8P8DDR_IRQ3 (1<<H8P8DDR_IRQ3_BIT)
206#define H8P8DDR_IRQ2 (1<<H8P8DDR_IRQ2_BIT)
207#define H8P8DDR_IRQ1 (1<<H8P8DDR_IRQ1_BIT)
208#define H8P8DDR_IRQ0 (1<<H8P8DDR_IRQ0_BIT)
209
210/* port9 (SCI) */
211
212#define H8P9DDR 0xffffd0
213#define H8P9DR 0xffffd2
214
215#define H8P9DDR_SCK1_BIT 5
216#define H8P9DDR_SCK0_BIT 4
217#define H8P9DDR_RXD1_BIT 3
218#define H8P9DDR_RXD0_BIT 2
219#define H8P9DDR_TXD1_BIT 1
220#define H8P9DDR_TXD0_BIT 0
221
222#define H8P9DDR_SCK1 (1<<H8P9DDR_SCK1_BIT)
223#define H8P9DDR_SCK0 (1<<H8P9DDR_SCK0_BIT)
224#define H8P9DDR_RXD1 (1<<H8P9DDR_RXD1_BIT)
225#define H8P9DDR_RXD0 (1<<H8P9DDR_RXD0_BIT)
226#define H8P9DDR_TXD1 (1<<H8P9DDR_TXD1_BIT)
227#define H8P9DDR_TXD0 (1<<H8P9DDR_TXD0_BIT)
228
229#define H8P9DDR_IRQ5_BIT 5
230#define H8P9DDR_IRQ4_BIT 4
231
232#define H8P9DDR_IRQ5 (1<<H8P9DDR_IRQ5_BIT)
233#define H8P9DDR_IRQ4 (1<<H8P9DDR_IRQ4_BIT)
234
235/* portA (TPC/ITU/DMA) */
236
237#define H8PADDR 0xffffd1
238#define H8PADR 0xffffd3
239
240#define H8PADDR_TP7_BIT 7
241#define H8PADDR_TP6_BIT 6
242#define H8PADDR_TP5_BIT 5
243#define H8PADDR_TP4_BIT 4
244#define H8PADDR_TP3_BIT 3
245#define H8PADDR_TP2_BIT 2
246#define H8PADDR_TP1_BIT 1
247#define H8PADDR_TP0_BIT 0
248
249#define H8PADDR_TP7 (1<<H8PADDR_TP7_BIT)
250#define H8PADDR_TP6 (1<<H8PADDR_TP6_BIT)
251#define H8PADDR_TP5 (1<<H8PADDR_TP5_BIT)
252#define H8PADDR_TP4 (1<<H8PADDR_TP4_BIT)
253#define H8PADDR_TP3 (1<<H8PADDR_TP3_BIT)
254#define H8PADDR_TP2 (1<<H8PADDR_TP2_BIT)
255#define H8PADDR_TP1 (1<<H8PADDR_TP1_BIT)
256#define H8PADDR_TP0 (1<<H8PADDR_TP0_BIT)
257
258#define H8PADDR_TIOCB2_BIT 7
259#define H8PADDR_TIOCA2_BIT 6
260#define H8PADDR_TIOCB1_BIT 5
261#define H8PADDR_TIOCA1_BIT 4
262#define H8PADDR_TIOCB0_BIT 3
263#define H8PADDR_TIOCA0_BIT 2
264
265#define H8PADDR_TIOCB2 (1<<H8PADDR_TIOCB2_BIT)
266#define H8PADDR_TIOCA2 (1<<H8PADDR_TIOCA2_BIT)
267#define H8PADDR_TIOCB1 (1<<H8PADDR_TIOCB1_BIT)
268#define H8PADDR_TIOCA1 (1<<H8PADDR_TIOCA1_BIT)
269#define H8PADDR_TIOCB0 (1<<H8PADDR_TIOCB0_BIT)
270#define H8PADDR_TIOCA0 (1<<H8PADDR_TIOCA0_BIT)
271
272#define H8PADDR_TEND1_BIT 1
273#define H8PADDR_TEND0_BIT 0
274
275#define H8PADDR_TEND1 (1<<H8PADDR_TEND1_BIT)
276#define H8PADDR_TEND0 (1<<H8PADDR_TEND0_BIT)
277
278#define H8PADDR_A20_BIT 7
279#define H8PADDR_A21_BIT 6
280#define H8PADDR_A22_BIT 5
281#define H8PADDR_A23_BIT 4
282
283#define H8PADDR_A20 (1<<H8PADDR_A20_BIT)
284#define H8PADDR_A21 (1<<H8PADDR_A21_BIT)
285#define H8PADDR_A22 (1<<H8PADDR_A22_BIT)
286#define H8PADDR_A23 (1<<H8PADDR_A23_BIT)
287
288#define H8PADDR_CS4_BIT 6
289#define H8PADDR_CS5_BIT 5
290#define H8PADDR_CS6_BIT 4
291
292#define H8PADDR_CS4 (1<<H8PADDR_CS4_BIT)
293#define H8PADDR_CS5 (1<<H8PADDR_CS5_BIT)
294#define H8PADDR_CS6 (1<<H8PADDR_CS6_BIT)
295
296#define H8PADDR_TCLKD_BIT 3
297#define H8PADDR_TCLKC_BIT 2
298#define H8PADDR_TCLKB_BIT 1
299#define H8PADDR_TCLKA_BIT 0
300
301#define H8PADDR_TCLKD (1<<H8PADDR_TCLKD_BIT)
302#define H8PADDR_TCLKC (1<<H8PADDR_TCLKC_BIT)
303#define H8PADDR_TCLKB (1<<H8PADDR_TCLKB_BIT)
304#define H8PADDR_TCLKA (1<<H8PADDR_TCLKA_BIT)
305
306/* portB (TP/ITU/DMA/AD) */
307
308#define H8PBDDR 0xffffd4
309#define H8PBDR 0xffffd6
310
311#define H8PBDDR_TP15_BIT 7
312#define H8PBDDR_TP14_BIT 6
313#define H8PBDDR_TP13_BIT 5
314#define H8PBDDR_TP12_BIT 4
315#define H8PBDDR_TP11_BIT 3
316#define H8PBDDR_TP10_BIT 2
317#define H8PBDDR_TP9_BIT 1
318#define H8PBDDR_TP8_BIT 0
319
320#define H8PBDDR_TP15 (1<<H8PBDDR_TP15_BIT)
321#define H8PBDDR_TP14 (1<<H8PBDDR_TP14_BIT)
322#define H8PBDDR_TP13 (1<<H8PBDDR_TP13_BIT)
323#define H8PBDDR_TP12 (1<<H8PBDDR_TP12_BIT)
324#define H8PBDDR_TP11 (1<<H8PBDDR_TP11_BIT)
325#define H8PBDDR_TP10 (1<<H8PBDDR_TP10_BIT)
326#define H8PBDDR_TP9 (1<<H8PBDDR_TP9_BIT)
327#define H8PBDDR_TP8 (1<<H8PBDDR_TP8_BIT)
328
329#define H8PBDDR_DREQ1_BIT 7
330#define H8PBDDR_DREQ0_BIT 6
331
332#define H8PBDDR_DREQ1 (1<<H8PBDDR_DREQ1_BIT)
333#define H8PBDDR_DREQ0 (1<<H8PBDDR_DREQ0_BIT)
334
335#define H8PBDDR_TOCXB4_BIT 5
336#define H8PBDDR_TOCXA4_BIT 4
337#define H8PBDDR_TIOCB4_BIT 3
338#define H8PBDDR_TIOCA4_BIT 2
339#define H8PBDDR_TIOCB3_BIT 1
340#define H8PBDDR_TIOCA3_BIT 0
341
342#define H8PBDDR_TOCXB4 (1<<H8PBDDR_TOCXB4_BIT)
343#define H8PBDDR_TOCXA4 (1<<H8PBDDR_TOCXA4_BIT)
344#define H8PBDDR_TIOCB4 (1<<H8PBDDR_TIOCB4_BIT)
345#define H8PBDDR_TIOCA4 (1<<H8PBDDR_TIOCA4_BIT)
346#define H8PBDDR_TIOCB3 (1<<H8PBDDR_TIOCB3_BIT)
347#define H8PBDDR_TIOCA3 (1<<H8PBDDR_TIOCA3_BIT)
348
349#define H8PBDDR_ADTRG_BIT 7
350
351#define H8PBDDR_ADTRG (1<<H8PBDDR_ADTRG_BIT)
352
353#define H8PBDDR_CS7_BIT 6
354
355#define H8PBDDR_CS7 (1<<H8PBDDR_CS7_BIT)
356
357/* Interrupt Contolller */
358
359#define H8SYSCR 0xfffff2
360#define H8IPRA 0xfffff8
361#define H8IPRB 0xfffff9
362
363/* System Control Register */
364
365#define H8SYSCR_SSBY_BIT 7
366#define H8SYSCR_STS2_BIT 6
367#define H8SYSCR_STS1_BIT 5
368#define H8SYSCR_STS0_BIT 4
369#define H8SYSCR_UE_BIT 3
370#define H8SYSCR_NMIEG_BIT 2
371#define H8SYSCR_RAME_BIT 0
372
373#define H8SYSCR_SSBY (1<<(H8SYSCR_SSBY_BIT))
374#define H8SYSCR_STS2 (1<<(H8SYSCR_STS2_BIT))
375#define H8SYSCR_STS1 (1<<(H8SYSCR_STS1_BIT))
376#define H8SYSCR_STS0 (1<<(H8SYSCR_STS0_BIT))
377#define H8SYSCR_UE (1<<(H8SYSCR_UE_BIT))
378#define H8SYSCR_NMIEG (1<<(H8SYSCR_NMIEG_BIT))
379#define H8SYSCR_RAME (1<<(H8SYSCR_RAME_BIT))
380
381/* Interrupt Priority Register A */
382
383#define H8IPR_IRQ0_BIT 7 /* IRQ0 */
384#define H8IPR_IRQ1_BIT 6 /* IRQ1 */
385#define H8IPR_IRQ2_BIT 5 /* IRQ2 */
386#define H8IPR_IRQ3_BIT 5 /* IRQ3 */
387#define H8IPR_IRQ4_BIT 4 /* IRQ4 */
388#define H8IPR_IRQ5_BIT 4 /* IRQ5 */
389#define H8IPR_WDT_BIT 3 /* WDT */
390#define H8IPR_CMI_BIT 3 /* CMI */
391#define H8IPR_ITU0_BIT 2 /* ITU0 */
392#define H8IPR_ITU1_BIT 1 /* ITU1 */
393#define H8IPR_ITU2_BIT 0 /* ITU2 */
394
395#define H8IPR_IRQ0 (1<<(H8IPR_IRQ0_BIT))
396#define H8IPR_IRQ1 (1<<(H8IPR_IRQ1_BIT))
397#define H8IPR_IRQ2 (1<<(H8IPR_IRQ2_BIT))
398#define H8IPR_IRQ3 (1<<(H8IPR_IRQ3_BIT))
399#define H8IPR_IRQ4 (1<<(H8IPR_IRQ4_BIT))
400#define H8IPR_IRQ5 (1<<(H8IPR_IRQ5_BIT))
401#define H8IPR_WDT (1<<(H8IPR_WDT_BIT))
402#define H8IPR_CMI (1<<(H8IPR_CMI_BIT))
403#define H8IPR_ITU0 (1<<(H8IPR_ITU0_BIT))
404#define H8IPR_ITU1 (1<<(H8IPR_ITU1_BIT))
405#define H8IPR_ITU2 (1<<(H8IPR_ITU2_BIT))
406
407/* Interrupt Priority Register B */
408
409#define H8IPR_ITU3_BIT 7 /* ITU3 */
410#define H8IPR_ITU4_BIT 6 /* ITU4 */
411#define H8IPR_DMAC_BIT 5 /* DMAC (CH0,1) */
412#define H8IPR_SCI0_BIT 3 /* SCI0 */
413#define H8IPR_SCI1_BIT 2 /* SCI1 */
414#define H8IPR_AD_BIT 1 /* A/D */
415
416#define H8IPR_ITU3 (1<<(H8IPR_ITU3_BIT))
417#define H8IPR_ITU4 (1<<(H8IPR_ITU4_BIT))
418#define H8IPR_DMAC (1<<(H8IPR_DMAC_BIT))
419#define H8IPR_SCI0 (1<<(H8IPR_SCI0_BIT))
420#define H8IPR_SCI1 (1<<(H8IPR_SCI1_BIT))
421#define H8IPR_AD (1<<(H8IPR_AD_BIT))
422
423/* Bus Release Control Regisger */
424
425#define H8BRCR 0xfffff3
426
427/* Control bit in BRCR */
428
429#define H8BRCR_A23E_BIT 7
430#define H8BRCR_A22E_BIT 6
431#define H8BRCR_A21E_BIT 5
432#define H8BRCR_BRLE_BIT 1
433
434#define H8BRCR_A23E (1<<(H8BRCR_A23E_BIT))
435#define H8BRCR_A22E (1<<(H8BRCR_A22E_BIT))
436#define H8BRCR_A21E (1<<(H8BRCR_A21E_BIT))
437#define H8BRCR_BRLE (1<<(H8BRCR_BRLE_BIT))
438
439/* Integrated Timer Unit (ITU) */
440
441#define H8ITU_TSTR 0xffff60
442#define H8ITU_TSNC 0xffff61
443#define H8ITU_TMDR 0xffff62
444#define H8ITU_TFCR 0xffff63
445#define H8ITU_TOER 0xffff90
446#define H8ITU_TOCR 0xffff91
447
448#define H8ITU0 0xffff64 /* base address */
449#define H8ITU1 0xffff6e
450#define H8ITU2 0xffff78
451#define H8ITU3 0xffff82
452#define H8ITU4 0xffff92
453
454/* Integrated Timer Unit (ITU) */
455
456/* address offset */
457
458#define H8TCR 0
459#define H8TIOR 1
460#define H8TIER 2
461#define H8TSR 3
462#define H8TCNT 4
463#define H8TCNTH 4
464#define H8TCNTL 5
465#define H8GRA 6
466#define H8GRAH 6
467#define H8GRAL 7
468#define H8GRB 8
469#define H8GRBH 8
470#define H8GRBL 9
471#define H8BRA 10
472#define H8BRAH 10
473#define H8BRAL 11
474#define H8BRB 12
475#define H8BRBH 12
476#define H8BRBL 13
477
478/* ITU Timer Start Register (TSTR) */
479
480#define H8TSTR_STR4_BIT 4
481#define H8TSTR_STR3_BIT 3
482#define H8TSTR_STR2_BIT 2
483#define H8TSTR_STR1_BIT 1
484#define H8TSTR_STR0_BIT 0
485
486#define H8TSTR_STR4 (1<<H8TSTR_STR4_BIT)
487#define H8TSTR_STR3 (1<<H8TSTR_STR3_BIT)
488#define H8TSTR_STR2 (1<<H8TSTR_STR2_BIT)
489#define H8TSTR_STR1 (1<<H8TSTR_STR1_BIT)
490#define H8TSTR_STR0 (1<<H8TSTR_STR0_BIT)
491
492/* ITU Timer Control Register (TCR) */
493
494#define H8TCR_CCLR1_BIT 6
495#define H8TCR_CCLR0_BIT 5
496#define H8TCR_CKEG1_BIT 4
497#define H8TCR_CKEG0_BIT 3
498#define H8TCR_TPSC2_BIT 2
499#define H8TCR_TPSC1_BIT 1
500#define H8TCR_TPSC0_BIT 0
501
502#define H8TCR_CCLR1 (1<<H8TCR_CCLR1_BIT)
503#define H8TCR_CCLR0 (1<<H8TCR_CCLR0_BIT)
504#define H8TCR_CKEG1 (1<<H8TCR_CKEG1_BIT)
505#define H8TCR_CKEG0 (1<<H8TCR_CKEG0_BIT)
506#define H8TCR_TPSC2 (1<<H8TCR_TPSC2_BIT)
507#define H8TCR_TPSC1 (1<<H8TCR_TPSC1_BIT)
508#define H8TCR_TPSC0 (1<<H8TCR_TPSC0_BIT)
509
510/* ITU Timer Status Register (TSR) */
511
512#define H8TSR_OVIF_BIT 2
513#define H8TSR_IMIFB_BIT 1
514#define H8TSR_IMIFA_BIT 0
515
516#define H8TSR_OVIF (1<<H8TSR_OVIF_BIT)
517#define H8TSR_IMIFB (1<<H8TSR_IMIFB_BIT)
518#define H8TSR_IMIFA (1<<H8TSR_IMIFA_BIT)
519
520/* ITU Timer Intrrupt Enable Register (TIER) */
521
522#define H8TIER_OVIE_BIT 2
523#define H8TIER_IMIEB_BIT 1
524#define H8TIER_IMIEA_BIT 0
525
526#define H8TIER_OVIE (1<<H8TIER_OVIE_BIT)
527#define H8TIER_IMIEB (1<<H8TIER_IMIEB_BIT)
528#define H8TIER_IMIEA (1<<H8TIER_IMIEA_BIT)
529
530/* ITU Timer I/O Control Register (TIOR) */
531
532#define H8TIOR_IOB2_BIT 6
533#define H8TIOR_IOB1_BIT 5
534#define H8TIOR_IOB0_BIT 4
535#define H8TIOR_IOA2_BIT 2
536#define H8TIOR_IOA1_BIT 1
537#define H8TIOR_IOA0_BIT 0
538
539#define H8TIOR_IOB2 (1<<H8TIOR_IOB2_BIT)
540#define H8TIOR_IOB1 (1<<H8TIOR_IOB1_BIT)
541#define H8TIOR_IOB0 (1<<H8TIOR_IOB0_BIT)
542#define H8TIOR_IOA2 (1<<H8TIOR_IOA2_BIT)
543#define H8TIOR_IOA1 (1<<H8TIOR_IOA1_BIT)
544#define H8TIOR_IOA0 (1<<H8TIOR_IOA0_BIT)
545
546/* Serial Communication Interface (SCI) */
547
548#define H8SCI0 0xffffb0 /* base address */
549#define H8SCI1 0xffffb8
550
551/* address offset */
552
553#define H8SMR 0
554#define H8BRR 1
555#define H8SCR 2
556#define H8TDR 3
557#define H8SSR 4
558#define H8RDR 5
559
560/* SCI Serial Mode Register (SMR) */
561
562#define H8SMR_CA_BIT 7
563#define H8SMR_CHR_BIT 6
564#define H8SMR_PE_BIT 5
565#define H8SMR_OE_BIT 4
566#define H8SMR_STOP_BIT 3
567#define H8SMR_MP_BIT 2
568#define H8SMR_CKS1_BIT 1
569#define H8SMR_CKS0_BIT 0
570
571#define H8SMR_CA (1<<H8SMR_CA_BIT)
572#define H8SMR_CHR (1<<H8SMR_CHR_BIT)
573#define H8SMR_PE (1<<H8SMR_PE_BIT)
574#define H8SMR_OE (1<<H8SMR_OE_BIT)
575#define H8SMR_STOP (1<<H8SMR_STOP_BIT)
576#define H8SMR_MP (1<<H8SMR_MP_BIT)
577#define H8SMR_CKS1 (1<<H8SMR_CKS1_BIT)
578#define H8SMR_CKS0 (1<<H8SMR_CKS0_BIT)
579#define H8SMR_CKS_MASK (H8SMR_CKS1|H8SMR_CKS0)
580
581/* SCI Serial Control Register (SCR) */
582
583#define H8SCR_TIE_BIT 7
584#define H8SCR_RIE_BIT 6
585#define H8SCR_TE_BIT 5
586#define H8SCR_RE_BIT 4
587#define H8SCR_MPIE_BIT 3
588#define H8SCR_TEIE_BIT 2
589#define H8SCR_CKE1_BIT 1
590#define H8SCR_CKE0_BIT 0
591
592#define H8SCR_TIE (1<<H8SCR_TIE_BIT)
593#define H8SCR_RIE (1<<H8SCR_RIE_BIT)
594#define H8SCR_TE (1<<H8SCR_TE_BIT)
595#define H8SCR_RE (1<<H8SCR_RE_BIT)
596#define H8SCR_MPIE (1<<H8SCR_MPIE_BIT)
597#define H8SCR_TEIE (1<<H8SCR_TEIE_BIT)
598#define H8SCR_CKE1 (1<<H8SCR_CKE1_BIT)
599#define H8SCR_CKE0 (1<<H8SCR_CKE0_BIT)
600#define H8SCR_CKE_MASK (H8SCR_CKE1|H8SCR_CKE0)
601#define H8SCR_IE (H8SCR_TIE|H8SCR_RIE|H8SCR_MPIE|H8SCR_TEIE)
602
603/* SCI Serial Status Register (SSR) */
604
605#define H8SSR_TDRE_BIT 7
606#define H8SSR_RDRF_BIT 6
607#define H8SSR_ORER_BIT 5
608#define H8SSR_FER_BIT 4
609#define H8SSR_PER_BIT 3
610#define H8SSR_TEND_BIT 2
611#define H8SSR_MPB_BIT 1
612#define H8SSR_MPBT_BIT 0
613
614#define H8SSR_TDRE (1<<H8SSR_TDRE_BIT)
615#define H8SSR_RDRF (1<<H8SSR_RDRF_BIT)
616#define H8SSR_ORER (1<<H8SSR_ORER_BIT)
617#define H8SSR_FER (1<<H8SSR_FER_BIT)
618#define H8SSR_PER (1<<H8SSR_PER_BIT)
619#define H8SSR_TEND (1<<H8SSR_TEND_BIT)
620#define H8SSR_MPB (1<<H8SSR_MPB_BIT)
621#define H8SSR_MPBT (1<<H8SSR_MPBT_BIT)
622
623/*
624 * 内
625蔵メモリの定義
626 */
627#define H8IN_ROM_BASE 0x000000
628#define H8IN_ROM_SIZE 0x020000
629#define H8IN_RAM_BASE 0xffdf10
630#define H8IN_RAM_SIZE 0x002000
631
632#endif /* _H8_3052F_H_ */
Note: See TracBrowser for help on using the repository browser.