[26] | 1 | /*
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| 2 | * TOPPERS/JSP Kernel
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| 3 | * Toyohashi Open Platform for Embedded Real-Time Systems/
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| 4 | * Just Standard Profile Kernel
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| 5 | *
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| 6 | * Copyright (C) 2000-2004 by Embedded and Real-Time Systems Laboratory
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| 7 | * Toyohashi Univ. of Technology, JAPAN
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| 8 | * Copyright (C) 2001-2007 by Industrial Technology Institute,
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| 9 | * Miyagi Prefectural Government, JAPAN
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| 10 | * Copyright (C) 2001-2004 by Dep. of Computer Science and Engineering
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| 11 | * Tomakomai National College of Technology, JAPAN
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| 12 | *
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| 13 | * ä¸è¨èä½æ¨©è
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| 14 | ã¯ï¼ä»¥ä¸ã® (1)ã(4) ã®æ¡ä»¶ãï¼Free Software Foundation
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| 15 | * ã«ãã£ã¦å
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| 16 | ¬è¡¨ããã¦ãã GNU General Public License ã® Version 2 ã«è¨
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| 17 | * è¿°ããã¦ããæ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§ã¢ï¼æ¬ã½ããã¦ã§ã¢
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| 18 | * ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ã使ç¨ã»è¤è£½ã»æ¹å¤ã»åé
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| 19 | å¸ï¼ä»¥ä¸ï¼
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| 20 | * å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
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| 21 | * (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
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| 22 | * 権表示ï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
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| 23 | * ã¹ã³ã¼ãä¸ã«å«ã¾ãã¦ãããã¨ï¼
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| 24 | * (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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| 25 | * ç¨ã§ããå½¢ã§åé
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| 26 | å¸ããå ´åã«ã¯ï¼åé
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| 27 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨
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| 28 | * è
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| 29 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
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| 30 | * ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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| 31 | * (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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| 32 | * ç¨ã§ããªãå½¢ã§åé
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| 33 | å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
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| 34 | * ã¨ï¼
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| 35 | * (a) åé
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| 36 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨è
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| 37 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
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| 38 | * ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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| 39 | * (b) åé
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| 40 | å¸ã®å½¢æ
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| 41 | ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSããã¸ã§ã¯ãã«
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| 42 | * å ±åãããã¨ï¼
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| 43 | * (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
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| 44 | * 害ãããï¼ä¸è¨èä½æ¨©è
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| 45 | ããã³TOPPERSããã¸ã§ã¯ããå
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| 46 | 責ãããã¨ï¼
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| 47 | *
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| 48 | * æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
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| 49 | ã
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| 50 | * ãã³TOPPERSããã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ãã®é©ç¨å¯è½æ§ã
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| 51 | * å«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´
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| 52 | * æ¥çã¾ãã¯éæ¥çã«çãããããªãæ害ã«é¢ãã¦ãï¼ãã®è²¬ä»»ãè² ããªãï¼
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| 53 | *
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| 54 | * @(#) $Id: h8_3048f.h,v 1.7 2007/03/23 07:58:33 honda Exp $
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| 55 | */
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| 56 |
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| 57 | #ifndef _H8_3048F_H_
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| 58 | #define _H8_3048F_H_
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| 59 |
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| 60 | /*
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| 61 | * H8/3048Fç¨å®ç¾©
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| 62 | * H8/3048F-ONEã¨å
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| 63 | ±ç¨ã§ããã
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| 64 | * 両è
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| 65 | ã®éãã¯ããã©ãã·ã¥ROMé¢é£ã®å¶å¾¡ã¬ã¸ã¹ã¿ç¾¤ã®æ±ãã§ãããã
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| 66 | * ãã®ãã¡ã¤ã«ã«ã¯ãã©ãã·ã¥ROMé¢é£ã®å¶å¾¡ã¬ã¸ã¹ã¿ç¾¤ã¯å®ç¾©ãã¦ããªã
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| 67 | * ï¼å®è¡ä¸ã«ãã©ãã·ã¥ROMãæ¸ãæãã使ãæ¹ã¯æ³å®ãã¦ããªãï¼
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| 68 | *
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| 69 | * intåã16ãããã®ãããã¢ãã¬ã¹å¤ã«ã¯ãã¹ã¦Lãä»å ãã¦ããã
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| 70 | */
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| 71 |
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| 72 | /* Interrupt numbers */
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| 73 |
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| 74 | #define IRQ_NMI 7u /* NMI */
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| 75 |
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| 76 | #define IRQ_EXT0 12u /* IRQ0 */
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| 77 | #define IRQ_EXT1 13u /* IRQ1 */
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| 78 | #define IRQ_EXT2 14u /* IRQ2 */
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| 79 | #define IRQ_EXT3 15u /* IRQ3 */
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| 80 | #define IRQ_EXT4 16u /* IRQ4 */
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| 81 | #define IRQ_EXT5 17u /* IRQ5 */
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| 82 |
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| 83 | #define IRQ_WOVI 20u /* Watch Doc Timer */
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| 84 |
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| 85 | #define IRQ_CMI 21u /* Compare Match */
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| 86 |
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| 87 | #define IRQ_IMIA0 24u /* ITU0 IMIA0 */
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| 88 | #define IRQ_IMIB0 25u /* ITU0 IMIB0 */
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| 89 | #define IRQ_OVI0 26u /* ITU0 OVI0 */
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| 90 |
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| 91 | #define IRQ_IMIA1 28u /* ITU1 IMIA1 */
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| 92 | #define IRQ_IMIB1 29u /* ITU1 IMIB1 */
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| 93 | #define IRQ_OVI1 30u /* ITU1 OVI1 */
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| 94 |
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| 95 | #define IRQ_IMIA2 32u /* ITU2 IMIA2 */
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| 96 | #define IRQ_IMIB2 33u /* ITU2 IMIB2 */
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| 97 | #define IRQ_OVI2 34u /* ITU2 OVI2 */
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| 98 |
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| 99 | #define IRQ_IMIA3 36u /* ITU3 IMIA3 */
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| 100 | #define IRQ_IMIB3 37u /* ITU3 IMIB3 */
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| 101 | #define IRQ_OVI3 38u /* ITU3 OVI3 */
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| 102 |
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| 103 | #define IRQ_IMIA4 40u /* ITU4 IMIA4 */
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| 104 | #define IRQ_IMIB4 41u /* ITU4 IMIB4 */
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| 105 | #define IRQ_OVI4 42u /* ITU4 OVI4 */
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| 106 |
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| 107 | #define IRQ_DEND0A 44u /* DMAC */
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| 108 | #define IRQ_DEND0B 45u /* DMAC */
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| 109 | #define IRQ_DEND1A 46u /* DMAC */
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| 110 | #define IRQ_DEND1B 47u /* DMAC */
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| 111 |
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| 112 | #define IRQ_ERI0 52u /* SCI0 ERI */
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| 113 | #define IRQ_RXI0 53u /* SCI0 RXI */
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| 114 | #define IRQ_TXI0 54u /* SCI0 TXI */
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| 115 | #define IRQ_TEI0 55u /* SCI0 TEI */
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| 116 |
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| 117 | #define IRQ_ERI1 56u /* SCI1 ERI */
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| 118 | #define IRQ_RXI1 57u /* SCI1 RXI */
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| 119 | #define IRQ_TXI1 58u /* SCI1 TXI */
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| 120 | #define IRQ_TEI1 59u /* SCI1 TEI */
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| 121 |
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| 122 | #define IRQ_ADI 60u /* A/D */
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| 123 |
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| 124 | /* register address */
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| 125 |
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| 126 | /* I/O ports */
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| 127 |
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| 128 | /* port1: A0 - A7 */
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| 129 |
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| 130 | #define H8P1DDR 0xffffc0ul
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| 131 | #define H8P1DR 0xffffc2ul
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| 132 |
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| 133 | /* port2: A8 - A15 */
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| 134 |
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| 135 | #define H8P2DDR 0xffffc1ul
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| 136 | #define H8P2DR 0xffffc3ul
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| 137 | #define H8P2PCR 0xffffd8ul
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| 138 |
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| 139 | /* port3: D8 - D15 */
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| 140 |
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| 141 | #define H8P3DDR 0xffffc4ul
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| 142 | #define H8P3DR 0xffffc6ul
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| 143 |
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| 144 | /* port4: D0 - D7 */
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| 145 |
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| 146 | #define H8P4DDR 0xffffc5ul
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| 147 | #define H8P4DR 0xffffc7ul
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| 148 | #define H8P4PCR 0xffffdaul
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| 149 |
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| 150 | /* port5: A16 - A19 */
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| 151 |
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| 152 | #define H8P5DDR 0xffffc8ul
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| 153 | #define H8P5DR 0xffffcaul
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| 154 | #define H8P5PCR 0xffffdbul
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| 155 |
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| 156 | #define H8P5DDR_A19_BIT 3u
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| 157 | #define H8P5DDR_A18_BIT 2u
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| 158 | #define H8P5DDR_A17_BIT 1u
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| 159 | #define H8P5DDR_A16_BIT 0u
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| 160 |
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| 161 | #define H8P5DDR_A19 (1u<<H8P5DDR_A19_BIT)
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| 162 | #define H8P5DDR_A18 (1u<<H8P5DDR_A18_BIT)
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| 163 | #define H8P5DDR_A17 (1u<<H8P5DDR_A17_BIT)
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| 164 | #define H8P5DDR_A16 (1u<<H8P5DDR_A16_BIT)
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| 165 |
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| 166 | /* port6 */
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| 167 |
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| 168 | #define H8P6DDR 0xffffc9ul
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| 169 | #define H8P6DR 0xffffcbul
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| 170 |
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| 171 | #define H8P6DDR_HWR_BIT 6u
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| 172 | #define H8P6DDR_LWR_BIT 5u
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| 173 | #define H8P6DDR_RD_BIT 4u
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| 174 | #define H8P6DDR_AS_BIT 3u
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| 175 | #define H8P6DDR_BACK_BIT 2u
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| 176 | #define H8P6DDR_BREQ_BIT 1u
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| 177 | #define H8P6DDR_WAIT_BIT 0u
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| 178 |
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| 179 | #define H8P6DDR_HWR (1u<<H8P6DDR_HWR_BIT)
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| 180 | #define H8P6DDR_LWR (1u<<H8P6DDR_LWR_BIT)
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| 181 | #define H8P6DDR_RD (1u<<H8P6DDR_RD_BIT)
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| 182 | #define H8P6DDR_AS (1u<<H8P6DDR_AS_BIT)
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| 183 | #define H8P6DDR_BACK (1u<<H8P6DDR_BACK_BIT)
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| 184 | #define H8P6DDR_BREQ (1u<<H8P6DDR_BREQ_BIT)
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| 185 | #define H8P6DDR_WAIT (1u<<H8P6DDR_WAIT_BIT)
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| 186 |
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| 187 | /* port7 */
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| 188 |
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| 189 | #define H8P7DR 0xffffceul
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| 190 |
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| 191 | /* port8 */
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| 192 |
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| 193 | #define H8P8DDR 0xffffcdul
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| 194 | #define H8P8DR 0xffffcful
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| 195 |
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| 196 | #define H8P8DDR_CS0_BIT 4u
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| 197 | #define H8P8DDR_CS1_BIT 3u
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| 198 | #define H8P8DDR_CS2_BIT 2u
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| 199 | #define H8P8DDR_CS3_BIT 1u
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| 200 | #define H8P8DDR_RFSH_BIT 0u
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| 201 |
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| 202 | #define H8P8DDR_CS0 (1u<<H8P8DDR_CS0_BIT)
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| 203 | #define H8P8DDR_CS1 (1u<<H8P8DDR_CS1_BIT)
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| 204 | #define H8P8DDR_CS2 (1u<<H8P8DDR_CS2_BIT)
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| 205 | #define H8P8DDR_CS3 (1u<<H8P8DDR_CS3_BIT)
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| 206 | #define H8P8DDR_RFSH (1u<<H8P8DDR_RFSH_BIT)
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| 207 |
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| 208 | #define H8P8DDR_IRQ3_BIT 3u
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| 209 | #define H8P8DDR_IRQ2_BIT 2u
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| 210 | #define H8P8DDR_IRQ1_BIT 1u
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| 211 | #define H8P8DDR_IRQ0_BIT 0u
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| 212 |
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| 213 | #define H8P8DDR_IRQ3 (1u<<H8P8DDR_IRQ3_BIT)
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| 214 | #define H8P8DDR_IRQ2 (1u<<H8P8DDR_IRQ2_BIT)
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| 215 | #define H8P8DDR_IRQ1 (1u<<H8P8DDR_IRQ1_BIT)
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| 216 | #define H8P8DDR_IRQ0 (1u<<H8P8DDR_IRQ0_BIT)
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| 217 |
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| 218 | /* port9 (SCI) */
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| 219 |
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| 220 | #define H8P9DDR 0xffffd0ul
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| 221 | #define H8P9DR 0xffffd2ul
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| 222 |
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| 223 | #define H8P9DDR_SCK1_BIT 5u
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| 224 | #define H8P9DDR_SCK0_BIT 4u
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| 225 | #define H8P9DDR_RXD1_BIT 3u
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| 226 | #define H8P9DDR_RXD0_BIT 2u
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| 227 | #define H8P9DDR_TXD1_BIT 1u
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| 228 | #define H8P9DDR_TXD0_BIT 0u
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| 229 |
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| 230 | #define H8P9DDR_SCK1 (1u<<H8P9DDR_SCK1_BIT)
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| 231 | #define H8P9DDR_SCK0 (1u<<H8P9DDR_SCK0_BIT)
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| 232 | #define H8P9DDR_RXD1 (1u<<H8P9DDR_RXD1_BIT)
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| 233 | #define H8P9DDR_RXD0 (1u<<H8P9DDR_RXD0_BIT)
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| 234 | #define H8P9DDR_TXD1 (1u<<H8P9DDR_TXD1_BIT)
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| 235 | #define H8P9DDR_TXD0 (1u<<H8P9DDR_TXD0_BIT)
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| 236 |
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| 237 | #define H8P9DDR_IRQ5_BIT 5u
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| 238 | #define H8P9DDR_IRQ4_BIT 4u
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| 239 |
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| 240 | #define H8P9DDR_IRQ5 (1u<<H8P9DDR_IRQ5_BIT)
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| 241 | #define H8P9DDR_IRQ4 (1u<<H8P9DDR_IRQ4_BIT)
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| 242 |
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| 243 | /* portA (TPC/ITU/DMA) */
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| 244 |
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| 245 | #define H8PADDR 0xffffd1ul
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| 246 | #define H8PADR 0xffffd3ul
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| 247 |
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| 248 | #define H8PADDR_TP7_BIT 7u
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| 249 | #define H8PADDR_TP6_BIT 6u
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| 250 | #define H8PADDR_TP5_BIT 5u
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| 251 | #define H8PADDR_TP4_BIT 4u
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| 252 | #define H8PADDR_TP3_BIT 3u
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| 253 | #define H8PADDR_TP2_BIT 2u
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| 254 | #define H8PADDR_TP1_BIT 1u
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| 255 | #define H8PADDR_TP0_BIT 0u
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| 256 |
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| 257 | #define H8PADDR_TP7 (1u<<H8PADDR_TP7_BIT)
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| 258 | #define H8PADDR_TP6 (1u<<H8PADDR_TP6_BIT)
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| 259 | #define H8PADDR_TP5 (1u<<H8PADDR_TP5_BIT)
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| 260 | #define H8PADDR_TP4 (1u<<H8PADDR_TP4_BIT)
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| 261 | #define H8PADDR_TP3 (1u<<H8PADDR_TP3_BIT)
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| 262 | #define H8PADDR_TP2 (1u<<H8PADDR_TP2_BIT)
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| 263 | #define H8PADDR_TP1 (1u<<H8PADDR_TP1_BIT)
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| 264 | #define H8PADDR_TP0 (1u<<H8PADDR_TP0_BIT)
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| 265 |
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| 266 | #define H8PADDR_TIOCB2_BIT 7u
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| 267 | #define H8PADDR_TIOCA2_BIT 6u
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| 268 | #define H8PADDR_TIOCB1_BIT 5u
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| 269 | #define H8PADDR_TIOCA1_BIT 4u
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| 270 | #define H8PADDR_TIOCB0_BIT 3u
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| 271 | #define H8PADDR_TIOCA0_BIT 2u
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| 272 |
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| 273 | #define H8PADDR_TIOCB2 (1u<<H8PADDR_TIOCB2_BIT)
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| 274 | #define H8PADDR_TIOCA2 (1u<<H8PADDR_TIOCA2_BIT)
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| 275 | #define H8PADDR_TIOCB1 (1u<<H8PADDR_TIOCB1_BIT)
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| 276 | #define H8PADDR_TIOCA1 (1u<<H8PADDR_TIOCA1_BIT)
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| 277 | #define H8PADDR_TIOCB0 (1u<<H8PADDR_TIOCB0_BIT)
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| 278 | #define H8PADDR_TIOCA0 (1u<<H8PADDR_TIOCA0_BIT)
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| 279 |
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| 280 | #define H8PADDR_TEND1_BIT 1u
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| 281 | #define H8PADDR_TEND0_BIT 0u
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| 282 |
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| 283 | #define H8PADDR_TEND1 (1u<<H8PADDR_TEND1_BIT)
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| 284 | #define H8PADDR_TEND0 (1u<<H8PADDR_TEND0_BIT)
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| 285 |
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| 286 | #define H8PADDR_A20_BIT 7u
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| 287 | #define H8PADDR_A21_BIT 6u
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| 288 | #define H8PADDR_A22_BIT 5u
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| 289 | #define H8PADDR_A23_BIT 4u
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| 290 |
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| 291 | #define H8PADDR_A20 (1u<<H8PADDR_A20_BIT)
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| 292 | #define H8PADDR_A21 (1u<<H8PADDR_A21_BIT)
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| 293 | #define H8PADDR_A22 (1u<<H8PADDR_A22_BIT)
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| 294 | #define H8PADDR_A23 (1u<<H8PADDR_A23_BIT)
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| 295 |
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| 296 | #define H8PADDR_CS4_BIT 6u
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| 297 | #define H8PADDR_CS5_BIT 5u
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| 298 | #define H8PADDR_CS6_BIT 4u
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| 299 |
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| 300 | #define H8PADDR_CS4 (1u<<H8PADDR_CS4_BIT)
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| 301 | #define H8PADDR_CS5 (1u<<H8PADDR_CS5_BIT)
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| 302 | #define H8PADDR_CS6 (1u<<H8PADDR_CS6_BIT)
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| 303 |
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| 304 | #define H8PADDR_TCLKD_BIT 3u
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| 305 | #define H8PADDR_TCLKC_BIT 2u
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| 306 | #define H8PADDR_TCLKB_BIT 1u
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| 307 | #define H8PADDR_TCLKA_BIT 0u
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| 308 |
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| 309 | #define H8PADDR_TCLKD (1u<<H8PADDR_TCLKD_BIT)
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| 310 | #define H8PADDR_TCLKC (1u<<H8PADDR_TCLKC_BIT)
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| 311 | #define H8PADDR_TCLKB (1u<<H8PADDR_TCLKB_BIT)
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| 312 | #define H8PADDR_TCLKA (1u<<H8PADDR_TCLKA_BIT)
|
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| 313 |
|
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| 314 | /* portB (TP/ITU/DMA/AD) */
|
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| 315 |
|
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| 316 | #define H8PBDDR 0xffffd4ul
|
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| 317 | #define H8PBDR 0xffffd6ul
|
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| 318 |
|
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| 319 | #define H8PBDDR_TP15_BIT 7u
|
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| 320 | #define H8PBDDR_TP14_BIT 6u
|
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| 321 | #define H8PBDDR_TP13_BIT 5u
|
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| 322 | #define H8PBDDR_TP12_BIT 4u
|
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| 323 | #define H8PBDDR_TP11_BIT 3u
|
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| 324 | #define H8PBDDR_TP10_BIT 2u
|
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| 325 | #define H8PBDDR_TP9_BIT 1u
|
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| 326 | #define H8PBDDR_TP8_BIT 0u
|
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| 327 |
|
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| 328 | #define H8PBDDR_TP15 (1u<<H8PBDDR_TP15_BIT)
|
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| 329 | #define H8PBDDR_TP14 (1u<<H8PBDDR_TP14_BIT)
|
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| 330 | #define H8PBDDR_TP13 (1u<<H8PBDDR_TP13_BIT)
|
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| 331 | #define H8PBDDR_TP12 (1u<<H8PBDDR_TP12_BIT)
|
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| 332 | #define H8PBDDR_TP11 (1u<<H8PBDDR_TP11_BIT)
|
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| 333 | #define H8PBDDR_TP10 (1u<<H8PBDDR_TP10_BIT)
|
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| 334 | #define H8PBDDR_TP9 (1u<<H8PBDDR_TP9_BIT)
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| 335 | #define H8PBDDR_TP8 (1u<<H8PBDDR_TP8_BIT)
|
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| 336 |
|
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| 337 | #define H8PBDDR_DREQ1_BIT 7u
|
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| 338 | #define H8PBDDR_DREQ0_BIT 6u
|
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| 339 |
|
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| 340 | #define H8PBDDR_DREQ1 (1u<<H8PBDDR_DREQ1_BIT)
|
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| 341 | #define H8PBDDR_DREQ0 (1u<<H8PBDDR_DREQ0_BIT)
|
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| 342 |
|
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| 343 | #define H8PBDDR_TOCXB4_BIT 5u
|
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| 344 | #define H8PBDDR_TOCXA4_BIT 4u
|
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| 345 | #define H8PBDDR_TIOCB4_BIT 3u
|
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| 346 | #define H8PBDDR_TIOCA4_BIT 2u
|
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| 347 | #define H8PBDDR_TIOCB3_BIT 1u
|
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| 348 | #define H8PBDDR_TIOCA3_BIT 0u
|
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| 349 |
|
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| 350 | #define H8PBDDR_TOCXB4 (1u<<H8PBDDR_TOCXB4_BIT)
|
---|
| 351 | #define H8PBDDR_TOCXA4 (1u<<H8PBDDR_TOCXA4_BIT)
|
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| 352 | #define H8PBDDR_TIOCB4 (1u<<H8PBDDR_TIOCB4_BIT)
|
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| 353 | #define H8PBDDR_TIOCA4 (1u<<H8PBDDR_TIOCA4_BIT)
|
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| 354 | #define H8PBDDR_TIOCB3 (1u<<H8PBDDR_TIOCB3_BIT)
|
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| 355 | #define H8PBDDR_TIOCA3 (1u<<H8PBDDR_TIOCA3_BIT)
|
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| 356 |
|
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| 357 | #define H8PBDDR_ADTRG_BIT 7u
|
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| 358 |
|
---|
| 359 | #define H8PBDDR_ADTRG (1u<<H8PBDDR_ADTRG_BIT)
|
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| 360 |
|
---|
| 361 | #define H8PBDDR_CS7_BIT 6u
|
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| 362 |
|
---|
| 363 | #define H8PBDDR_CS7 (1u<<H8PBDDR_CS7_BIT)
|
---|
| 364 |
|
---|
| 365 | /* Interrupt Contolller */
|
---|
| 366 |
|
---|
| 367 | #define H8SYSCR 0xfffff2ul
|
---|
| 368 | #define H8IPRA 0xfffff8ul
|
---|
| 369 | #define H8IPRB 0xfffff9ul
|
---|
| 370 |
|
---|
| 371 | /* System Control Register */
|
---|
| 372 |
|
---|
| 373 | #define H8SYSCR_SSBY_BIT 7u
|
---|
| 374 | #define H8SYSCR_STS2_BIT 6u
|
---|
| 375 | #define H8SYSCR_STS1_BIT 5u
|
---|
| 376 | #define H8SYSCR_STS0_BIT 4u
|
---|
| 377 | #define H8SYSCR_UE_BIT 3u
|
---|
| 378 | #define H8SYSCR_NMIEG_BIT 2u
|
---|
| 379 | #define H8SYSCR_RAME_BIT 0u
|
---|
| 380 |
|
---|
| 381 | #define H8SYSCR_SSBY (1u<<(H8SYSCR_SSBY_BIT))
|
---|
| 382 | #define H8SYSCR_STS2 (1u<<(H8SYSCR_STS2_BIT))
|
---|
| 383 | #define H8SYSCR_STS1 (1u<<(H8SYSCR_STS1_BIT))
|
---|
| 384 | #define H8SYSCR_STS0 (1u<<(H8SYSCR_STS0_BIT))
|
---|
| 385 | #define H8SYSCR_UE (1u<<(H8SYSCR_UE_BIT))
|
---|
| 386 | #define H8SYSCR_NMIEG (1u<<(H8SYSCR_NMIEG_BIT))
|
---|
| 387 | #define H8SYSCR_RAME (1u<<(H8SYSCR_RAME_BIT))
|
---|
| 388 |
|
---|
| 389 | /* Interrupt Priority Register A */
|
---|
| 390 |
|
---|
| 391 | #define H8IPR_IRQ0_BIT 7u /* IRQ0 */
|
---|
| 392 | #define H8IPR_IRQ1_BIT 6u /* IRQ1 */
|
---|
| 393 | #define H8IPR_IRQ2_BIT 5u /* IRQ2 */
|
---|
| 394 | #define H8IPR_IRQ3_BIT 5u /* IRQ3 */
|
---|
| 395 | #define H8IPR_IRQ4_BIT 4u /* IRQ4 */
|
---|
| 396 | #define H8IPR_IRQ5_BIT 4u /* IRQ5 */
|
---|
| 397 | #define H8IPR_WDT_BIT 3u /* WDT */
|
---|
| 398 | #define H8IPR_CMI_BIT 3u /* CMI */
|
---|
| 399 | #define H8IPR_ITU0_BIT 2u /* ITU0 */
|
---|
| 400 | #define H8IPR_ITU1_BIT 1u /* ITU1 */
|
---|
| 401 | #define H8IPR_ITU2_BIT 0u /* ITU2 */
|
---|
| 402 |
|
---|
| 403 | #define H8IPR_IRQ0 (1u<<(H8IPR_IRQ0_BIT))
|
---|
| 404 | #define H8IPR_IRQ1 (1u<<(H8IPR_IRQ1_BIT))
|
---|
| 405 | #define H8IPR_IRQ2 (1u<<(H8IPR_IRQ2_BIT))
|
---|
| 406 | #define H8IPR_IRQ3 (1u<<(H8IPR_IRQ3_BIT))
|
---|
| 407 | #define H8IPR_IRQ4 (1u<<(H8IPR_IRQ4_BIT))
|
---|
| 408 | #define H8IPR_IRQ5 (1u<<(H8IPR_IRQ5_BIT))
|
---|
| 409 | #define H8IPR_WDT (1u<<(H8IPR_WDT_BIT))
|
---|
| 410 | #define H8IPR_CMI (1u<<(H8IPR_CMI_BIT))
|
---|
| 411 | #define H8IPR_ITU0 (1u<<(H8IPR_ITU0_BIT))
|
---|
| 412 | #define H8IPR_ITU1 (1u<<(H8IPR_ITU1_BIT))
|
---|
| 413 | #define H8IPR_ITU2 (1u<<(H8IPR_ITU2_BIT))
|
---|
| 414 |
|
---|
| 415 | /* Interrupt Priority Register B */
|
---|
| 416 |
|
---|
| 417 | #define H8IPR_ITU3_BIT 7u /* ITU3 */
|
---|
| 418 | #define H8IPR_ITU4_BIT 6u /* ITU4 */
|
---|
| 419 | #define H8IPR_DMAC_BIT 5u /* DMAC (CH0,1) */
|
---|
| 420 | #define H8IPR_SCI0_BIT 3u /* SCI0 */
|
---|
| 421 | #define H8IPR_SCI1_BIT 2u /* SCI1 */
|
---|
| 422 | #define H8IPR_AD_BIT 1u /* A/D */
|
---|
| 423 |
|
---|
| 424 | #define H8IPR_ITU3 (1u<<(H8IPR_ITU3_BIT))
|
---|
| 425 | #define H8IPR_ITU4 (1u<<(H8IPR_ITU4_BIT))
|
---|
| 426 | #define H8IPR_DMAC (1u<<(H8IPR_DMAC_BIT))
|
---|
| 427 | #define H8IPR_SCI0 (1u<<(H8IPR_SCI0_BIT))
|
---|
| 428 | #define H8IPR_SCI1 (1u<<(H8IPR_SCI1_BIT))
|
---|
| 429 | #define H8IPR_AD (1u<<(H8IPR_AD_BIT))
|
---|
| 430 |
|
---|
| 431 | /* Bus Release Control Regisger */
|
---|
| 432 |
|
---|
| 433 | #define H8BRCR 0xfffff3ul
|
---|
| 434 |
|
---|
| 435 | /* Control bit in BRCR */
|
---|
| 436 |
|
---|
| 437 | #define H8BRCR_A23E_BIT 7u
|
---|
| 438 | #define H8BRCR_A22E_BIT 6u
|
---|
| 439 | #define H8BRCR_A21E_BIT 5u
|
---|
| 440 | #define H8BRCR_BRLE_BIT 1u
|
---|
| 441 |
|
---|
| 442 | #define H8BRCR_A23E (1u<<(H8BRCR_A23E_BIT))
|
---|
| 443 | #define H8BRCR_A22E (1u<<(H8BRCR_A22E_BIT))
|
---|
| 444 | #define H8BRCR_A21E (1u<<(H8BRCR_A21E_BIT))
|
---|
| 445 | #define H8BRCR_BRLE (1u<<(H8BRCR_BRLE_BIT))
|
---|
| 446 |
|
---|
| 447 | /* Integrated Timer Unit (ITU) */
|
---|
| 448 |
|
---|
| 449 | #define H8ITU_TSTR 0xffff60ul
|
---|
| 450 | #define H8ITU_TSNC 0xffff61ul
|
---|
| 451 | #define H8ITU_TMDR 0xffff62ul
|
---|
| 452 | #define H8ITU_TFCR 0xffff63ul
|
---|
| 453 | #define H8ITU_TOER 0xffff90ul
|
---|
| 454 | #define H8ITU_TOCR 0xffff91ul
|
---|
| 455 |
|
---|
| 456 | #define H8ITU0 0xffff64ul /* base address */
|
---|
| 457 | #define H8ITU1 0xffff6eul
|
---|
| 458 | #define H8ITU2 0xffff78ul
|
---|
| 459 | #define H8ITU3 0xffff82ul
|
---|
| 460 | #define H8ITU4 0xffff92ul
|
---|
| 461 |
|
---|
| 462 | /* Integrated Timer Unit (ITU) */
|
---|
| 463 |
|
---|
| 464 | /* address offset */
|
---|
| 465 |
|
---|
| 466 | #define H8TCR 0ul
|
---|
| 467 | #define H8TIOR 1ul
|
---|
| 468 | #define H8TIER 2ul
|
---|
| 469 | #define H8TSR 3ul
|
---|
| 470 | #define H8TCNT 4ul
|
---|
| 471 | #define H8TCNTH 4ul
|
---|
| 472 | #define H8TCNTL 5ul
|
---|
| 473 | #define H8GRA 6ul
|
---|
| 474 | #define H8GRAH 6ul
|
---|
| 475 | #define H8GRAL 7ul
|
---|
| 476 | #define H8GRB 8ul
|
---|
| 477 | #define H8GRBH 8ul
|
---|
| 478 | #define H8GRBL 9ul
|
---|
| 479 | #define H8BRA 10ul
|
---|
| 480 | #define H8BRAH 10ul
|
---|
| 481 | #define H8BRAL 11ul
|
---|
| 482 | #define H8BRB 12ul
|
---|
| 483 | #define H8BRBH 12ul
|
---|
| 484 |
|
---|
| 485 | /* ITU Timer Start Register (TSTR) */
|
---|
| 486 |
|
---|
| 487 | #define H8TSTR_STR4_BIT 4u
|
---|
| 488 | #define H8TSTR_STR3_BIT 3u
|
---|
| 489 | #define H8TSTR_STR2_BIT 2u
|
---|
| 490 | #define H8TSTR_STR1_BIT 1u
|
---|
| 491 | #define H8TSTR_STR0_BIT 0u
|
---|
| 492 |
|
---|
| 493 | #define H8TSTR_STR4 (1u<<H8TSTR_STR4_BIT)
|
---|
| 494 | #define H8TSTR_STR3 (1u<<H8TSTR_STR3_BIT)
|
---|
| 495 | #define H8TSTR_STR2 (1u<<H8TSTR_STR2_BIT)
|
---|
| 496 | #define H8TSTR_STR1 (1u<<H8TSTR_STR1_BIT)
|
---|
| 497 | #define H8TSTR_STR0 (1u<<H8TSTR_STR0_BIT)
|
---|
| 498 |
|
---|
| 499 | /* ITU Timer Control Register (TCR) */
|
---|
| 500 |
|
---|
| 501 | #define H8TCR_CCLR1_BIT 6u
|
---|
| 502 | #define H8TCR_CCLR0_BIT 5u
|
---|
| 503 | #define H8TCR_CKEG1_BIT 4u
|
---|
| 504 | #define H8TCR_CKEG0_BIT 3u
|
---|
| 505 | #define H8TCR_TPSC2_BIT 2u
|
---|
| 506 | #define H8TCR_TPSC1_BIT 1u
|
---|
| 507 | #define H8TCR_TPSC0_BIT 0u
|
---|
| 508 |
|
---|
| 509 | #define H8TCR_CCLR1 (1u<<H8TCR_CCLR1_BIT)
|
---|
| 510 | #define H8TCR_CCLR0 (1u<<H8TCR_CCLR0_BIT)
|
---|
| 511 | #define H8TCR_CKEG1 (1u<<H8TCR_CKEG1_BIT)
|
---|
| 512 | #define H8TCR_CKEG0 (1u<<H8TCR_CKEG0_BIT)
|
---|
| 513 | #define H8TCR_TPSC2 (1u<<H8TCR_TPSC2_BIT)
|
---|
| 514 | #define H8TCR_TPSC1 (1u<<H8TCR_TPSC1_BIT)
|
---|
| 515 | #define H8TCR_TPSC0 (1u<<H8TCR_TPSC0_BIT)
|
---|
| 516 |
|
---|
| 517 | /* ITU Timer Status Register (TSR) */
|
---|
| 518 |
|
---|
| 519 | #define H8TSR_OVIF_BIT 2u
|
---|
| 520 | #define H8TSR_IMIFB_BIT 1u
|
---|
| 521 | #define H8TSR_IMIFA_BIT 0u
|
---|
| 522 |
|
---|
| 523 | #define H8TSR_OVIF (1u<<H8TSR_OVIF_BIT)
|
---|
| 524 | #define H8TSR_IMIFB (1u<<H8TSR_IMIFB_BIT)
|
---|
| 525 | #define H8TSR_IMIFA (1u<<H8TSR_IMIFA_BIT)
|
---|
| 526 |
|
---|
| 527 | /* ITU Timer Intrrupt Enable Register (TIER) */
|
---|
| 528 |
|
---|
| 529 | #define H8TIER_OVIE_BIT 2u
|
---|
| 530 | #define H8TIER_IMIEB_BIT 1u
|
---|
| 531 | #define H8TIER_IMIEA_BIT 0u
|
---|
| 532 |
|
---|
| 533 | #define H8TIER_OVIE (1u<<H8TIER_OVIE_BIT)
|
---|
| 534 | #define H8TIER_IMIEB (1u<<H8TIER_IMIEB_BIT)
|
---|
| 535 | #define H8TIER_IMIEA (1u<<H8TIER_IMIEA_BIT)
|
---|
| 536 |
|
---|
| 537 | /* ITU Timer I/O Control Register (TIOR) */
|
---|
| 538 |
|
---|
| 539 | #define H8TIOR_IOB2_BIT 6u
|
---|
| 540 | #define H8TIOR_IOB1_BIT 5u
|
---|
| 541 | #define H8TIOR_IOB0_BIT 4u
|
---|
| 542 | #define H8TIOR_IOA2_BIT 2u
|
---|
| 543 | #define H8TIOR_IOA1_BIT 1u
|
---|
| 544 | #define H8TIOR_IOA0_BIT 0u
|
---|
| 545 |
|
---|
| 546 | #define H8TIOR_IOB2 (1u<<H8TIOR_IOB2_BIT)
|
---|
| 547 | #define H8TIOR_IOB1 (1u<<H8TIOR_IOB1_BIT)
|
---|
| 548 | #define H8TIOR_IOB0 (1u<<H8TIOR_IOB0_BIT)
|
---|
| 549 | #define H8TIOR_IOA2 (1u<<H8TIOR_IOA2_BIT)
|
---|
| 550 | #define H8TIOR_IOA1 (1u<<H8TIOR_IOA1_BIT)
|
---|
| 551 | #define H8TIOR_IOA0 (1u<<H8TIOR_IOA0_BIT)
|
---|
| 552 |
|
---|
| 553 | /* Serial Communication Interface (SCI) */
|
---|
| 554 |
|
---|
| 555 | #define H8SCI0 0xffffb0ul /* base address */
|
---|
| 556 | #define H8SCI1 0xffffb8ul
|
---|
| 557 |
|
---|
| 558 | /* address offset */
|
---|
| 559 |
|
---|
| 560 | #define H8SMR 0ul
|
---|
| 561 | #define H8BRR 1ul
|
---|
| 562 | #define H8SCR 2ul
|
---|
| 563 | #define H8TDR 3ul
|
---|
| 564 | #define H8SSR 4ul
|
---|
| 565 | #define H8RDR 5ul
|
---|
| 566 |
|
---|
| 567 | /* SCI Serial Mode Register (SMR) */
|
---|
| 568 |
|
---|
| 569 | #define H8SMR_CA_BIT 7u
|
---|
| 570 | #define H8SMR_CHR_BIT 6u
|
---|
| 571 | #define H8SMR_PE_BIT 5u
|
---|
| 572 | #define H8SMR_OE_BIT 4u
|
---|
| 573 | #define H8SMR_STOP_BIT 3u
|
---|
| 574 | #define H8SMR_MP_BIT 2u
|
---|
| 575 | #define H8SMR_CKS1_BIT 1u
|
---|
| 576 | #define H8SMR_CKS0_BIT 0u
|
---|
| 577 |
|
---|
| 578 | #define H8SMR_CA (1u<<H8SMR_CA_BIT)
|
---|
| 579 | #define H8SMR_CHR (1u<<H8SMR_CHR_BIT)
|
---|
| 580 | #define H8SMR_PE (1u<<H8SMR_PE_BIT)
|
---|
| 581 | #define H8SMR_OE (1u<<H8SMR_OE_BIT)
|
---|
| 582 | #define H8SMR_STOP (1u<<H8SMR_STOP_BIT)
|
---|
| 583 | #define H8SMR_MP (1u<<H8SMR_MP_BIT)
|
---|
| 584 | #define H8SMR_CKS1 (1u<<H8SMR_CKS1_BIT)
|
---|
| 585 | #define H8SMR_CKS0 (1u<<H8SMR_CKS0_BIT)
|
---|
| 586 | #define H8SMR_CKS_MASK (H8SMR_CKS1|H8SMR_CKS0)
|
---|
| 587 |
|
---|
| 588 | /* SCI Serial Control Register (SCR) */
|
---|
| 589 |
|
---|
| 590 | #define H8SCR_TIE_BIT 7u
|
---|
| 591 | #define H8SCR_RIE_BIT 6u
|
---|
| 592 | #define H8SCR_TE_BIT 5u
|
---|
| 593 | #define H8SCR_RE_BIT 4u
|
---|
| 594 | #define H8SCR_MPIE_BIT 3u
|
---|
| 595 | #define H8SCR_TEIE_BIT 2u
|
---|
| 596 | #define H8SCR_CKE1_BIT 1u
|
---|
| 597 | #define H8SCR_CKE0_BIT 0u
|
---|
| 598 |
|
---|
| 599 | #define H8SCR_TIE (1u<<H8SCR_TIE_BIT)
|
---|
| 600 | #define H8SCR_RIE (1u<<H8SCR_RIE_BIT)
|
---|
| 601 | #define H8SCR_TE (1u<<H8SCR_TE_BIT)
|
---|
| 602 | #define H8SCR_RE (1u<<H8SCR_RE_BIT)
|
---|
| 603 | #define H8SCR_MPIE (1u<<H8SCR_MPIE_BIT)
|
---|
| 604 | #define H8SCR_TEIE (1u<<H8SCR_TEIE_BIT)
|
---|
| 605 | #define H8SCR_CKE1 (1u<<H8SCR_CKE1_BIT)
|
---|
| 606 | #define H8SCR_CKE0 (1u<<H8SCR_CKE0_BIT)
|
---|
| 607 | #define H8SCR_CKE_MASK (H8SCR_CKE1|H8SCR_CKE0)
|
---|
| 608 | #define H8SCR_IE (H8SCR_TIE|H8SCR_RIE|H8SCR_MPIE|H8SCR_TEIE)
|
---|
| 609 |
|
---|
| 610 | /* SCI Serial Status Register (SSR) */
|
---|
| 611 |
|
---|
| 612 | #define H8SSR_TDRE_BIT 7u
|
---|
| 613 | #define H8SSR_RDRF_BIT 6u
|
---|
| 614 | #define H8SSR_ORER_BIT 5u
|
---|
| 615 | #define H8SSR_FER_BIT 4u
|
---|
| 616 | #define H8SSR_PER_BIT 3u
|
---|
| 617 | #define H8SSR_TEND_BIT 2u
|
---|
| 618 | #define H8SSR_MPB_BIT 1u
|
---|
| 619 | #define H8SSR_MPBT_BIT 0u
|
---|
| 620 |
|
---|
| 621 | #define H8SSR_TDRE (1u<<H8SSR_TDRE_BIT)
|
---|
| 622 | #define H8SSR_RDRF (1u<<H8SSR_RDRF_BIT)
|
---|
| 623 | #define H8SSR_ORER (1u<<H8SSR_ORER_BIT)
|
---|
| 624 | #define H8SSR_FER (1u<<H8SSR_FER_BIT)
|
---|
| 625 | #define H8SSR_PER (1u<<H8SSR_PER_BIT)
|
---|
| 626 | #define H8SSR_TEND (1u<<H8SSR_TEND_BIT)
|
---|
| 627 | #define H8SSR_MPB (1u<<H8SSR_MPB_BIT)
|
---|
| 628 | #define H8SSR_MPBT (1u<<H8SSR_MPBT_BIT)
|
---|
| 629 |
|
---|
| 630 | /*
|
---|
| 631 | * å
|
---|
| 632 | èµã¡ã¢ãªã®å®ç¾©
|
---|
| 633 | */
|
---|
| 634 |
|
---|
| 635 | #define H8IN_ROM_BASE 0x000000ul
|
---|
| 636 | #define H8IN_ROM_SIZE 0x020000ul
|
---|
| 637 | #define H8IN_RAM_BASE 0xffef10ul
|
---|
| 638 | #define H8IN_RAM_SIZE 0x001000ul
|
---|
| 639 |
|
---|
| 640 | #endif /* _H8_3048F_H_ */
|
---|