[26] | 1 | /*
|
---|
| 2 | * TOPPERS/JSP Kernel
|
---|
| 3 | * Toyohashi Open Platform for Embedded Real-Time Systems/
|
---|
| 4 | * Just Standard Profile Kernel
|
---|
| 5 | *
|
---|
| 6 | * Copyright (C) 2000-2003 by Embedded and Real-Time Systems Laboratory
|
---|
| 7 | * Toyohashi Univ. of Technology, JAPAN
|
---|
| 8 | * Copyright (C) 2000-2003 by Industrial Technology Institute,
|
---|
| 9 | * Miyagi Prefectural Government, JAPAN
|
---|
| 10 | * Copyright (C) 2002-2004 by Hokkaido Industrial Research Institute, JAPAN
|
---|
| 11 | * Copyright (C) 2007 by KURUSUGAWA Electronics Industry Inc, JAPAN
|
---|
| 12 | * Copyright (C) 2008 by Takahisa Yokota
|
---|
| 13 | *
|
---|
| 14 | * ä¸è¨èä½æ¨©è
|
---|
| 15 | ã¯ï¼ä»¥ä¸ã® (1)ã(4) ã®æ¡ä»¶ãï¼Free Software Foundation
|
---|
| 16 | * ã«ãã£ã¦å
|
---|
| 17 | ¬è¡¨ããã¦ãã GNU General Public License ã® Version 2 ã«è¨
|
---|
| 18 | * è¿°ããã¦ããæ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§ã¢ï¼æ¬ã½ããã¦ã§ã¢
|
---|
| 19 | * ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ã使ç¨ã»è¤è£½ã»æ¹å¤ã»åé
|
---|
| 20 | å¸ï¼ä»¥ä¸ï¼
|
---|
| 21 | * å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
|
---|
| 22 | * (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
|
---|
| 23 | * 権表示ï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
|
---|
| 24 | * ã¹ã³ã¼ãä¸ã«å«ã¾ãã¦ãããã¨ï¼
|
---|
| 25 | * (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
|
---|
| 26 | * ç¨ã§ããå½¢ã§åé
|
---|
| 27 | å¸ããå ´åã«ã¯ï¼åé
|
---|
| 28 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨
|
---|
| 29 | * è
|
---|
| 30 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
|
---|
| 31 | * ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
|
---|
| 32 | * (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
|
---|
| 33 | * ç¨ã§ããªãå½¢ã§åé
|
---|
| 34 | å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
|
---|
| 35 | * ã¨ï¼
|
---|
| 36 | * (a) åé
|
---|
| 37 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨è
|
---|
| 38 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
|
---|
| 39 | * ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
|
---|
| 40 | * (b) åé
|
---|
| 41 | å¸ã®å½¢æ
|
---|
| 42 | ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSããã¸ã§ã¯ãã«
|
---|
| 43 | * å ±åãããã¨ï¼
|
---|
| 44 | * (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
|
---|
| 45 | * 害ãããï¼ä¸è¨èä½æ¨©è
|
---|
| 46 | ããã³TOPPERSããã¸ã§ã¯ããå
|
---|
| 47 | 責ãããã¨ï¼
|
---|
| 48 | *
|
---|
| 49 | * æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
|
---|
| 50 | ã
|
---|
| 51 | * ãã³TOPPERSããã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ãã®é©ç¨å¯è½æ§ã
|
---|
| 52 | * å«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´
|
---|
| 53 | * æ¥çã¾ãã¯éæ¥çã«çãããããªãæ害ã«é¢ãã¦ãï¼ãã®è²¬ä»»ãè² ããªãï¼
|
---|
| 54 | *
|
---|
| 55 | * @(#) $Id: mcfuart.c,v 1.3 2005/07/06 00:45:07 honda Exp $
|
---|
| 56 | */
|
---|
| 57 |
|
---|
| 58 | /*
|
---|
| 59 | * COLDFIREå
|
---|
| 60 | èµUARTç¨ ç°¡æãã©ã¤ã
|
---|
| 61 | */
|
---|
| 62 |
|
---|
| 63 | #include <s_services.h>
|
---|
| 64 | #include "mcfuart.h"
|
---|
| 65 |
|
---|
| 66 | /*
|
---|
| 67 | * ã·ãªã¢ã«I/Oãã¼ã管çãããã¯ã®å®ç¾©
|
---|
| 68 | */
|
---|
| 69 | /* å
|
---|
| 70 | ¥åºåãã¼ãã®è¨å®ã¯sys_config.c */
|
---|
| 71 | /* å²è¾¼ã¿ãã¯ã¿çªå·ã®è¨å®ã¯hw_serial.h */
|
---|
| 72 | /* 管çãããã¯ã®è¨å®ã¯mcfuart.c */
|
---|
| 73 |
|
---|
| 74 | #ifndef GDB_STUB
|
---|
| 75 |
|
---|
| 76 | const SIOPINIB siopinib_table[TNUM_PORT] = {
|
---|
| 77 | {IPSBAR + 0x00000200, BRR9600, 0x0, 0x27}, /* UART0 */
|
---|
| 78 | #if TNUM_PORT >= 2
|
---|
| 79 | {IPSBAR + 0x00000240, BRR9600, 0x0, 0x27}, /* UART1 */
|
---|
| 80 | #endif /* TNUM_PORT >= 2 */
|
---|
| 81 | };
|
---|
| 82 |
|
---|
| 83 | #else /* GDB_STUB */
|
---|
| 84 |
|
---|
| 85 | const SIOPINIB siopinib_table[TNUM_PORT] = {
|
---|
| 86 | {IPSBAR + 0x00000200, BRR9600, 0x0, 6}, /* SCIF2 */
|
---|
| 87 | };
|
---|
| 88 |
|
---|
| 89 | #endif /* GDB_STUB */
|
---|
| 90 |
|
---|
| 91 | #if defined(TTM)
|
---|
| 92 | /*
|
---|
| 93 | * ã·ãªã¢ã«I/Oãã¼ã管çãããã¯ã®å®ç¾©
|
---|
| 94 | * ã2chãµãã¼ãã«æ¡å¼µããå ´åã¯åæå¤ç¨ã®ãã¼ã¿ãå«ãã
|
---|
| 95 | */
|
---|
| 96 | struct sio_port_control_block
|
---|
| 97 | {
|
---|
| 98 | VP_INT exinf; /* æ¡å¼µæ
|
---|
| 99 | å ± */
|
---|
| 100 | BOOL openflag; /* ãªã¼ãã³æ¸ã¿ãã©ã° */
|
---|
| 101 | };
|
---|
| 102 | #endif
|
---|
| 103 | /*
|
---|
| 104 | * ã·ãªã¢ã«I/Oãã¼ã管çãããã¯ã®ã¨ãªã¢
|
---|
| 105 | */
|
---|
| 106 | static SIOPCB siopcb_table[TNUM_PORT];
|
---|
| 107 |
|
---|
| 108 | /*
|
---|
| 109 | * ã·ãªã¢ã«I/Oãã¼ãIDãã管çãããã¯ãåãåºãããã®ãã¯ã
|
---|
| 110 | */
|
---|
| 111 | #define INDEX_SIOP(siopid) ((UINT)((siopid) - 1))
|
---|
| 112 | #define get_siopcb(siopid) (&(siopcb_table[INDEX_SIOP(siopid)]))
|
---|
| 113 |
|
---|
| 114 | /*
|
---|
| 115 | * æåãåä¿¡ã§ãããï¼
|
---|
| 116 | */
|
---|
| 117 | Inline BOOL
|
---|
| 118 | mcfuart_getready (SIOPCB * siopcb)
|
---|
| 119 | {
|
---|
| 120 | return (sil_reb_mem((VB *) (siopcb->siopinib->reg_base + MCF_UART_USR)) & MCF_UART_USR_RXRDY);
|
---|
| 121 | }
|
---|
| 122 |
|
---|
| 123 | /*
|
---|
| 124 | * æåãéä¿¡ã§ãããï¼
|
---|
| 125 | */
|
---|
| 126 | Inline BOOL
|
---|
| 127 | mcfuart_putready (SIOPCB * siopcb)
|
---|
| 128 | {
|
---|
| 129 | /* Wait until space is available in the FIFO */
|
---|
| 130 | return (sil_reb_mem((VB*)(siopcb->siopinib->reg_base + MCF_UART_USR)) & MCF_UART_USR_TXRDY);
|
---|
| 131 | }
|
---|
| 132 |
|
---|
| 133 | /*
|
---|
| 134 | * åä¿¡ããæåã®ååºã
|
---|
| 135 | */
|
---|
| 136 | Inline char
|
---|
| 137 | mcfuart_getchar (SIOPCB * siopcb)
|
---|
| 138 | {
|
---|
| 139 | VB data;
|
---|
| 140 | data = sil_reb_mem ((VB*)(siopcb->siopinib->reg_base + MCF_UART_URB));
|
---|
| 141 | return data;
|
---|
| 142 | }
|
---|
| 143 |
|
---|
| 144 | /*
|
---|
| 145 | * éä¿¡ããæåã®æ¸è¾¼ã¿
|
---|
| 146 | */
|
---|
| 147 | Inline void
|
---|
| 148 | mcfuart_putchar (SIOPCB * siopcb, char c)
|
---|
| 149 | {
|
---|
| 150 | /* Send the character */
|
---|
| 151 | sil_wrb_mem ((VB*)(siopcb->siopinib->reg_base + MCF_UART_UTB), c);
|
---|
| 152 | }
|
---|
| 153 |
|
---|
| 154 | /*
|
---|
| 155 | * SIOãã©ã¤ãã®åæåã«ã¼ãã³
|
---|
| 156 | */
|
---|
| 157 | void
|
---|
| 158 | mcfuart_initialize ()
|
---|
| 159 | {
|
---|
| 160 | SIOPCB *siopcb;
|
---|
| 161 | UINT i;
|
---|
| 162 | /*
|
---|
| 163 | * ã·ã«ã¢ã«I/Oãã¼ã管çãããã¯ã®åæå
|
---|
| 164 | */
|
---|
| 165 | for (siopcb = siopcb_table, i = 0; i < TNUM_PORT; siopcb++, i++) {
|
---|
| 166 | siopcb->openflag = FALSE;
|
---|
| 167 | siopcb->siopinib = (&siopinib_table[i]);
|
---|
| 168 | }
|
---|
| 169 | }
|
---|
| 170 |
|
---|
| 171 | /*
|
---|
| 172 | * ãªã¼ãã³ãã¦ãããã¼ãããããï¼
|
---|
| 173 | */
|
---|
| 174 | BOOL
|
---|
| 175 | mcfuart_openflag (ID siopid)
|
---|
| 176 | {
|
---|
| 177 | return (siopcb_table[siopid -1].openflag);
|
---|
| 178 | }
|
---|
| 179 |
|
---|
| 180 | /*
|
---|
| 181 | * ã·ãªã¢ã«I/Oãã¼ãã®ãªã¼ãã³
|
---|
| 182 | */
|
---|
| 183 | SIOPCB *
|
---|
| 184 | mcfuart_opn_por (ID siopid, VP_INT exinf)
|
---|
| 185 | {
|
---|
| 186 | volatile int i;
|
---|
| 187 | SIOPCB *siopcb = get_siopcb(siopid);
|
---|
| 188 | // éä¿¡åæ¢
|
---|
| 189 | sil_wrb_mem ((VB *) (siopcb->siopinib->reg_base + MCF_UART_UCR), (VB) (MCF_UART_UCR_MISC_RR));
|
---|
| 190 | sil_wrb_mem ((VB *) (siopcb->siopinib->reg_base + MCF_UART_UCR), (VB) (MCF_UART_UCR_MISC_RT));
|
---|
| 191 | sil_wrb_mem ((VB *) (siopcb->siopinib->reg_base + MCF_UART_UCR), (VB) (MCF_UART_UCR_MISC_RRC));
|
---|
| 192 |
|
---|
| 193 | sil_wrb_mem ((VB *) (siopcb->siopinib->reg_base + MCF_UART_UMR1), 0x93);
|
---|
| 194 | sil_wrb_mem ((VB *) (siopcb->siopinib->reg_base + MCF_UART_UMR2), 0x07);
|
---|
| 195 | sil_wrb_mem ((VB *) (siopcb->siopinib->reg_base + MCF_UART_UCSR), 0xDD);
|
---|
| 196 |
|
---|
| 197 | sil_wrb_mem ((VB *) (siopcb->siopinib->reg_base + MCF_UART_UBG1), (VB) (siopcb->siopinib->brr >> 8));
|
---|
| 198 | sil_wrb_mem ((VB *) (siopcb->siopinib->reg_base + MCF_UART_UBG2), (VB) (siopcb->siopinib->brr & 0x00ff));
|
---|
| 199 |
|
---|
| 200 | /* å²è¾¼ã¿è¨±å¯ */
|
---|
| 201 | siopcb->imr = (VB)MCF_UART_UIMR_RXRDY;
|
---|
| 202 | sil_wrb_mem ((VB *) (siopcb->siopinib->reg_base + MCF_UART_UIMR), (VB) (siopcb->imr));
|
---|
| 203 |
|
---|
| 204 | /* éåä¿¡è¨±å¯ */
|
---|
| 205 | sil_wrb_mem ((VB *) (siopcb->siopinib->reg_base + MCF_UART_UCR), (VB) (MCF_UART_UCR_TC_EN | MCF_UART_UCR_RC_EN));
|
---|
| 206 |
|
---|
| 207 | siopcb->exinf = exinf;
|
---|
| 208 | siopcb->openflag = TRUE;
|
---|
| 209 | if (siopcb->siopinib->reg_base == (IPSBAR + 0x00000200)) {
|
---|
| 210 | sil_wrw_mem ((VW*)MCF_INTC_IMRL(MCF_INTC0), sil_rew_mem((VW*)MCF_INTC_IMRL(MCF_INTC0)) & (~(1 << (TBIT_GP0))));
|
---|
| 211 | } else if (siopcb->siopinib->reg_base == (IPSBAR + 0x00000240)) {
|
---|
| 212 | sil_wrw_mem ((VW*)MCF_INTC_IMRL(MCF_INTC0), sil_rew_mem((VW*)MCF_INTC_IMRL(MCF_INTC0)) & (~(1 << (TBIT_GP1))));
|
---|
| 213 | }
|
---|
| 214 | for (i = 0; i < 1000;i++);
|
---|
| 215 | return (siopcb);
|
---|
| 216 | }
|
---|
| 217 |
|
---|
| 218 | /*
|
---|
| 219 | * ã·ãªã¢ã«I/Oãã¼ãã®ã¯ãã¼ãº
|
---|
| 220 | */
|
---|
| 221 | void
|
---|
| 222 | mcfuart_cls_por (SIOPCB * siopcb)
|
---|
| 223 | {
|
---|
| 224 | /* éåä¿¡ç¦æ¢ */
|
---|
| 225 | sil_wrb_mem ((VB *) (siopcb->siopinib->reg_base + MCF_UART_UCSR),
|
---|
| 226 | (VB) (MCF_UART_UCR_TC_DIS | MCF_UART_UCR_RC_DIS));
|
---|
| 227 | /* å²è¾¼ã¿ç¦æ¢ */
|
---|
| 228 | sil_wrb_mem ((VB *) (siopcb->siopinib->reg_base + MCF_UART_UIMR), 0);
|
---|
| 229 | if (siopcb->siopinib->reg_base == (IPSBAR + 0x00000200)) {
|
---|
| 230 | sil_wrw_mem (MCF_INTC_IMRL(MCF_INTC0), sil_rew_mem(MCF_INTC_IMRL(MCF_INTC0)) | (1 << TBIT_GP0));
|
---|
| 231 | } else if (siopcb->siopinib->reg_base == (IPSBAR + 0x00000240)) {
|
---|
| 232 | sil_wrw_mem (MCF_INTC_IMRL(MCF_INTC0), sil_rew_mem(MCF_INTC_IMRL(MCF_INTC0)) | (1 << TBIT_GP1));
|
---|
| 233 | }
|
---|
| 234 | siopcb->openflag = FALSE;
|
---|
| 235 | }
|
---|
| 236 |
|
---|
| 237 | /*
|
---|
| 238 | * ã·ãªã¢ã«I/Oãã¼ãã¸ã®æåéä¿¡
|
---|
| 239 | */
|
---|
| 240 | BOOL
|
---|
| 241 | mcfuart_snd_chr (SIOPCB * siopcb, char c)
|
---|
| 242 | {
|
---|
| 243 | if (mcfuart_putready (siopcb)) {
|
---|
| 244 | mcfuart_putchar (siopcb, c);
|
---|
| 245 | return (TRUE);
|
---|
| 246 | }
|
---|
| 247 | return (FALSE);
|
---|
| 248 | }
|
---|
| 249 |
|
---|
| 250 | /*
|
---|
| 251 | * ã·ãªã¢ã«I/Oãã¼ãããã®æååä¿¡
|
---|
| 252 | */
|
---|
| 253 | INT
|
---|
| 254 | mcfuart_rcv_chr (SIOPCB * siopcb)
|
---|
| 255 | {
|
---|
| 256 | if (mcfuart_getready (siopcb)) {
|
---|
| 257 | return ((INT) (UB) mcfuart_getchar (siopcb));
|
---|
| 258 | }
|
---|
| 259 | return (-1);
|
---|
| 260 | }
|
---|
| 261 |
|
---|
| 262 | /*
|
---|
| 263 | * ã·ãªã¢ã«I/Oãã¼ãããã®ã³ã¼ã«ããã¯ã®è¨±å¯
|
---|
| 264 | */
|
---|
| 265 | void
|
---|
| 266 | mcfuart_ena_cbr (SIOPCB * siopcb, UINT cbrtn)
|
---|
| 267 | {
|
---|
| 268 | switch (cbrtn) {
|
---|
| 269 | case SIO_ERDY_SND: /* éä¿¡å²ãè¾¼ã¿è¦æ±ãè¨±å¯ */
|
---|
| 270 | siopcb->imr |= MCF_UART_UIMR_TXRDY;
|
---|
| 271 | break;
|
---|
| 272 | case SIO_ERDY_RCV: /* åä¿¡å²ãè¾¼ã¿è¦æ±ãè¨±å¯ */
|
---|
| 273 | siopcb->imr |= MCF_UART_UIMR_RXRDY;
|
---|
| 274 | break;
|
---|
| 275 | }
|
---|
| 276 | sil_wrb_mem ((VB *) (siopcb->siopinib->reg_base + MCF_UART_UIMR), siopcb->imr);
|
---|
| 277 | }
|
---|
| 278 |
|
---|
| 279 | /*
|
---|
| 280 | * ã·ãªã¢ã«I/Oãã¼ãããã®ã³ã¼ã«ããã¯ã®ç¦æ¢
|
---|
| 281 | */
|
---|
| 282 | void
|
---|
| 283 | mcfuart_dis_cbr (SIOPCB * siopcb, UINT cbrtn)
|
---|
| 284 | {
|
---|
| 285 | switch (cbrtn) {
|
---|
| 286 | case SIO_ERDY_SND: /* éä¿¡å²ãè¾¼ã¿è¦æ±ãç¦æ¢ */
|
---|
| 287 | siopcb->imr &= ~MCF_UART_UIMR_TXRDY;
|
---|
| 288 | break;
|
---|
| 289 | case SIO_ERDY_RCV: /* åä¿¡å²ãè¾¼ã¿è¦æ±ãç¦æ¢ */
|
---|
| 290 | siopcb->imr &= ~MCF_UART_UIMR_RXRDY;
|
---|
| 291 | break;
|
---|
| 292 | }
|
---|
| 293 | sil_wrb_mem ((VB *) (siopcb->siopinib->reg_base + MCF_UART_UIMR), siopcb->imr);
|
---|
| 294 | }
|
---|
| 295 |
|
---|
| 296 | /*
|
---|
| 297 | * ãã¼ãªã³ã°ã«ããæåã®éä¿¡
|
---|
| 298 | */
|
---|
| 299 | void
|
---|
| 300 | mcfuart_putc_pol (ID portid, char c)
|
---|
| 301 | {
|
---|
| 302 | while (!mcfuart_putready (&siopcb_table[portid - 1]));
|
---|
| 303 | mcfuart_putchar (&siopcb_table[portid - 1], c);
|
---|
| 304 | }
|
---|
| 305 |
|
---|
| 306 | /*
|
---|
| 307 | * ã·ãªã¢ã«I/Oãã¼ãã«å¯¾ããéä¿¡å²è¾¼ã¿å¦ç
|
---|
| 308 | */
|
---|
| 309 | Inline void
|
---|
| 310 | mcfuart_isr_siop (SIOPCB * siopcb)
|
---|
| 311 | {
|
---|
| 312 | VB uisr = sil_reb_mem ((VB *) (siopcb->siopinib->reg_base + MCF_UART_UISR));
|
---|
| 313 | uisr &= siopcb->imr;
|
---|
| 314 | if ((uisr & MCF_UART_UISR_TXRDY) && mcfuart_putready (siopcb)) {
|
---|
| 315 | /*
|
---|
| 316 | * éä¿¡éç¥ã³ã¼ã«ããã¯ã«ã¼ãã³ãå¼ã³åºãï¼
|
---|
| 317 | */
|
---|
| 318 | mcfuart_ierdy_snd (siopcb->exinf);
|
---|
| 319 | }
|
---|
| 320 | else if ((uisr & MCF_UART_UISR_RXRDY) && mcfuart_getready (siopcb)) {
|
---|
| 321 | /*
|
---|
| 322 | * éä¿¡éç¥ã³ã¼ã«ããã¯ã«ã¼ãã³ãå¼ã³åºãï¼
|
---|
| 323 | */
|
---|
| 324 | mcfuart_ierdy_rcv (siopcb->exinf);
|
---|
| 325 | }
|
---|
| 326 | }
|
---|
| 327 |
|
---|
| 328 | /* å²ãè¾¼ã¿æ¤åº */
|
---|
| 329 | void
|
---|
| 330 | mcfuart_isr (void)
|
---|
| 331 | {
|
---|
| 332 | if (siopcb_table[0].openflag) {
|
---|
| 333 | mcfuart_isr_siop (get_siopcb (1));
|
---|
| 334 | }
|
---|
| 335 | }
|
---|
| 336 |
|
---|
| 337 | #if TNUM_PORT >= 2
|
---|
| 338 | /* å²ãè¾¼ã¿æ¤åº */
|
---|
| 339 | void
|
---|
| 340 | mcfuart_isr2 (void)
|
---|
| 341 | {
|
---|
| 342 |
|
---|
| 343 | if (siopcb_table[1].openflag) {
|
---|
| 344 | mcfuart_isr_siop (get_siopcb (2));
|
---|
| 345 | }
|
---|
| 346 | }
|
---|
| 347 | #endif
|
---|