[26] | 1 | /*
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| 2 | * TOPPERS/JSP Kernel
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| 3 | * Toyohashi Open Platform for Embedded Real-Time Systems/
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| 4 | * Just Standard Profile Kernel
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| 5 | *
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| 6 | * Copyright (C) 2000-2003 by Embedded and Real-Time Systems Laboratory
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| 7 | * Toyohashi Univ. of Technology, JAPAN
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| 8 | * Copyright (C) 2007 by KURUSUGAWA Electronics Industry Inc, JAPAN
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| 9 | * Copyright (C) 2008 by Takahisa Yokota
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| 10 | *
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| 11 | * ä¸è¨èä½æ¨©è
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| 12 | ã¯ï¼ä»¥ä¸ã® (1)ã(4) ã®æ¡ä»¶ãï¼Free Software Foundation
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| 13 | * ã«ãã£ã¦å
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| 14 | ¬è¡¨ããã¦ãã GNU General Public License ã® Version 2 ã«è¨
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| 15 | * è¿°ããã¦ããæ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§ã¢ï¼æ¬ã½ããã¦ã§ã¢
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| 16 | * ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ã使ç¨ã»è¤è£½ã»æ¹å¤ã»åé
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| 17 | å¸ï¼ä»¥ä¸ï¼
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| 18 | * å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
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| 19 | * (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
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| 20 | * 権表示ï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
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| 21 | * ã¹ã³ã¼ãä¸ã«å«ã¾ãã¦ãããã¨ï¼
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| 22 | * (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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| 23 | * ç¨ã§ããå½¢ã§åé
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| 24 | å¸ããå ´åã«ã¯ï¼åé
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| 25 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨
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| 26 | * è
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| 27 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
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| 28 | * ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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| 29 | * (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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| 30 | * ç¨ã§ããªãå½¢ã§åé
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| 31 | å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
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| 32 | * ã¨ï¼
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| 33 | * (a) åé
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| 34 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨è
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| 35 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
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| 36 | * ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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| 37 | * (b) åé
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| 38 | å¸ã®å½¢æ
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| 39 | ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSããã¸ã§ã¯ãã«
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| 40 | * å ±åãããã¨ï¼
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| 41 | * (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
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| 42 | * 害ãããï¼ä¸è¨èä½æ¨©è
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| 43 | ããã³TOPPERSããã¸ã§ã¯ããå
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| 44 | 責ãããã¨ï¼
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| 45 | *
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| 46 | * æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
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| 47 | ã
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| 48 | * ãã³TOPPERSããã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ãã®é©ç¨å¯è½æ§ã
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| 49 | * å«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´
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| 50 | * æ¥çã¾ãã¯éæ¥çã«çãããããªãæ害ã«é¢ãã¦ãï¼ãã®è²¬ä»»ãè² ããªãï¼
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| 51 | *
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| 52 | * @(#) $Id: m52235.h,v 1.8 2003/06/18 12:40:08 hiro Exp $
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| 53 | */
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| 54 |
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| 55 | /*
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| 56 | * M52235 CPUãã¼ãã®ãã¼ãã¦ã§ã¢è³æºã®å®ç¾©
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| 57 | */
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| 58 |
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| 59 | #ifndef _M52235_H_
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| 60 | #define _M52235_H_
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| 61 |
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| 62 | #include <sil.h>
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| 63 |
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| 64 | #define MCF_UART0 77
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| 65 | #define MCF_UART1 78
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| 66 | #define MCF_UART2 79
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| 67 | #define MCF_PIT0 119
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| 68 |
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| 69 | #define TBIT_GP0 (13)
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| 70 | #define TBIT_GP1 (14)
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| 71 |
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| 72 | #define TBIT_GP2 (15)
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| 73 |
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| 74 | #define TBIT_TT0 (55 - 32)
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| 75 | #define TBIT_TT1 (56 - 32)
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| 76 |
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| 77 | #define REF_CLK_MHZ (25)
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| 78 | #define SYS_CLK_MHZ (60)
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| 79 | #define REF_CLK_KHZ (REF_CLK_MHZ * 1000)
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| 80 | #define SYS_CLK_KHZ (SYS_CLK_MHZ * 1000)
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| 81 | #define SYSTEM_CLOCK SYS_CLK_MHZ
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| 82 |
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| 83 | #define IPSBAR (0x40000000)
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| 84 |
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| 85 | #define MCF_SCM_RAMBAR (IPSBAR + 0x000008)
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| 86 | #define MCF_SCM_RAMBAR_BDE (0x00000200)
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| 87 | #define MCF_SCM_RAMBAR_BA(x) ((x)&0xFFFF0000)
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| 88 |
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| 89 | #define MCF_CLK_SYNCR (IPSBAR + 0x00120000)
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| 90 | #define MCF_CLK_SYNSR (IPSBAR + 0x00120002)
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| 91 |
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| 92 | #define MCF_CLK_SYNCR_PLLEN (0x0001)
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| 93 | #define MCF_CLK_SYNCR_PLLMODE (0x0002)
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| 94 | #define MCF_CLK_SYNCR_CLKSRC (0x0004)
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| 95 | #define MCF_CLK_SYNCR_FWKUP (0x0020)
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| 96 | #define MCF_CLK_SYNCR_DISCLK (0x0040)
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| 97 | #define MCF_CLK_SYNCR_LOCEN (0x0080)
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| 98 | #define MCF_CLK_SYNCR_RFD(x) (((x)&0x0007)<<8)
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| 99 | #define MCF_CLK_SYNCR_LOCRE (0x0800)
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| 100 | #define MCF_CLK_SYNCR_MFD(x) (((x)&0x0007)<<12)
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| 101 | #define MCF_CLK_SYNCR_LOLRE (0x8000)
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| 102 |
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| 103 | #define MCF_CLK_SYNSR_LOCS (0x04)
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| 104 | #define MCF_CLK_SYNSR_LOCK (0x08)
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| 105 | #define MCF_CLK_SYNSR_LOCKS (0x10)
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| 106 | #define MCF_CLK_SYNSR_CRYOSC (0x20)
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| 107 | #define MCF_CLK_SYNSR_OCOSC (0x40)
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| 108 | #define MCF_CLK_SYNSR_EXTOSC (0x80)
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| 109 |
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| 110 | #define MCF_CLK_LPCR_LPD(x) (((x)&0x0F)<<0)
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| 111 |
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| 112 | #define MCF_CLK_CCHR_PFD(x) (((x)&0x07)<<0)
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| 113 |
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| 114 | #define MCF_CLK_RTCDR_RTCDF(x) (((x)&0xFFFFFFFF)<<0)
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| 115 |
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| 116 | /*
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| 117 | * PLL min/max specifications
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| 118 | */
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| 119 | #define MAX_FVCO 60000 /* KHz */
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| 120 | #define MAX_FSYS 60000 /* KHz */
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| 121 | #define MAX_FREF 48000 /* KHz */
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| 122 | #define MIN_FREF 1000 /* KHz */
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| 123 | #define MAX_MFD 18 /* Multiplier (not encoded) */
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| 124 | #define MIN_MFD 4 /* Multiplier (not encoded) */
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| 125 | #define MAX_RFD 128 /* Divider (not encoded) */
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| 126 | #define MIN_RFD 1 /* Divider (not encoded) */
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| 127 |
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| 128 | /*
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| 129 | * Low Power Divider specifications
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| 130 | */
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| 131 | #define MIN_LPD (1 << 0) /* Divider (not encoded) */
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| 132 | #define MAX_LPD (1 << 15) /* Divider (not encoded) */
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| 133 |
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| 134 | #define MCF_CLK_LPCR (IPSBAR + 0x120007)
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| 135 | #define MCF_CLK_CCHR (IPSBAR + 0x120008)
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| 136 | #define MCF_CLK_RTCDR (IPSBAR + 0x12000C)
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| 137 |
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| 138 | #define MCF_INTC0 (IPSBAR + 0x0C00)
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| 139 | #define MCF_INTC1 (IPSBAR + 0x0D00)
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| 140 |
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| 141 | #define MCF_INTC_IMRL(ch) (ch + 0x0c)
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| 142 | #define MCF_INTC_IMRH(ch) (ch + 0x08)
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| 143 | #define MCF_INTC_ICR(ch, n) (ch + 0x40 + n)
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| 144 |
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| 145 | #define MCF_INTC_IMRH_ALL (0x00000000)
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| 146 | #define MCF_INTC_IMRL_ALL (0x00000001)
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| 147 |
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| 148 | #define MCF_GPIO_PUAPAR (IPSBAR + 0x100071)
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| 149 | #define MCF_GPIO_PUBPAR (IPSBAR + 0x100072)
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| 150 | #define MCF_GPIO_PUCPAR (IPSBAR + 0x100073)
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| 151 | #define MCF_GPIO_PUBPAR_TXD1_TXD1 (0x01)
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| 152 | #define MCF_GPIO_PUBPAR_RXD1_RXD1 (0x04)
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| 153 | #define MCF_GPIO_PUCPAR_TXD2_TXD2 (0x01)
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| 154 | #define MCF_GPIO_PUCPAR_RXD2_RXD2 (0x02)
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| 155 | #define MCF_GPIO_PUAPAR_TXD0_TXD0 (0x01)
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| 156 | #define MCF_GPIO_PUAPAR_RXD0_RXD0 (0x04)
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| 157 |
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| 158 | #endif /* _M52235_H_ */
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