1 | /*
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2 | * TOPPERS/JSP Kernel
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3 | * Toyohashi Open Platform for Embedded Real-Time Systems/
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4 | * Just Standard Profile Kernel
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5 | *
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6 | * Copyright (C) 2000-2003 by Embedded and Real-Time Systems Laboratory
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7 | * Toyohashi Univ. of Technology, JAPAN
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8 | * Copyright (C) 2003 by Advanced Data Controls, Corp
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9 | * Copyright (C) 2004 by Embedded and Real-Time Systems Laboratory
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10 | * Graduate School of Information Science, Nagoya Univ., JAPAN
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11 | * Copyright (C) 2006 by GJ Business Division RICOH COMPANY,LTD. JAPAN
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12 | *
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13 | * ä¸è¨è使¨©è
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14 | ã¯ï¼ä»¥ä¸ã® (1)ã(4) ã®æ¡ä»¶ãï¼Free Software Foundation
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15 | * ã«ãã£ã¦å
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16 | ¬è¡¨ããã¦ãã GNU General Public License ã® Version 2 ã«è¨
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17 | * è¿°ããã¦ããæ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§ã¢ï¼æ¬ã½ããã¦ã§ã¢
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18 | * ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ã使ç¨ã»è¤è£½ã»æ¹å¤ã»åé
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19 | å¸ï¼ä»¥ä¸ï¼
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20 | * å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
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21 | * (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
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22 | * 権表示ï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
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23 | * ã¹ã³ã¼ãä¸ã«å«ã¾ãã¦ãããã¨ï¼
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24 | * (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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25 | * ç¨ã§ããå½¢ã§åé
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26 | å¸ããå ´åã«ã¯ï¼åé
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27 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨
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28 | * è
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29 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è使¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
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30 | * ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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31 | * (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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32 | * ç¨ã§ããªãå½¢ã§åé
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33 | å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
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34 | * ã¨ï¼
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35 | * (a) åé
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36 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨è
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37 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
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38 | * 使¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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39 | * (b) åé
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40 | å¸ã®å½¢æ
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41 | ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSããã¸ã§ã¯ãã«
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42 | * å ±åãããã¨ï¼
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43 | * (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
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44 | * 害ãããï¼ä¸è¨è使¨©è
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45 | ããã³TOPPERSããã¸ã§ã¯ããå
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46 | 責ãããã¨ï¼
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47 | *
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48 | * æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨è使¨©è
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49 | ã
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50 | * ãã³TOPPERSããã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ãã®é©ç¨å¯è½æ§ã
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51 | * å«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´
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52 | * æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ãã®è²¬ä»»ãè² ããªãï¼
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53 | *
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54 | * @(#) $Id$
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55 | */
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56 |
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57 | #define _MACRO_ONLY
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58 | #include "jsp_kernel.h"
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59 | #include <at91sam7s.h>
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60 |
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61 |
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62 | /*
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63 | * ä½ã¬ãã«ã®ã¿ã¼ã²ããã·ã¹ãã ä¾åã®åæå
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64 | *
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65 | * ã¹ã¿ã¼ãã¢ããã¢ã¸ã¥ã¼ã«ã®ä¸ã§ï¼ã¡ã¢ãªåæåã®åã«å¼ã³åºãããï¼
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66 | */
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67 |
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68 | .text
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69 | .align 2
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70 | .global hardware_init_hook
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71 | hardware_init_hook:
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72 | ldr r10, =TADR_BASE_RSTC
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73 | ldr r0, =0xA5000c01 /* NRST enable */
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74 | str r0, [r10, #TOFF_RSTC_MR]
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75 | /* Set up FLASH wait state */
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76 | ldr r10, =TADR_MC_BASE
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77 | ldr r0, =(50<<MC_FMR_FMCN_SHIFT) | MC_FMR_FWS_1FWS
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78 | str r0, [r10, #TOFF_MC_FMR]
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79 | /* Disable Watchdog */
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80 | ldr r10, =TADR_WDT_BASE
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81 | ldr r0, =WDT_MR_WDDIS
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82 | str r0, [r10, #TOFF_WDT_MR]
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83 | /* Enable the main oscillator */
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84 | ldr r10, =TADR_PMC_BASE
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85 | ldr r0, =(6<<CKGR_MOR_OSCOUNT_SHIFT)|CKGR_MOR_MOSCEN
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86 | str r0, [r10, #TOFF_CKGR_MOR]
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87 | /* Wait for main oscillator to stabilize */
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88 | oscillator_wait:
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89 | ldr r0, [r10, #TOFF_PMC_SR]
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90 | tst r0, #PMC_SR_MOSCS
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91 | beq oscillator_wait
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92 | /* Set up the PLL */
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93 | /* MCK=18.432[MHz]/(DIV=14)*((MUL=72)+1)/2=48054857[Hz] */
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94 | ldr r0, =(14<<CKGR_PLLR_DIV_SHIFT) | (28<<CKGR_PLLR_PLLCOUNT_SHIFT) | (72<<CKGR_PLLR_MUL_SHIFT)
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95 | str r0, [r10, #TOFF_CKGR_PLLR]
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96 | /* Wait for PLL to lock */
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97 | PLLlock_wait:
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98 | ldr r0, [r10, #TOFF_PMC_SR]
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99 | tst r0, #PMC_SR_LOCK
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100 | beq PLLlock_wait
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101 | /* Select PLL as clock source */
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102 | ldr r0, =(PMC_MCKR_CSS_PLL_CLOCK|PMC_MCKR_PRES_CLK_2)
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103 | str r0, [r10, #TOFF_PMC_MCKR]
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104 | /* Setup the stack for each mode */
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105 | mov r0, sp
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106 | msr cpsr_c, #(CPSR_FIQ|CPSR_IRQ_BIT|CPSR_FIQ_BIT) /* Set up Fast Interrupt Mode and set FIQ Mode Stack */
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107 | ldr r8, =TADR_AIC_BASE /* Init the FIQ register */
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108 |
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109 | msr cpsr_c, #(CPSR_IRQ|CPSR_IRQ_BIT|CPSR_FIQ_BIT) /* Set up Interrupt Mode and set IRQ Mode Stack */
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110 | mov r13, r0 /* Init stack IRQ */
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111 |
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112 | msr cpsr_c, #(CPSR_SVC|CPSR_IRQ_BIT|CPSR_FIQ_BIT) /* Return Supervisor Mode and set Supervisor Mode */
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113 |
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114 | init_done:
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115 | mov pc, lr
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116 |
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117 |
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118 | .text
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119 | .align 2
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120 | .global software_init_hook
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121 | software_init_hook:
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122 | mov pc, lr
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123 |
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124 | .text
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125 | .align 2
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126 | .global software_term_hook
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127 | software_term_hook:
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128 | mov pc, lr
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129 |
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130 |
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131 | /*
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132 | *
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133 | * å²è¾¼ã¿ã®åºå
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134 | ¥ãå£å¦ç
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135 | *
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136 | */
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137 | .text
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138 | .align 4
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139 | .global IRQ_Handler
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140 | IRQ_Handler:
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141 |
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142 | /*
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143 | * å²è¾¼ã¿ã¢ã¼ã
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144 | *
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145 | * cpsrãspsr_irqã«å¾©å¸°å
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146 | ãr14_irq(lp)ã«å
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147 | ¥ãï¼
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148 | * spsr_irqã¨r14_irqã¨r13(sp)_irqã r14,r13ã¨ãªãï¼
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149 | */
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150 |
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151 | /*
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152 | * ã¿ã¹ã¯ã®å使ã¢ã¼ã(ã¹ã¼ãã¼ãã¤ã¶ã¼ã¢ã¼ã)ã¸
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153 | */
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154 | mov sp,#(CPSR_SVC | CPSR_FIQ_BIT | CPSR_IRQ_BIT)
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155 | msr cpsr_all, sp
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156 | stmfd sp!, {r0-r3,ip,lr,pc} /* pcã¯ããã¼ */
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157 |
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158 |
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159 | /*
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160 | * spsrã¨æ»ãçªå°ãåå¾ããããã«IRQã¢ã¼ãã¸
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161 | */
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162 | mov r0,#(CPSR_IRQ | CPSR_FIQ_BIT | CPSR_IRQ_BIT)
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163 | msr cpsr,r0
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164 | sub r0,lr,#4
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165 | mrs r1,spsr
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166 |
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167 | /*
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168 | * ã¹ã¼ãã¼ãã¤ã¶ã¼ã¢ã¼ãã«
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169 | */
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170 | and r2, r1, #CPSR_FIQ_BIT /* FIQãããã®ç¶æ¿ */
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171 | orr r2, r2, #(CPSR_SVC|CPSR_IRQ_BIT)
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172 | msr cpsr_all, r2
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173 | str r0, [sp,#0x18] /* Store pc */
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174 | stmfd sp!,{r1} /* spsr */
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175 |
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176 |
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177 | /*
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178 | * å¤éå²ãè¾¼ã¿ãå¤å®
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179 | */
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180 | ldr r2, =interrupt_count
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181 | ldr r3, [r2]
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182 | add r0,r3,#1
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183 | str r0, [r2]
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184 | cmp r3, #0x00
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185 |
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186 | moveq r2,sp /* ãã¹ãå²ãè¾¼ã¿ã§ãªãå ´å */
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187 | ldreq sp,=STACKTOP /* ã¹ã¿ãã¯ã®å¤æ´ */
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188 | stmeqfd sp!,{r2} /* ã¿ã¹ã¯ã¹ã¿ãã¯ã®ä¿å */
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189 |
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190 | /*
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191 | * å²ãè¾¼ã¿è¦å ã®å¤å®ï¼
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192 | */
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193 | ldr r3, =TADR_AIC_BASE
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194 | ldr r0, [r3, #TOFF_AIC_IVR]
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195 | str r3, [r3, #TOFF_AIC_IVR]
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196 |
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197 | /*
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198 | * å²ãè¾¼ã¿è¨±å¯
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199 | */
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200 | mrs r2, cpsr
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201 | and r2, r2, #~CPSR_IRQ_BIT /* å²è¾¼ã¿è¨±å¯ */
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202 | msr cpsr,r2
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203 |
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204 | /*
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205 | * Call Handler
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206 | */
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207 | mov lr, pc
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208 | mov pc, r0
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209 |
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210 | /*
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211 | * å²ãè¾¼ã¿ç¦æ¢
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212 | */
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213 | mrs r2, cpsr
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214 | and r2, r2, #CPSR_FIQ_BIT /* FIQãããã®ç¶æ¿ */
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215 | orr r2, r2, #(CPSR_SVC|CPSR_IRQ_BIT)
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216 | msr cpsr,r2
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217 |
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218 | /*
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219 | * å²è¾¼ã¿ã¯ãªã¢
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220 | */
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221 | ldr r3, =TADR_AIC_BASE
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222 | mov r0, #0
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223 | str r0, [r3, #TOFF_AIC_EOICR]
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224 |
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225 | /*
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226 | * å²è¾¼ã¿ãã¹ãåæ°(interrupt_count) ãã¯ãªã¡ã³ã
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227 | */
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228 | ldr r2, =interrupt_count
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229 | ldr r1, [r2]
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230 | sub r3, r1, #1
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231 | str r3, [r2]
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232 | cmp r3, #0x00
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233 | bne return_to_task_irq
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234 |
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235 | /*
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236 | * ã¿ã¹ã¯ã¹ã¿ãã¯ã®å¾©å¸°
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237 | */
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238 | ldmfd sp!,{r0}
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239 | mov sp, r0
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240 |
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241 | ldr r1, =reqflg /* Check reqflg */
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242 | ldr r0, [r1]
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243 | cmp r0, #0
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244 | beq return_to_task_irq
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245 | mov r0, #0
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246 | str r0, [r1] /* Clear reqflg */
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247 | b ret_int
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248 |
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249 | return_to_task_irq:
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250 | /*
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251 | * 復帰å¦ç
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252 | * å²ãè¾¼ã¿è¨±å¯ã¨ãªããã¿ã¹ã¯ã³ã³ããã¹ãä¸ã«ä¿åãã¦ããããï¼
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253 | * åé¡ã¯ãªã
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254 | */
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255 | ldmfd sp!,{r1} /* CPSRã®å¾©å¸°å¦ç */
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256 | mrs r2, cpsr /* FIQãç¶æ¿ */
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257 | and r2, r2, #CPSR_FIQ_BIT
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258 | and r1, r1, #~CPSR_FIQ_BIT
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259 | orr r1, r1, r2
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260 | msr spsr, r1 /* å²ãè¾¼ã¿è¨±å¯ */
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261 | ldmfd sp!,{r0-r3,ip,lr,pc}^ /*ã¿ã¹ã¯å¾©å¸° + å²è¾¼ã¿è¨±å¯ */
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262 |
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263 | .text
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264 | .align 4
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265 | .global FIQ_Handler
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266 | FIQ_Handler:
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267 | /* Switch in SVC/User Mode to allow User Stack access for C code */
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268 | /* because the FIQ is not yet acknowledged */
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269 | /* Save and r0 in FIQ_Register */
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270 | mov r9, r0
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271 | ldr r0, [r8, #TOFF_AIC_FVR]
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272 | msr cpsr_c,#(CPSR_SVC|CPSR_IRQ_BIT|CPSR_FIQ_BIT)
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273 | /* Save scratch/used registers and LR in User Stack */
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274 | ldr sp, =(STACKTOP+FIQ_DATA_SIZE)
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275 | stmfd sp!, { r1-r3, r12, lr}
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276 | /* Branch to the routine pointed by the AIC_FVR */
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277 | mov r14, pc
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278 | bx r0
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279 | /* Restore scratch/used registers and LR from User Stack */
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280 | ldmia sp!, { r1-r3, r12, lr}
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281 | /* Leave Interrupts disabled and switch back in FIQ mode */
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282 | msr cpsr_c, #(CPSR_FIQ|CPSR_IRQ_BIT|CPSR_FIQ_BIT)
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283 | /* Restore the R0 ARM_MODE_SVC register */
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284 | mov r0, r9
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285 | /* Restore the Program Counter using the LR_fiq directly in the PC */
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286 | subs pc, lr, #4
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287 |
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288 |
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