source: anotherchoice/tags/jsp-1.4.4-full-UTF8/config/armv4/at91sam7s/at91sam7s.h@ 26

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1/*
2 * rommon Simple Monitor
3 *
4 * Copyright (C) 1999-2004 by Dep. of Computer Science and Engineering
5 * Tomakomai National College of Technology, JAPAN
6 * Copyright (C) 2006 by GJ Business Division RICOH COMPANY,LTD. JAPAN
7 *
8 * 上記著作権者
9は,以下の (1)〜(4) の条件か,Free Software Foundation
10 * によってå…
11¬è¡¨ã•ã‚Œã¦ã„ã‚‹ GNU General Public License の Version 2 に記
12 * 述されている条件を満たす場合に限り,本ソフトウェア(本ソフトウェア
13 * を改変したものを含む.以下同じ)を使用・複製・改変・再é…
14å¸ƒï¼ˆä»¥ä¸‹ï¼Œ
15 * 利用と呼ぶ)することを無償で許諾する.
16 * (1) 本ソフトウェアをソースコードの形で利用する場合には,上記の著作
17 * 権表示,この利用条件および下記の無保証規定が,そのままの形でソー
18 * スコード中に含まれていること.
19 * (2) 本ソフトウェアを,ライブラリ形式など,他のソフトウェア開発に使
20 * 用できる形で再é…
21å¸ƒã™ã‚‹å ´åˆã«ã¯ï¼Œå†é…
22å¸ƒã«ä¼´ã†ãƒ‰ã‚­ãƒ¥ãƒ¡ãƒ³ãƒˆï¼ˆåˆ©ç”¨
23 * 者
24マニュアルなど)に,上記の著作権表示,この利用条件および下記
25 * の無保証規定を掲載すること.
26 * (3) 本ソフトウェアを,機器に組み込むなど,他のソフトウェア開発に使
27 * 用できない形で再é…
28å¸ƒã™ã‚‹å ´åˆã«ã¯ï¼Œæ¬¡ã®ã„ずれかの条件を満たすこ
29 * と.
30 * (a) 再é…
31å¸ƒã«ä¼´ã†ãƒ‰ã‚­ãƒ¥ãƒ¡ãƒ³ãƒˆï¼ˆåˆ©ç”¨è€…
32マニュアルなど)に,上記の著
33 * 作権表示,この利用条件および下記の無保証規定を掲載すること.
34 * (b) 再é…
35å¸ƒã®å½¢æ…
36‹ã‚’,別に定める方法によって,TOPPERSプロジェクトに
37 * 報告すること.
38 * (4) 本ソフトウェアの利用により直接的または間接的に生じるいかなる損
39 * 害からも,上記著作権者
40およびTOPPERSプロジェクトをå…
41è²¬ã™ã‚‹ã“と.
42 *
43 * 本ソフトウェアは,無保証で提供されているものである.上記著作権者
44お
45 * よびTOPPERSプロジェクトは,本ソフトウェアに関して,その適用可能性も
46 * 含めて,いかなる保証も行わない.また,本ソフトウェアの利用により直
47 * 接的または間接的に生じたいかなる損害に関しても,その責任を負わない.
48 *
49 * @(#) $Id$
50 */
51
52#ifndef _AT91SAM7S_H_
53#define _AT91SAM7S_H_
54
55#ifndef _MACRO_ONLY
56#include <itron.h>
57#include <sil.h>
58#endif /* _MACRO_ONLY */
59
60#include "armv4.h"
61#include "sys_config.h"
62#include "cpu_config.h"
63
64
65/*
66 * ADVANCED INTERRUPT CONTROLLER
67 */
68#define TADR_AIC_BASE 0xFFFFF000 /* AIC base address */
69#define TOFF_AIC_SMR 0x0000 /* Source Mode Register0-31 (R/W) */
70 #define AIC_PRIOR (7<<0) /* Priority Level */
71 #define AIC_PRIOR_LOWEST (0) /* Lowest priority level */
72 #define AIC_PRIOR_HIGHEST (7) /* Highest priority level */
73 #define AIC_SRCTYPE (3<<5) /* Interrupt Source Type */
74 #define AIC_SRCTYPE_INT_LEVEL_SENSITIVE (0<<5) /* Internal Sources Code Label Level Sensitive */
75 #define AIC_SRCTYPE_INT_EDGE_TRIGGERED (1<<5) /* Internal Sources Code Label Edge triggered */
76 #define AIC_SRCTYPE_EXT_HIGH_LEVEL (2<<5) /* External Sources Code Label High-level Sensitive */
77 #define AIC_SRCTYPE_EXT_POSITIVE_EDGE (3<<5) /* External Sources Code Label Positive Edge triggered */
78#define TOFF_AIC_SVR 0x0080 /* Source Vector Register0-31 (R/W) */
79#define TOFF_AIC_IVR 0x0100 /* Interrupt Vector Register (R) */
80#define TOFF_AIC_FVR 0x0104 /* Fast Interrupt Vector Register (R) */
81#define TOFF_AIC_ISR 0x0108 /* Interrupt Status Register (R) */
82#define TOFF_AIC_IPR 0x010C /* Interrupt Pending Register (R) */
83#define TOFF_AIC_IMR 0x0110 /* Interrupt Mask Register (R) */
84#define TOFF_AIC_CISR 0x0114 /* Core Interrupt Status Register (R) */
85#define TOFF_AIC_IECR 0x0120 /* Interrupt Enable Command Register (W) */
86#define TOFF_AIC_IDCR 0x0124 /* Interruot Disable Command Register (W) */
87#define TOFF_AIC_ICCR 0x0128 /* Interrupt Clear Command Register (W) */
88#define TOFF_AIC_ISCR 0x012C /* Interrupt Set Command Register (W) */
89#define TOFF_AIC_EOICR 0x0130 /* End of Interrupt Command Register (W) */
90#define TOFF_AIC_SPU 0x0134 /* Spurios Interrupt Vector Register (R/W */
91#define TOFF_AIC_DCR 0x0138 /* Debug Control Register (R/W) */
92#define TOFF_AIC_FFER 0x0140 /* Fast Forcing Enable Register (W) */
93#define TOFF_AIC_FFDR 0x0144 /* Fast Forcing Disable Register (W) */
94#define TOFF_AIC_FFSR 0x0148 /* Fast Forcing Status Register (R) */
95
96
97#define IRQ_FIQ_PID 0
98#define IRQ_SYSIRQ_PID 1
99#define IRQ_PIOA_PID 2
100#define IRQ_ADC_PID 4
101#define IRQ_SPI_PID 5
102#define IRQ_US0_PID 6
103#define IRQ_US1_PID 7
104#define IRQ_SSC_PID 8
105#define IRQ_TWI_PID 9
106#define IRQ_PWM_PID 10
107#define IRQ_UDP_PID 11
108#define IRQ_TC0_PID 12
109#define IRQ_TC1_PID 13
110#define IRQ_TC2_PID 14
111#define IRQ_IRQ0_PID 30
112#define IRQ_IRQ1_PID 31
113
114#ifndef SMR_US0
115#define SMR_US0 (AIC_SRCTYPE_INT_LEVEL_SENSITIVE|AIC_PRIOR_HIGHEST)
116#endif
117#ifndef SMR_US1
118#define SMR_US1 (AIC_SRCTYPE_INT_LEVEL_SENSITIVE|AIC_PRIOR_HIGHEST)
119#endif
120#ifndef SMR_TC0
121#define SMR_TC0 (AIC_SRCTYPE_INT_LEVEL_SENSITIVE|3)
122#endif
123#ifndef SMR_TC1
124#define SMR_TC1 (AIC_SRCTYPE_INT_LEVEL_SENSITIVE|3)
125#endif
126#ifndef SMR_TC2
127#define SMR_TC2 (AIC_SRCTYPE_INT_LEVEL_SENSITIVE|3)
128#endif
129
130/*
131 * DEBUG UNIT Debug Unit
132 */
133#define TADR_DBGU_BASE 0xFFFFF200 /* Debug Unit BASE address */
134#define TOFF_DBGU_CR 0x0000 /* Control Register (W):TOFF_US_CR */
135#define TOFF_DBGU_MR 0x0004 /* Mode Register (R/W):TOFF_US_MR */
136#define TOFF_DBGU_IER 0x0008 /* Interrupt Enable Register (W):TOFF_US_IER */
137#define TOFF_DBGU_IDR 0x000C /* Interrupt Disable Register (W):TOFF_US_IDR */
138#define TOFF_DBGU_IMR 0x0010 /* Interrupt Mask Regiser (R):TOFF_US_IMR */
139#define TOFF_DBGU_SR 0x0014 /* Status Register (R):TOFF_US_CSR */
140#define TOFF_DBGU_RHR 0x0018 /* Receive Holding Register (R):TOFF_US_RHR */
141#define TOFF_DBGU_THR 0x001C /* Transmit Holding Register (W):TOFF_US_THR */
142#define TOFF_DBGU_BRGR 0x0020 /* Baud Rate Generator Register (R/W):TOFF_US_BRGR */
143#define TOFF_DBGU_CIDR 0x0040 /* Chip ID Register (R) */
144#define TOFF_DBGU_EXID 0x0044 /* Chip ID Extension Register (R) */
145#define TOFF_DBGU_FNR 0x0048 /* Force NTRST Register (R/W) */
146
147
148/*
149 * PARALLEL INPUT/OUTPUT CONTROLLER
150 */
151#define TADR_PIO_BASE 0xFFFFF400 /* PIO BASE ADDRESS */
152#define TOFF_PIO_PER 0x0000 /* PIO Enable Register (W) */
153#define TOFF_PIO_PDR 0x0004 /* PIO Disable Register (W) */
154#define TOFF_PIO_PSR 0x0008 /* PIO Status Register (R) */
155#define TOFF_PIO_OER 0x0010 /* Output Enable Register (W) */
156#define TOFF_PIO_ODR 0x0014 /* Output Disable Register (W) */
157#define TOFF_PIO_OSR 0x0018 /* Output Status Register (R) */
158#define TOFF_PIO_IFER 0x0020 /* Glitch Input Filter Enable Register (W) */
159#define TOFF_PIO_IFDR 0x0024 /* Glitch Input Filter Disable Register (W) */
160#define TOFF_PIO_IFSR 0x0028 /* Glitch Input Filter Status Register (R) */
161#define TOFF_PIO_SODR 0x0030 /* Set Output Data Register (W) */
162#define TOFF_PIO_CODR 0x0034 /* Clear Output Data Register (W) */
163#define TOFF_PIO_ODSR 0x0038 /* Output Data Status Register (R) */
164#define TOFF_PIO_PDSR 0x003C /* Pin Data Status Register (R) */
165#define TOFF_PIO_IER 0x0040 /* Interrupt Enable Register (W) */
166#define TOFF_PIO_IDR 0x0044 /* Interrupt Disable Register (W) */
167#define TOFF_PIO_IMR 0x0048 /* Interrupt Mask Register (R) */
168#define TOFF_PIO_ISR 0x004C /* Interrupt Status Register (R) */
169#define TOFF_PIO_MDER 0x0050 /* Multi-driver Enable Register (W) */
170#define TOFF_PIO_MDDR 0x0054 /* Multi-driver Disable Register (W) */
171#define TOFF_PIO_MDSR 0x0058 /* Multi-driver Status Register (R) */
172#define TOFF_PIO_PUDR 0x0060 /* Pull-up Disable Register (W) */
173#define TOFF_PIO_PUER 0x0064 /* Pull-up Enable Register (W) */
174#define TOFF_PIO_PUSR 0x0068 /* Pad Pull-up Statuse Register (R) */
175#define TOFF_PIO_ASR 0x0070 /* Peripheral A Select Register (W) */
176#define TOFF_PIO_BSR 0x0074 /* Peripheral B Select Register (W) */
177#define TOFF_PIO_ABSR 0x0078 /* AB Status Register (R) */
178#define TOFF_PIO_OWER 0x00A0 /* Output Write Enable (W) */
179#define TOFF_PIO_OWDR 0x00A4 /* Output Write Disable (W) */
180#define TOFF_PIO_OWSR 0x00A8 /* Output Write Status Register (R) */
181
182/*
183 * POWER MANAGMENT CONTROLLER
184 */
185#define TADR_PMC_BASE 0xFFFFFC00 /* PMC BASE ADDRESS */
186#define TOFF_PMC_SCER 0x0000 /* System Clock Enable Register (W) */
187#define TOFF_PMC_SCDR 0x0004 /* System Clock Disable Register (W) */
188#define TOFF_PMC_SCSR 0x0008 /* System Clock Status Register (R) */
189#define TOFF_PMC_PCER 0x0010 /* Peripheral Clock Enable Register (W) */
190#define TOFF_PMC_PCDR 0x0014 /* Peripheral Clock Disable Register (W) */
191#define TOFF_PMC_PCSR 0x0018 /* Peripheral Clock Status Register (W) */
192#define TOFF_CKGR_MOR 0x0020 /* Main Oscillator Register (W) */
193 #define CKGR_MOR_MOSCEN (1<<0)
194 #define CKGR_MOR_OSCBYPASS (1<<1)
195 #define CKGR_MOR_OSCOUNT_SHIFT 8
196#define TOFF_CKGR_MCFR 0x0024 /* Main Clock Frequency Register (R) */
197#define TOFF_CKGR_PLLR 0x002C /* PLL Register (R/W) */
198 #define CKGR_PLLR_DIV_SHIFT 0
199 #define CKGR_PLLR_PLLCOUNT_SHIFT 8
200 #define CKGR_PLLR_MUL_SHIFT 16
201#define TOFF_PMC_MCKR 0x0030 /* Master Clock Register (R/W) */
202 #define PMC_MCKR_CSS_PLL_CLOCK (3<<0)
203 #define PMC_MCKR_PRES_CLK_2 (1<<2)
204#define TOFF_PMC_PCK0 0x0040 /* Programmable Clock 0 Register (R/W) */
205#define TOFF_PMC_PCK1 0x0044 /* Programmable Clock 1 Register (R/W) */
206#define TOFF_PMC_IER 0x0060 /* Interrupt Enable Register (W) */
207#define TOFF_PMC_IDR 0x0064 /* Interrupt Disable Register (W) */
208#define TOFF_PMC_SR 0x0068 /* Status Register (R) */
209 #define PMC_SR_MOSCS (1<<0)
210 #define PMC_SR_LOCK (1<<2)
211#define TOFF_PMC_IMR 0x006C /* Interrupt Mask Register (R) */
212
213/*
214 * RESET CONTROLLER (RSTC)
215 */
216#define TADR_BASE_RSTC 0xFFFFFD00 /* RSTC BASE Address */
217#define TOFF_RSTC_CR 0x0000 /* Reset Controller Control Register (W) */
218#define TOFF_RSTC_SR 0x0004 /* Reset Controller Status Register (R) */
219#define TOFF_RSTC_MR 0x0008 /* Reset Controller Mode Register (R/W) */
220
221/*
222 * REAL-TIME TIMER (RTT)
223 */
224#define TADR_RTT_BASE 0xFFFFFD20 /* Real-time Timer BASE address */
225#define TOFF_RTT_MR 0x0000 /* Mode Register (R/W) */
226#define TOFF_RTT_AR 0x0004 /* Alarm Register (R/W) */
227#define TOFF_RTT_VR 0x0008 /* Value Register (R) */
228#define TOFF_RTT_SR 0x000C /* Status Register (R) */
229
230/*
231 * PERIODIC INTERVAL TIMER (PIT)
232 */
233#define TADR_PIT_BASE 0xFFFFFD30 /* Periodic Interval Timer BASE Address */
234#define TOFF_PIT_MR 0x0000 /* Mode Register (R/W) */
235#define TOFF_PIT_SR 0x0004 /* Status Register (R) */
236#define TOFF_PIT_PIVR 0x0008 /* Periodic Interval Value Register (R) */
237#define TOFF_PIT_PIIR 0x000C /* Periodic Interval Image Register (R) */
238
239/*
240 * WATCHDOG TIMER (WDT)
241 */
242#define TADR_WDT_BASE 0xFFFFFD40 /* Watchdog Timer BASE address */
243#define TOFF_WDT_CR 0x0000 /* Watchdog Timer Control Register (W) */
244#define TOFF_WDT_MR 0x0004 /* Watchdog Timer Mode Register (R/W) */
245 #define WDT_MR_WDDIS (1<<15)
246#define TOFF_WDT_SR 0x0008 /* Watchdog Timer Status Register (R) */
247
248/*
249 * VOLTAGE REGULATOR POWER CONTROLLER (VREG)
250 */
251#define TADR_VREG_BASE 0xFFFFFD60 /* VREG BASE address */
252#define TOFF_VREG_MR 0x0000 /* Voltage Regulator Mode Register (R/W) */
253/*
254 * MEMORY CONTROLLER (MC)
255 */
256#define TADR_MC_BASE 0xFFFFFF00 /* Memory Controller BASE address */
257#define TOFF_MC_RCR 0x0000 /* MC Remap Control Register (W) */
258#define TOFF_MC_ASR 0x0004 /* MC Abort Status Register (R) */
259#define TOFF_MC_AASR 0x0008 /* MC Abort Address Status Register (R) */
260#define TOFF_MC_FMR 0x0060 /* MC Flash Mode Register(R/W) */
261 #define MC_FMR_FWS_0FWS (0<<8)
262 #define MC_FMR_FWS_1FWS (1<<8)
263 #define MC_FMR_FWS_2FWS (2<<8)
264 #define MC_FMR_FWS_3FWS (3<<8)
265 #define MC_FMR_FMCN_SHIFT 16
266#define TOFF_MC_FCR 0x0064 /* MC Flash Command Register (W) */
267#define TOFF_MC_FSR 0x0068 /* MC Flash Status Register (R) */
268
269/*
270 * TIMER COUNTER
271 */
272#define TADR_TC_BASE 0xFFFA0000 /* Timer Counter BASE ADDRESS */
273#define TC_WINDOW 0x0040 /* Timer Counter window size */
274#define TOFF_TC_CCR 0x0000 /* Channel Control Register (W) */
275 #define TC_CLKEN (1<<0) /* (TC) Counter Clock Enable Command */
276 #define TC_CLKDIS (1<<1) /* (TC) Counter Clock Disable Command */
277 #define TC_SWTRG (1<<2) /* (TC) Software Trigger Command */
278#define TOFF_TC_CMR 0x0004 /* Channel Mode Register (R/W) */
279 #define TC_CLKS 0x7
280 #define TC_CLKS_MCK2 0x0
281 #define TC_CLKS_MCK8 0x1
282 #define TC_CLKS_MCK32 0x2
283 #define TC_CLKS_MCK128 0x3
284 #define TC_CLKS_MCK1024 0x4
285 #define TC_WAVESEL00 (0<<13) /* (TC) UP mode without atomatic trigger on RC Compare */
286 #define TC_WAVESEL01 (1<<13) /* (TC) UPDOWN mode without automatic trigger on RC Compare */
287 #define TC_WAVESEL10 (2<<13) /* (TC) UP mode with automatic trigger on RC Compare */
288 #define TC_WAVESEL11 (3<<13) /* (TC) UPDOWN mode with automatic trigger on RC Compare */
289#define TOFF_TC_CV 0x0010 /* Counter Value (R) */
290#define TOFF_TC_RA 0x0014 /* Register A (R/W) */
291#define TOFF_TC_RB 0x0018 /* Register B (R/W) */
292#define TOFF_TC_RC 0x001C /* Register C (R/W) */
293#define TOFF_TC_SR 0x0020 /* Statis Register (R) */
294 #define TC_COVFS (1<<0) /* (TC) Counter Overflow */
295 #define TC_LOVRS (1<<1) /* (TC) Load Overrun */
296 #define TC_CPAS (1<<2) /* (TC) RA Compare */
297 #define TC_CPBS (1<<3) /* (TC) RB Compare */
298 #define TC_CPCS (1<<4) /* (TC) RC Compare */
299 #define TC_LDRAS (1<<5) /* (TC) RA Loading */
300 #define TC_LDRBS (1<<6) /* (TC) RB Loading */
301 #define TC_ETRGS (1<<7) /* (TC) External Trigger */
302 #define TC_CLKSTA (1<<16) /* (TC) Clock Enabling */
303 #define TC_MTIOA (1<<17) /* (TC) TIOA Mirror */
304 #define TC_MTIOB (1<<18) /* (TC) TIOA Mirror */
305#define TOFF_TC_IER 0x0024 /* Interrupt Enable Register (W) */
306#define TOFF_TC_IDR 0x0028 /* Interrupt Disable Register (W) */
307#define TOFF_TC_IMR 0x002C /* Interrupt Mask Register (R) */
308#define TOFF_TC_BCR 0x00C0 /* TC Block Control Register (W) */
309#define TOFF_TC_BMR 0x00C4 /* TC Block Mode Register (R/W) */
310
311/*
312 * USB DEVICE PORT (UDP)
313 */
314#define TADR_UDP_BASE 0xFFFB0000 /* USB Device Port BASE Address */
315#define TOFF_UDP_FRM_NUM 0x0000 /* Frame Number Register (R) */
316 #define UDP_FRM_NUM (0x7FF) /* Frame Number as Defined in the Packet Field Formats */
317 #define UDP_FRM_ERR (1<< 16) /* Frame Error */
318 #define UDP_FRM_OK (1<< 17) /* Frame OK */
319#define TOFF_UDP_GLB_STAT 0x0004 /* Global State Register (R/W) */
320 #define UDP_FADDEN (1<<0) /* Function Address Enable */
321 #define UDP_CONFG (1<<1) /* Configured */
322 #define UDP_ESR (1<<2) /* Enable Send Resume */
323 #define UDP_RSMINPR (1<<3) /* A Resume Has Been Sent to the Host */
324 #define UDP_RMWUPE (1<<4) /* Remote Wake Up Enable */
325#define TOFF_UDP_FADDR 0x0008 /* Function Address Register (R/W) */
326 #define UDP_FADD (0xFF<<0) /* Function Address Value */
327 #define UDP_FEN ( 1<<8) /* Function Enable */
328#define TOFF_UDP_IER 0x0010 /* Interrupt Enable Register (W) */
329 #define UDP_IEPINT0 (1<<0) /* Endpoint 0 Interrupt */
330 #define UDP_IEPINT1 (1<<1) /* Endpoint 0 Interrupt */
331 #define UDP_IEPINT2 (1<<2) /* Endpoint 2 Interrupt */
332 #define UDP_IEPINT3 (1<<3) /* Endpoint 3 Interrupt */
333 #define UDP_IEPINT4 (1<<4) /* Endpoint 4 Interrupt */
334 #define UDP_IEPINT5 (1<<5) /* Endpoint 5 Interrupt */
335 #define UDP_IEPINT6 (1<<6) /* Endpoint 6 Interrupt */
336 #define UDP_IEPINT7 (1<<7) /* Endpoint 7 Interrupt */
337 #define UDP_IRXSUSP (1<<8) /* USB Suspend Interrupt */
338 #define UDP_IRXRSM (1<<9) /* USB Resume Interrupt */
339 #define UDP_IEXTRSM (1<<10) /* USB External Resume Interrupt */
340 #define UDP_ISOFINT (1<<11) /* USB Start Of frame Interrupt */
341 #define UDP_IWAKEUP (1<<13) /* USB Walkup Interrupt */
342#define TOFF_UDP_IDR 0x0014 /* Interrupt Disable Register (W) */
343#define TOFF_UDP_IMR 0x0018 /* Interrupt Mask Register (R) */
344#define TOFF_UDP_ISR 0x001C /* Interrupt Status Register (R) */
345 #define UDP_ENDBUSRES (1<<12) /* USB End Of Bus Reset Interrupt */
346#define TOFF_UDP_ICR 0x0020 /* Interrupt Clear Register (W) */
347#define TOFF_UDP_RST_EP 0x0028 /* Reset Endpoint Register (R/W) */
348 #define UDP_EP0 (1<<0) /* Reset Endpoint 0 */
349 #define UDP_EP1 (1<<1) /* Reset Endpoint 1 */
350 #define UDP_EP2 (1<<2) /* Reset Endpoint 2 */
351 #define UDP_EP3 (1<<3) /* Reset Endpoint 3 */
352 #define UDP_EP4 (1<<4) /* Reset Endpoint 4 */
353 #define UDP_EP5 (1<<5) /* Reset Endpoint 5 */
354 #define UDP_EP6 (1<<6) /* Reset Endpoint 6 */
355 #define UDP_EP7 (1<<7) /* Reset Endpoint 7 */
356#define TOFF_UDP_CSR 0x0030 /* Endpoint Control Status Register (R/W) */
357#define TOFF_UDP_CSR0 0x0030 /* Endpoint0 Control Status Register (R/W) */
358#define TOFF_UDP_CSR1 0x0034 /* Endpoint1 Control Status Register (R/W) */
359#define TOFF_UDP_CSR2 0x0038 /* Endpoint2 Control Status Register (R/W) */
360#define TOFF_UDP_CSR3 0x003C /* Endpoint3 Control Status Register (R/W) */
361 #define UDP_TXCOMP (1<<0) /* Generates an IN packet with data previously written in the DPR */
362 #define UDP_RX_DATA_BK0 (1<<1) /* Receive Data Bank 0 */
363 #define UDP_RXSETUP (1<<2) /* Sends STALL to the Host (Control endpoints) */
364 #define UDP_ISOERROR (1<<3) /* Isochronous error (Isochronous endpoints) */
365 #define UDP_TXPKTRDY (1<<4) /* Transmit Packet Ready */
366 #define UDP_FORCESTALL (1<<5) /* Force Stall (used by Control, Bulk and Isochronous endpoints). */
367 #define UDP_RX_DATA_BK1 (1<<6) /* Receive Data Bank 1 (only used by endpoints with ping-pong attributes). */
368 #define UDP_DIR (1<<7) /* Transfer Direction */
369 #define UDP_EPTYPE (7<<8) /* Endpoint type */
370 #define UDP_EPTYPE_CTRL (0<<8) /* Control */
371 #define UDP_EPTYPE_ISO_OUT (1<<8) /* Isochronous OUT */
372 #define UDP_EPTYPE_BULK_OUT (2<<8) /* Bulk OUT */
373 #define UDP_EPTYPE_INT_OUT (3<<8) /* Interrupt OUT */
374 #define UDP_EPTYPE_ISO_IN (5<<8) /* Isochronous IN */
375 #define UDP_EPTYPE_BULK_IN (6<<8) /* Bulk IN */
376 #define UDP_EPTYPE_INT_IN (7<<8) /* Interrupt IN */
377 #define UDP_DTGLE (1<<11) /* Data Toggle */
378 #define UDP_EPEDS (1<<15) /* Endpoint Enable Disable */
379 #define UDP_RXBYTECNT (0x7FF<<16) /* Number Of Bytes Available in the FIFO */
380#define TOFF_UDP_FDR 0x0050 /* Endpoint FIFO Data Register (R/W) */
381#define TOFF_UDP_FDR0 0x0050 /* Endpoint0 FIFO Data Register (R/W) */
382#define TOFF_UDP_FDR1 0x0054 /* Endpoint1 FIFO Data Register (R/W) */
383#define TOFF_UDP_FDR2 0x0058 /* Endpoint2 FIFO Data Register (R/W) */
384#define TOFF_UDP_FDR3 0x005C /* Endpoint3 FIFO Data Register (R/W) */
385#define TOFF_UDP_TXVC 0x0074 /* Transmitter Control Register (R/W) */
386 #define UDP_TXVDIS (1<<8) /* */
387 #define UDP_PUON (1<<9) /* Pull-up ON */
388
389/*
390 * TWO-WIRE INTERFACE (TWI)
391 */
392#define TADR_TWI_BASE 0xFFFB8000 /* Two-wire Interface BASE address */
393#define TOFF_TWI_CR 0x0000 /* Control Register (W) */
394#define TOFF_TWI_MMR 0x0004 /* Master Mode Register (R/W) */
395#define TOFF_TWI_IADR 0x000C /* Internal Address Register (R/W) */
396#define TOFF_TWI_CWGR 0x0010 /* Clock Wavefrom Generator Register (R/W) */
397#define TOFF_TWI_SR 0x0020 /* Status Register (R) */
398#define TOFF_TWI_IER 0x0024 /* Interrupt Enable Register (W) */
399#define TOFF_TWI_IDR 0x0028 /* Interrupt Disable Register (W) */
400#define TOFF_TWI_IMR 0x002C /* Interrupt Mask Register (R) */
401#define TOFF_TWI_RHR 0x0030 /* Receive Holding Register (R) */
402#define TOFF_TWI_THR 0x0034 /* Transmit Holding Register (R/W) */
403
404/*
405 * UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER(USART)
406 */
407#define TADR_US_BASE 0xFFFC0000 /* USART BASE address */
408#define US_WINDOW 0x4000 /* USART Window size */
409#define TOFF_US_CR 0x0000 /* Control Register (W) */
410 #define US_RSTRX 0x0004 /* Reset Receiver */
411 #define US_RSTTX 0x0008 /* Reset Transmitter */
412 #define US_RXEN 0x0010 /* Receiver Enable */
413 #define US_RXDIS 0x0020 /* Receiver Disable */
414 #define US_TXEN 0x0040 /* Transmitter Enable */
415 #define US_TXDIS 0x0080 /* Transmitter Disable */
416 #define US_RSTSTA 0x0100 /* Reset Status Bits */
417 #define US_STTBRK 0x0200 /* Start Break */
418 #define US_STPBRK 0x0400 /* Stop Break */
419 #define US_STTTO 0x0800 /* Start Time-out */
420 #define US_SENDA 0x1000 /* Send Address */
421#define TOFF_US_MR 0x0004 /* Mode Register (R/W) */
422 #define US_CLKS 0x0030 /* Clock Selection */
423 #define US_CLKS_MCK 0x0000 /* Master Clock */
424 #define US_CLKS_MCK8 0x0010 /* Master Clock divided by 8 */
425 #define US_CLKS_SCK 0x0020 /* External Clock */
426 #define US_CLKS_SLCK 0x0030 /* Slow Clock */
427 #define US_CHRL 0x00C0 /* Byte Length */
428 #define US_CHRL_5 0x0000 /* 5 bits */
429 #define US_CHRL_6 0x0040 /* 6 bits */
430 #define US_CHRL_7 0x0080 /* 7 bits */
431 #define US_CHRL_8 0x00C0 /* 8 bits */
432 #define US_PAR 0x0E00 /* Parity Mode */
433 #define US_PAR_EVEN 0x0000 /* Even Parity */
434 #define US_PAR_ODD 0x0200 /* Odd Parity */
435 #define US_PAR_SPACE 0x0400 /* Space Parity to 0 */
436 #define US_PAR_MARK 0x0600 /* Marked Parity to 1 */
437 #define US_PAR_NO 0x0800 /* No Parity */
438 #define US_PAR_MULTIDROP 0x0C00 /* Multi-drop Mode */
439 #define US_NBSTOP 0x3000 /* Stop Bit Number */
440 #define US_NBSTOP_1 0x0000 /* 1 Stop Bit */
441 #define US_NBSTOP_1_5 0x1000 /* 1.5 Stop Bits */
442 #define US_NBSTOP_2 0x2000 /* 2 Stop Bits */
443 #define US_CHMODE 0xC000 /* Channel Mode */
444 #define US_CHMODE_NORMAL 0x0000 /* Normal Mode */
445 #define US_CHMODE_AUTOMATIC_ECHO 0x4000 /* Automatic Echo */
446 #define US_CHMODE_LOCAL_LOOPBACK 0x8000 /* Local Loopback */
447 #define US_CHMODE_REMOTE_LOOPBACK 0xC000 /* Remote Loopback */
448#define TOFF_US_IER 0x0008 /* Interrupt Enable Register (W) */
449#define TOFF_US_IDR 0x000C /* Interrupt Disable Register (W) */
450#define TOFF_US_IMR 0x0010 /* Interrupt Mask Register (R) */
451#define TOFF_US_CSR 0x0014 /* Channel Staus Register (R) */
452 #define US_RXRDY 0x0001 /* Receiver Ready */
453 #define US_TXRDY 0x0002 /* Transmitter Ready */
454 #define US_RXBRK 0x0004 /* Receiver Break */
455 #define US_ENDRX 0x0008 /* End of Receiver PDC Transfer */
456 #define US_ENDTX 0x0010 /* End of Transmitter PDC Transfer */
457 #define US_OVRE 0x0020 /* Overrun Error */
458 #define US_FRAME 0x0040 /* Framing Error */
459 #define US_PARE 0x0080 /* Parity Error */
460 #define US_TIMEOUT 0x0100 /* Receiver Timeout */
461 #define US_TXEMPTY 0x0200 /* Transmitter Empty */
462#define TOFF_US_RHR 0x0018 /* Receiver Holding Register (R) */
463#define TOFF_US_THR 0x001C /* Transmitter Holding Register (W) */
464#define TOFF_US_BRGR 0x0020 /* Baud Rate Generator Register (R/W) */
465
466#define TOFF_US_RTOR 0x0024 /* Receiver Time-out Register (R/W) */
467#define TOFF_US_TTGR 0x0028 /* Transmitter Timeguard Register (R/W) */
468#define TOFF_US_FIDI 0x0040 /* FIDI Ratio Register (R/W) */
469#define TOFF_US_NER 0x0044 /* Number of Errors Register (R) */
470#define TOFF_US_IF 0x004C /* IrDA Filter Register (R/W) */
471#define TOFF_US_MAN 0x0050 /* Manchester Encoder Decoder Register (R/W) */
472
473/*
474 * PUSE WIDTH MODULATION CONTROLLER
475 */
476#define TADR_PWM_BASE 0xFFFCC000 /* Pluse Widh Modulation Controller BASE address */
477#define TOFF_PWM_MR 0x0000 /* PWM Mode Register (R/W) */
478#define TOFF_PWM_ENA 0x0004 /* PWM Enable Register (W) */
479#define TOFF_PWM_DIS 0x0008 /* PWM Disable Register (W) */
480#define TOFF_PWM_SR 0x000C /* PWM Status Register (R) */
481#define TOFF_PWM_IER 0x0010 /* PWM Interrupt Enable Register (W) */
482#define TOFF_PWM_IDR 0x0014 /* PWM Interrupt Disable Register (W) */
483#define TOFF_PWM_IMR 0x0018 /* PWM Interrupt Mask Register (R) */
484#define TOFF_PWM_ISR 0x001C /* PWM Interrupt Status Register (R) */
485#define TADR_PWMC_BASE 0xFFFCC200 /* PWM Channel0 BASE address */
486#define CN_WINDOW 0x0020 /* PWM Channel Window size */
487#define TADR_PWMC0_BASE (TADR_PWMC_BASE)
488#define TADR_PWMC1_BASE (TADR_PWMC_BASE+CN_WINDOW)
489#define TOFF_PWM_CMR 0x0000 /* PWM Channel Mode Register (R/W) */
490#define TOFF_PWM_CDTY 0x0004 /* PWM Channel Duty Cycle Register (R/W) */
491#define TOFF_PWM_CPRD 0x0008 /* PWM Channel Period Register (R/W) */
492#define TOFF_PWM_CCNT 0x000C /* PWM Channel Counter Register (R) */
493#define TOFF_PWM_CUPD 0x0010 /* PWM Channel Update Register (W) */
494
495
496/*
497 * SYNCHRONOUS SERIAL CONTROLLER (SSC)
498 */
499#define TADR_SSC_BASE 0xFFFD4000 /* Synchronous Serial Controller BASE Address */
500#define TOFF_SSC_CR 0x0000 /* Control Register (W) */
501#define TOFF_SSC_CMR 0x0004 /* Clock Mode Register (R/W) */
502#define TOFF_SSC_RCMR 0x0010 /* Receive Clock Mode Register (R/W) */
503#define TOFF_SSC_RFMR 0x0014 /* Receive Frame Mode Register (R/W) */
504#define TOFF_SSC_TCMR 0x0018 /* Transmit Clock Mode Register (R/W) */
505#define TOFF_SSC_TFMR 0x001C /* Transmit Frame Mode Register (R/W) */
506#define TOFF_SSC_RHR 0x0020 /* Receive Holding Register (R) */
507#define TOFF_SSC_THR 0x0024 /* Transmit Holding Register (R) */
508#define TOFF_SSC_RSHR 0x0030 /* Receive Sync. Holding Register (R) */
509#define TOFF_SSC_TSHR 0x0034 /* Transmit Sync. Holding Register (R/W) */
510#define TOFF_SSC_RC0R 0x0038 /* Receive Compare 0 Register (R/W) */
511#define TOFF_SSC_RC1R 0x003C /* Receive Compare 1 Register (R/W) */
512#define TOFF_SSC_SR 0x0040 /* Status Register (R) */
513#define TOFF_SSC_IER 0x0044 /* Interrupt Enable Register (W) */
514#define TOFF_SSC_IDR 0x0048 /* Interrupt Disable Register (W) */
515#define TOFF_SSC_IMR 0x004C /* Interrupt Mask Register (R) */
516
517
518/*
519 * ANALOG-TO-DIGITAL CONVERTER (ADC)
520 */
521#define TADR_ADC_BASE 0xFFFD8000 /* Analog-to-digital Converter BASE address */
522#define TOFF_ADC_CR 0x0000 /* Control Register (W) */
523#define TOFF_ADC_MR 0x0004 /* Mode Register (R/W) */
524#define TOFF_ADC_CHER 0x0010 /* Channel Enable Register (W) */
525#define TOFF_ADC_CHDR 0x0014 /* Channel Disable Register (W) */
526#define TOFF_ADC_CHSR 0x0018 /* Channel Status Register (R) */
527#define TOFF_ADC_SR 0x001C /* Status Register (R) */
528#define TOFF_ADC_LCDR 0x0020 /* Last Converted Data Register (R) */
529#define TOFF_ADC_IER 0x0024 /* Interrupt Enable Register (W) */
530#define TOFF_ADC_IDR 0x0028 /* Interrupt Disable Register (W) */
531#define TOFF_ADC_IMR 0x002C /* Interrupt Mask Register (R) */
532#define TOFF_ADC_CDR 0x0030 /* Channel Data Register (R) */
533#define TOFF_ADC_CDR0 0x0030 /* Channel Data Register0 (R) */
534#define TOFF_ADC_CDR1 0x0034 /* Channel Data Register1 (R) */
535#define TOFF_ADC_CDR2 0x0038 /* Channel Data Register2 (R) */
536#define TOFF_ADC_CDR3 0x003C /* Channel Data Register3 (R) */
537#define TOFF_ADC_CDR4 0x0040 /* Channel Data Register4 (R) */
538#define TOFF_ADC_CDR5 0x0044 /* Channel Data Register5 (R) */
539#define TOFF_ADC_CDR6 0x0048 /* Channel Data Register6 (R) */
540#define TOFF_ADC_CDR7 0x004C /* Channel Data Register7 (R) */
541
542
543/*
544 * SERIAL PERIPHERAL INTERFACE (SPI)
545 */
546#define TADR_SPI_BASE 0xFFFE0000 /* Serial Peripheral Interfcae BASE Address */
547#define TOFF_SPI_CR 0x0000 /* Control Register (W) */
548#define TOFF_SPI_MR 0x0004 /* Mode Register (R/W) */
549#define TOFF_SPI_RDR 0x0008 /* Receive Data Register (R) */
550#define TOFF_SPI_TDR 0x000C /* Transmit Data Register (W) */
551#define TOFF_SPI_SR 0x0010 /* Status Register (R) */
552#define TOFF_SPI_IER 0x0014 /* Interrupt Enable Register (W) */
553#define TOFF_SPI_IDR 0x0018 /* Interrupt Disable Register (W) */
554#define TOFF_SPI_IMR 0x001C /* Interrupt Mask Register (R) */
555#define TOFF_SPI_CSR0 0x0030 /* Chip Select Register0 (R/W) */
556#define TOFF_SPI_CSR1 0x0034 /* Chip Select Register1 (R/W) */
557#define TOFF_SPI_CSR2 0x0038 /* Chip Select Register2 (R/W) */
558#define TOFF_SPI_CSR3 0x003C /* Chip Select Register3 (R/W) */
559
560/*
561 * PERIPHERAL DMA CONTROLLER (PDC)
562 */
563#define TOFF_PDC_RPR 0x0100 /* Receive Pointer Register (R/W) */
564#define TOFF_PDC_RCR 0x0104 /* Receive Counter Register (R/W) */
565#define TOFF_PDC_TPR 0x0108 /* Transmit Pointer Register (R/W) */
566#define TOFF_PDC_TCR 0x010C /* Transmit Counter Register (R/W) */
567#define TOFF_PDC_RNPR 0x0110 /* Receive Next Pointer Register (R/W) */
568#define TOFF_PDC_RNCR 0x0114 /* Receive Next Counter Register (R/W) */
569#define TOFF_PDC_TNPR 0x0118 /* Transmit Next Pointer Register (R/W) */
570#define TOFF_PDC_TNCR 0x011C /* Transmit Next Counter Register (R/W) */
571#define TOFF_PDC_PTCR 0x0120 /* PDC Transfar Control Register (W) */
572#define TOFF_PDC_PTSR 0x0124 /* PDC Transfar Status Register (R) */
573
574
575#if defined (__AT91SAM7S32__)
576// 32kbytes,256pages of 128bytes
577#define FLASH_PAGE_NB 256
578#define FLASH_PAGE_LOCK 32
579#define FLASH_PAGE_SIZE 128
580#define FLASH_PAGE_SIZE_BYTE 128
581#define FLASH_PAGE_SIZE_LONG 32
582// 8lockbits, protecting 8sectors of 32pages
583#define FLASH_LOCK_BITS_SECTOR 8
584#define FLASH_SECTOR_PAGE 32
585#define FLASH_LOCK_BITS 8
586
587#elif defined (__AT91SAM7S64__)
588// 64kbytes,512pages of 128bytes
589#define FLASH_PAGE_NB 512
590#define FLASH_PAGE_LOCK 32
591#define FLASH_PAGE_SIZE 128
592#define FLASH_PAGE_SIZE_BYTE 128
593#define FLASH_PAGE_SIZE_LONG 32
594// 16lockbits, protecting 16sectors of 32pages
595#define FLASH_LOCK_BITS_SECTOR 16
596#define FLASH_SECTOR_PAGE 32
597#define FLASH_LOCK_BITS 16
598
599#elif defined (__AT91SAM7S128__)
600// 128kbytes,512pages of 256bytes
601#define FLASH_PAGE_NB 512
602#define FLASH_PAGE_LOCK 64
603#define FLASH_PAGE_SIZE 256
604#define FLASH_PAGE_SIZE_BYTE 256
605#define FLASH_PAGE_SIZE_LONG 64
606// 8lockbits, protecting 8sectors of 64pages
607#define FLASH_LOCK_BITS_SECTOR 8
608#define FLASH_SECTOR_PAGE 64
609#define FLASH_LOCK_BITS 8
610
611#elif defined (__AT91SAM7S256__)
612// 256kbytes,1024pages of 256bytes
613#define FLASH_PAGE_NB 1024
614#define FLASH_PAGE_LOCK 65
615#define FLASH_PAGE_SIZE 256
616#define FLASH_PAGE_SIZE_BYTE 256
617#define FLASH_PAGE_SIZE_LONG 64
618// 16lockbits, protecting 16sectors of 64pages
619#define FLASH_LOCK_BITS_SECTOR 16
620#define FLASH_SECTOR_PAGE 64
621#define FLASH_LOCK_BITS 16
622
623#endif
624#define FLASH_BASE_ADDRESS 0x00100000
625
626#define MCK 48054857
627
628#ifndef _MACRO_ONLY
629
630/*
631 * 内
632蔵UART用 簡易SIOドライバ
633 */
634/*
635 * カーネル起動時用の初期化(sys_putcを使用するため)
636 */
637extern void init_uart(void);
638
639
640/*
641 * シリアルI/Oポート初期化ブロック
642 */
643typedef struct sio_port_initialization_block
644{
645 VP uart_base;
646 VP linectrl_pdr;
647 VP pmc_pcer;
648 VW pdr_bit;
649 VW irq_bit;
650}
651SIOPINIB;
652
653/*
654 * シリアルI/Oポート管理ブロックの定義
655 */
656typedef struct sio_port_control_block
657{
658 const SIOPINIB *siopinib; /* シリアルI/Oポート初期化ブロック */
659 VP_INT exinf; /* 拡張情
660å ± */
661 BOOL openflag; /* オープン済みフラグ */
662 BOOL sendflag; /* 送信割込みイネーブルフラグ */
663 BOOL getready; /* 文字を受信した状æ…
664‹ */
665 BOOL putready; /* 文字を送信できる状æ…
666‹ */
667
668}SIOPCB;
669
670
671/*
672 * コールバックルーチンの識別番号
673 */
674#define SIO_ERDY_SND 1u /* 送信可能コールバック */
675#define SIO_ERDY_RCV 2u /* 受信通知コールバック */
676
677/*
678 * オンチップのUARTからのポーリング出力
679 */
680Inline void
681uart_putc(char c)
682{
683 while (!(sil_rew_mem((VP)(TADR_DBGU_BASE+TOFF_US_CSR)) & US_TXEMPTY));
684 sil_wrw_mem((VP)(TADR_DBGU_BASE+TOFF_US_THR), c);
685}
686
687
688/*
689 * SIOドライバの初期化ルーチン
690 */
691extern void uart_initialize(void);
692
693/*
694 * オープンしているポートがあるか?
695 */
696extern BOOL uart_openflag(void);
697
698/*
699 * シリアルI/Oポートのオープン
700 */
701extern SIOPCB *uart_opn_por(ID siopid, VP_INT exinf);
702
703/*
704 * シリアルI/Oポートのクローズ
705 */
706extern void uart_cls_por(SIOPCB *siopcb);
707
708/*
709 * シリアルI/Oポートへの文字送信
710 */
711extern BOOL uart_snd_chr(SIOPCB *siopcb, char c);
712
713/*
714 * シリアルI/Oポートからの文字受信
715 */
716extern INT uart_rcv_chr(SIOPCB *siopcb);
717
718/*
719 * シリアルI/Oポートからのコールバックの許可
720 */
721extern void uart_ena_cbr(SIOPCB *siopcb, UINT cbrtn);
722
723/*
724 * シリアルI/Oポートからのコールバックの禁止
725 */
726extern void uart_dis_cbr(SIOPCB *siopcb, UINT cbrtn);
727
728/*
729 * SIOの割込みサービスルーチン
730 */
731extern void uart_in_isr(void);
732extern void uart_out_isr(void);
733
734/*
735 * シリアルI/Oポートからの送信可能コールバック
736 */
737extern void uart_ierdy_snd(VP_INT exinf);
738
739/*
740 * シリアルI/Oポートからの受信通知コールバック
741 */
742extern void uart_ierdy_rcv(VP_INT exinf);
743
744#endif /* _MACRO_ONLY */
745#endif /* _AT91SAM7S_H_ */
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