[26] | 1 | /*
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| 2 | * TOPPERS/JSP Kernel
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| 3 | * Toyohashi Open Platform for Embedded Real-Time Systems/
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| 4 | * Just Standard Profile Kernel
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| 5 | *
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| 6 | * Copyright (C) 2000-2003 by Embedded and Real-Time Systems Laboratory
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| 7 | * Toyohashi Univ. of Technology, JAPAN
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| 8 | * 2003 by Advanced Data Controls, Corp
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| 9 | * Copyright (C) 2009 by Suikan
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| 10 | *
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| 11 | * ä¸è¨èä½æ¨©è
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| 12 | ã¯ï¼ä»¥ä¸ã® (1)ã(4) ã®æ¡ä»¶ãï¼Free Software Foundation
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| 13 | * ã«ãã£ã¦å
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| 14 | ¬è¡¨ããã¦ãã GNU General Public License ã® Version 2 ã«è¨
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| 15 | * è¿°ããã¦ããæ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§ã¢ï¼æ¬ã½ããã¦ã§ã¢
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| 16 | * ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ã使ç¨ã»è¤è£½ã»æ¹å¤ã»åé
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| 17 | å¸ï¼ä»¥ä¸ï¼
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| 18 | * å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
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| 19 | * (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
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| 20 | * 権表示ï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
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| 21 | * ã¹ã³ã¼ãä¸ã«å«ã¾ãã¦ãããã¨ï¼
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| 22 | * (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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| 23 | * ç¨ã§ããå½¢ã§åé
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| 24 | å¸ããå ´åã«ã¯ï¼åé
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| 25 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨
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| 26 | * è
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| 27 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
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| 28 | * ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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| 29 | * (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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| 30 | * ç¨ã§ããªãå½¢ã§åé
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| 31 | å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
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| 32 | * ã¨ï¼
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| 33 | * (a) åé
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| 34 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨è
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| 35 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
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| 36 | * ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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| 37 | * (b) åé
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| 38 | å¸ã®å½¢æ
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| 39 | ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSããã¸ã§ã¯ãã«
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| 40 | * å ±åãããã¨ï¼
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| 41 | * (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
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| 42 | * 害ãããï¼ä¸è¨èä½æ¨©è
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| 43 | ããã³TOPPERSããã¸ã§ã¯ããå
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| 44 | 責ãããã¨ï¼
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| 45 | *
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| 46 | * æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
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| 47 | ã
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| 48 | * ãã³TOPPERSããã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ãã®é©ç¨å¯è½æ§ã
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| 49 | * å«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´
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| 50 | * æ¥çã¾ãã¯éæ¥çã«çãããããªãæ害ã«é¢ãã¦ãï¼ãã®è²¬ä»»ãè² ããªãï¼
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| 51 | *
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| 52 | */
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| 53 |
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| 54 |
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| 55 | /*
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| 56 | * ã¿ã¼ã²ãããããä¾åã¢ã¸ã¥ã¼ã«ï¼LPC2388ç¨ï¼
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| 57 | *
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| 58 | * ãã®ã¤ã³ã¯ã«ã¼ããã¡ã¤ã«ã¯ï¼sys_config.h ã®ã¿ããã¤ã³ã¯ã«ã¼ããããï¼
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| 59 | * ä»ã®ãã¡ã¤ã«ããç´æ¥ã¤ã³ã¯ã«ã¼ããã¦ã¯ãªããªãï¼
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| 60 | */
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| 61 |
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| 62 |
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| 63 | #ifndef _CHIP_CONFIG_H_
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| 64 | #define _CHIP_CONFIG_H_
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| 65 |
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| 66 |
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| 67 | /*
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| 68 | * å²è¾¼ã¿ãã³ãã©ã®æ大æ°
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| 69 | */
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| 70 | #define MAX_INT_NUM 31
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| 71 |
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| 72 | /*
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| 73 | * vxget_tim ããµãã¼ããããã©ããã®å®ç¾©
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| 74 | */
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| 75 | #define SUPPORT_VXGET_TIM
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| 76 |
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| 77 |
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| 78 |
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| 79 | /*
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| 80 | * å²è¾¼ã¿å¾
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| 81 | ã¡ç¶æ
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| 82 | ã§ã®å®è¡ã«ã¼ãã³
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| 83 | */
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| 84 | #ifdef ARM920T_CORE
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| 85 | #define WAIT_INTERRUPT mcr p15, 0, r3, c7, c0, 4
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| 86 | #else
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| 87 | #define WAIT_INTERRUPT nop
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| 88 | #endif
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| 89 |
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| 90 | /*
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| 91 | * ããã»ããµã®ã¨ã³ãã£ã¢ã³
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| 92 | */
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| 93 | #define SIL_ENDIAN SIL_ENDIAN_LITTLE /* ãªãã«ã¨ã³ãã£ã¢ã³ */
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| 94 |
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| 95 |
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| 96 | /*
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| 97 | * ----------------------- å²ãè¾¼ã¿ãã¯ãã«å®£è¨ --------------------
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| 98 | * INTNO_UART0 ã§ã¯ãªã INTO_U0 ã使ãã®ã¯ãUARTãTOPPERS/JSPå
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| 99 | é¨ã®ããã¤ã¹åã¨ãã¦
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| 100 | * 使ã£ã¦ãããUARTã®çªå·ã¨LPC2388ã®éåæéä¿¡ããã¤ã¹ã®çªå·ãä¸è´ããªãããã§ããã
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| 101 | *
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| 102 | */
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| 103 | #define INTNO_WDT 0
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| 104 | /*reserverved interrupt 1*/
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| 105 | #define INTNO_ARM0 2
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| 106 | #define INTNO_ARM1 3
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| 107 | #define INTNO_TIMER0 4
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| 108 | #define INTNO_TIMER1 5
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| 109 | #define INTNO_U0 6
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| 110 | #define INTNO_U1 7
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| 111 | #define INTNO_PWM1 8
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| 112 | #define INTNO_I2C0 9
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| 113 | #define INTNO_SSP0 10
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| 114 | #define INTNO_SSP1 11
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| 115 | #define INTNO_PLL 12
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| 116 | #define INTNO_RTC 13
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| 117 | #define INTNO_EINT0 14
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| 118 | #define INTNO_EINT1 15
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| 119 | #define INTNO_EINT2 16
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| 120 | #define INTNO_EINT3 17
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| 121 | #define INTNO_ADC0 18
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| 122 | #define INTNO_I2C1 19
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| 123 | #define INTNO_BOD 20
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| 124 | #define INTNO_ETHERNET 21
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| 125 | #define INTNO_USB 22
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| 126 | #define INTNO_CAN 23
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| 127 | #define INTNO_SD 24
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| 128 | #define INTNO_GPDMA 25
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| 129 | #define INTNO_TIMER2 26
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| 130 | #define INTNO_TIMER3 27
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| 131 | #define INTNO_U2 28
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| 132 | #define INTNO_U3 29
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| 133 | #define INTNO_I2C2 30
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| 134 | #define INTNO_I2S 31
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| 135 |
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| 136 | #define INHNO_WDT 0
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| 137 | /*reserverved interrupt 1*/
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| 138 | #define INHNO_ARM0 2
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| 139 | #define INHNO_ARM1 3
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| 140 | #define INHNO_TIMER0 4
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| 141 | #define INHNO_TIMER1 5
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| 142 | #define INHNO_U0 6
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| 143 | #define INHNO_U1 7
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| 144 | #define INHNO_PWM1 8
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| 145 | #define INHNO_I2C0 9
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| 146 | #define INHNO_SSP0 10
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| 147 | #define INHNO_SSP1 11
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| 148 | #define INHNO_PLL 12
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| 149 | #define INHNO_RTC 13
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| 150 | #define INHNO_EINT0 14
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| 151 | #define INHNO_EINT1 15
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| 152 | #define INHNO_EINT2 16
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| 153 | #define INHNO_EINT3 17
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| 154 | #define INHNO_ADC0 18
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| 155 | #define INHNO_I2C1 19
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| 156 | #define INHNO_BOD 20
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| 157 | #define INHNO_ETHERNET 21
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| 158 | #define INHNO_USB 22
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| 159 | #define INHNO_CAN 23
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| 160 | #define INHNO_SD 24
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| 161 | #define INHNO_GPDMA 25
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| 162 | #define INHNO_TIMER2 26
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| 163 | #define INHNO_TIMER3 27
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| 164 | #define INHNO_U2 28
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| 165 | #define INHNO_U3 29
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| 166 | #define INHNO_I2C2 30
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| 167 | #define INHNO_I2S 31
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| 168 |
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| 169 | /*
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| 170 | * SIO1,2,3ã«ã¯U0,U2,U3ãå²ãå½ã¦ã
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| 171 | */
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| 172 | #define INHNO_SIO INHNO_U0
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| 173 | #define INHNO_SIO2 INHNO_U2
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| 174 | #define INHNO_SIO3 INHNO_U3
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| 175 |
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| 176 | /*
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| 177 | * ----------------------- UART è¨å® ---------------------------
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| 178 | */
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| 179 |
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| 180 | /*
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| 181 | * UARTã®ãã¡ãå¹¾ã¤ã®ãã¼ããPDICã¨ãã¦ä½¿ç¨ããã宣è¨ããã
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| 182 | * LPC2388çã§ã¯æ大3
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| 183 | */
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| 184 | #define TNUM_SIOP_UART TNUM_SIOP
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| 185 |
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| 186 | /*
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| 187 | * UARTã®ã¬ã¸ã¹ã¿ãä½ãã¤ãå¢çã«é
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| 188 | ç½®ããã¦ããããæå®ãããæå®ã§ããå¤ã¯1,2,4ã®ããããã
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| 189 | */
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| 190 | #define UART_BOUNDARY 4
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| 191 |
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| 192 | /*
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| 193 | * UART ã¬ã¸ã¹ã¿ã¸ã®ã¢ã¯ã»ã¹ã«sil_xxb_iop()使ãå ´åã«ã¯ãã®ãã¯ãã宣è¨ããã
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| 194 | * å¤ã¯ä¸è¦ã宣è¨ããªãå ´åãsil_xxb_mem()ã«ãã£ã¦ã¢ã¯ã»ã¹ãããLPC2388å®è£
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| 195 |
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| 196 | * ã§ã¯memã¢ã¯ã»ã¹ã使ç¨ããã
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| 197 | */
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| 198 | /* #define UART_IOP_ACCESS */
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| 199 |
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| 200 | /*
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| 201 | * UARTã®ãã¼ã¹ã»ã¢ãã¬ã¹ãæå®ããããã¼ã¹ã¢ãã¬ã¹ã¨ã¯THRã®ã¢ãã¬ã¹ã®ãã¨ã
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| 202 | * U0,2,3ã使ãã®ã¯ãLPC2388ã«ããã¦U1ã ãå¥æ±ãã®ãã
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| 203 | */
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| 204 | #define UART0_ADDRESS 0xE000C000
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| 205 | #define UART1_ADDRESS 0xE0078000 /*U2*/
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| 206 | #define UART2_ADDRESS 0xE007C000 /*U3*/
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| 207 |
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| 208 | /*
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| 209 | * UARTå
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| 210 | é¨ã®åå¨åè·¯ã®è¨å®å¤ãæå®ããã16ãããã®å¤ãlpc2388uart.cå
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| 211 | é¨ã§
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| 212 | * ä¸ä½ã¨ä¸ä½ã«åå²ãã¦DLM/DLLã¬ã¸ã¹ã¿ã«è¨å®ãããã
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| 213 | *
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| 214 | * UARTã®ããã¤ã¶ã®åºåã¯ææãããã¼ã¬ã¼ãã®16åã§ãªããã°ãªããªãã
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| 215 | * U0,2,3ã使ãã®ã¯ãLPC2388ã«ããã¦U1ã ãå¥æ±ãã®ãã
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| 216 | */
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| 217 | #define UART0_DIVISOR (LP2388_SYSTEM_UART0_CLOCK/16/UART0_BAUD_RATE)
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| 218 | #define UART1_DIVISOR (LP2388_SYSTEM_UART1_CLOCK/16/UART2_BAUD_RATE) /*U2*/
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| 219 | #define UART2_DIVISOR (LP2388_SYSTEM_UART1_CLOCK/16/UART3_BAUD_RATE) /*U3*/
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| 220 |
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| 221 |
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| 222 | /*
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| 223 | * ----------------------- UART è¨å®ããã ---------------------------
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| 224 | */
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| 225 |
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| 226 |
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| 227 | #ifndef _MACRO_ONLY
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| 228 |
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| 229 | /*
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| 230 | * ã¿ã¼ã²ããã·ã¹ãã ä¾åã®åæå
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| 231 | */
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| 232 | extern void sys_initialize(void);
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| 233 |
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| 234 | /*
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| 235 | * ã¿ã¼ã²ããã·ã¹ãã ã®çµäº
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| 236 | *
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| 237 | * ã·ã¹ãã ãçµäºããæã«ä½¿ãï¼ROMã¢ãã¿å¼åºãã§å®ç¾ãããã¨ãæ³å®ã
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| 238 | * ã¦ããï¼
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| 239 | */
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| 240 | extern void sys_exit(void);
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| 241 |
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| 242 | /*
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| 243 | * ã¿ã¼ã²ããã·ã¹ãã ã®æååºå
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| 244 | *
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| 245 | * ã·ã¹ãã ã®ä½ã¬ãã«ã®æååºåã«ã¼ãã³ï¼ROMã¢ãã¿å¼åºãã§å®ç¾ããã
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| 246 | * ã¨ãæ³å®ãã¦ããï¼
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| 247 | */
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| 248 | extern void sys_putc(char c);
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| 249 |
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| 250 |
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| 251 |
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| 252 | /*
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| 253 | * IRQãã³ãã©(sys_support.S)
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| 254 | */
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| 255 | extern void IRQ_Handler(void);
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| 256 |
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| 257 | /*
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| 258 | * å²è¾¼ã¿ãã³ãã©ã®åºå
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| 259 | ¥å£å¦çã®çæãã¯ã
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| 260 | *
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| 261 | */
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| 262 | #define INTHDR_ENTRY(inthdr) extern void inthdr(void)
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| 263 |
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| 264 | #define INT_ENTRY(inthdr) inthdr
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| 265 |
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| 266 | /*
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| 267 | * å²è¾¼ã¿ãã³ãã©ã®è¨å®
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| 268 | *
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| 269 | * å²è¾¼ã¿çªå· inhno ã®å²è¾¼ã¿ãã³ãã©ã®èµ·åçªå°ã inthdr ã«è¨å®ããï¼
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| 270 | */
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| 271 | extern void define_inh(INHNO inhno, FP inthdr);
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| 272 |
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| 273 | extern void undef_interrupt();
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| 274 |
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| 275 | extern void init_IRQ();
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| 276 | extern void init_vector();
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| 277 | extern void init_uart0();
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| 278 |
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| 279 | /*
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| 280 | * å²ãè¾¼ã¿ã®ã¤ãã¼ãã«ããã£ã»ã¼ãã«
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| 281 | */
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| 282 |
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| 283 | extern ER dis_int(INTNO intno);
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| 284 | extern ER ena_int(INTNO intno);
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| 285 | extern ER chg_ims(unsigned int enableMask);
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| 286 | extern ER get_ims(unsigned int *p_enableMask);
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| 287 |
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| 288 | #endif /* _MACRO_ONLY */
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| 289 | #endif /* _SYS_CONFIG_H_ */
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