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source: UsbWattMeter/trunk/asp_dcre/pdic/rx600/rx630_uart.c@ 164

Last change on this file since 164 was 164, checked in by coas-nagasima, 8 years ago
TOPPERS/ECNLサンプルアプリ「USB充電器電力計」を追加
Property svn:eol-style set to `native` Property svn:keywords set to `Id` Property svn:mime-type set to `text/x-csrc`
File size: 12.0 KB

Line
1	/*
2	* TOPPERS/ASP Kernel
3	* Toyohashi Open Platform for Embedded Real-Time Systems/
4	* Advanced Standard Profile Kernel
5	*
6	* Copyright (C) 2008-2010 by Witz Corporation, JAPAN
7	* Copyright (C) 2013 by Mitsuhiro Matsuura
8	*
9	* ãLì ÒÍCÈºÌ(1)`(4)Ìðð½·êÉÀèC{\tgEF
10	* Ai{\tgEFAðüÏµ½àÌðÜÞDÈº¯¶jðgpE¡»Eü
11	* ÏEÄzziÈºCpÆÄÔj·é±Æð³Åø·éD
12	* (1) {\tgEFAð\[XR[hÌ`Åp·éêÉÍCãLÌì
13	* \¦C±Ìpð¨æÑºLÌ³ÛØKèªC»ÌÜÜÌ`Å\[
14	* XR[hÉÜÜêÄ¢é±ÆD
15	* (2) {\tgEFAðCCu`®ÈÇC¼Ì\tgEFAJÉg
16	* pÅ«é`ÅÄzz·éêÉÍCÄzzÉº¤hL
17	gip
18	* Ò}j
19	AÈÇjÉCãLÌì \¦C±Ìpð¨æÑºL
20	* Ì³ÛØKèðfÚ·é±ÆD
21	* (3) {\tgEFAðC@íÉgÝÞÈÇC¼Ì\tgEFAJÉg
22	* pÅ«È¢`ÅÄzz·éêÉÍCÌ¢¸ê©Ìðð½·±
23	* ÆD
24	* (a) ÄzzÉº¤hL
25	gipÒ}j
26	AÈÇjÉCãLÌ
27	* ì \¦C±Ìpð¨æÑºLÌ³ÛØKèðfÚ·é±ÆD
28	* (b) ÄzzÌ`ÔðCÊÉèßéû@ÉæÁÄCTOPPERSvWFNgÉ
29	* ñ·é±ÆD
30	* (4) {\tgEFAÌpÉæè¼ÚIÜ½ÍÔÚIÉ¶¶é¢©Èé¹
31	* Q©çàCãLì Ò¨æÑTOPPERSvWFNgðÆÓ·é±ÆD
32	* Ü½C{\tgEFAÌ[UÜ½ÍGh[U©çÌ¢©Èé
33	* RÉîÃ¿©çàCãLì Ò¨æÑTOPPERSvWFNgð
34	* ÆÓ·é±ÆD
35	*
36	* {\tgEFAÍC³ÛØÅñ³êÄ¢éàÌÅ éDãLì Ò¨
37	* æÑTOPPERSvWFNgÍC{\tgEFAÉÖµÄCÁèÌgpÚI
38	* ÉÎ·éK«àÜßÄC¢©ÈéÛØàsíÈ¢DÜ½C{\tgEF
39	* AÌpÉæè¼ÚIÜ½ÍÔÚIÉ¶¶½¢©Èé¹QÉÖµÄàC»
40	* ÌÓCðíÈ¢D
41	*
42	* @(#) $Id: rx630_uart.c 164 2016-03-07 11:33:50Z coas-nagasima $
43	*/
44
45
46	/*
47	* UARTp ÈÕSIOhCo
48	*/
49
50	#include <sil.h>
51	#include <kernel.h>
52	#include <t_syslog.h>
53	#include "target_syssvc.h"
54	#include "rx630_uart.h"
55
56	/* VA[hWX^iSMR) */
57	#define CKS UINT_C(0x03)
58	#define STOP UINT_C(0x08)
59	#define PM UINT_C(0x10)
60	#define PE UINT_C(0x20)
61	#define CHR UINT_C(0x40)
62	#define CM UINT_C(0x80)
63	#define ASYNC_7BIT UINT_C(0x00)
64	#define ASYNC_8BIT UINT_C(0x40)
65
66	/* VARg[WX^iSCR) */
67	#define CKE UINT_C(0x03)
68	#define TEIE UINT_C(0x04)
69	#define RE UINT_C(0x10)
70	#define TE UINT_C(0x20)
71	#define RIE UINT_C(0x40)
72	#define TIE UINT_C(0x80)
73
74	/* VAXe[^XWX^iSSRj */
75	#define TEND UINT_C(0x04)
76	#define PER UINT_C(0x08)
77	#define FER UINT_C(0x10)
78	#define ORER UINT_C(0x20)
79
80	/* VAg£[hWX^iSEMR) */
81	#define ACS0 UINT_C(0x01)
82	#define ABCS UINT_C(0x10)
83
84	#define SCI_SCR_FLG_ENABLE (RE \| TE)
85	#define SCI_SMR_FLG_ENABLE (STOP \| PM \| PE \| CHR \| CM)
86
87	/*
88	* VAI/O\|[gú»ubNÌè`
89	*/
90	typedef struct sio_port_initialization_block {
91	volatile uint8_t ctlreg; / VARg[WX^iSCR) */
92	volatile uint8_t modereg; / VA[hWX^iSMR) */
93	volatile uint8_t extmodereg; / VAg£[hWX^iSEMR) */
94	volatile uint8_t statusreg; / VAXe[^XWX^iSSRj */
95	volatile uint8_t tdreg; / gX~bgf[^WX^iTDR)*/
96	volatile uint8_t rdreg; / V[uf[^WX^iRDR) */
97	volatile uint8_t bitratereg; / rbg[gWX^iBRR) */
98	volatile uint32_t mstpcrreg; / W
99	[XgbvRg[WX^iMSTPCRj */
100	volatile uint8_t ssrreg; / Xe[^XWX^ */
101	volatile uint8_t rxiirreg; / RXIpÝvWX^ */
102	uint8_t tx_intno; /* Mif[^GveBjèÝÔ */
103	uint8_t rx_intno; /* óMif[^tjèÝÔ */
104	uint8_t te_intno; /* MiI¹jèÝÔ */
105	uint8_t sci_no; /* SCIÌÔ(SCI0`SCI6) */
106	uint32_t mstpcr_offset; /* MSTPCRÌÎ·érbgItZbg */
107	} SIOPINIB;
108
109	/*
110	* VAI/O\|[gÇubNÌè`
111	*/
112	struct sio_port_control_block {
113	const SIOPINIB p_siopinib; / VAI/O\|[gú»ubN */
114	intptr_t exinf; /* g£îñ */
115	bool_t openflag; /* I[vÏÝtO */
116	bool_t sendflag; /* MÝCl[utO */
117	bool_t getready; /* ¶ðóMµ½óÔ */
118	bool_t putready; /* ¶ðMÅ«éóÔ */
119	bool_t is_initialized; /* foCXú»ÏÝtO */
120	};
121
122	/*
123	* VAI/O\|[gÇubNÌGA
124	*/
125	static SIOPCB siopcb_table[TNUM_SIOP];
126
127	/* WX^e[u */
128	static const SIOPINIB siopinib_table[TNUM_SIOP] =
129	{
130	{
131	(volatile uint8_t *)SCI0_SCR_ADDR,
132	(volatile uint8_t *)SCI0_SMR_ADDR,
133	(volatile uint8_t *)SCI0_SEMR_ADDR,
134	(volatile uint8_t *)SCI0_SSR_ADDR,
135	(volatile uint8_t *)SCI0_TDR_ADDR,
136	(volatile uint8_t *)SCI0_RDR_ADDR,
137	(volatile uint8_t *)SCI0_BRR_ADDR,
138	(volatile uint32_t *)SYSTEM_MSTPCRB_ADDR,
139	(volatile uint8_t *)SCI0_SSR_ADDR,
140	(volatile uint8_t *)ICU_IR215_ADDR,
141	INT_SCI0_TXI,
142	INT_SCI0_RXI,
143	INT_SCI0_TEI,
144	0,
145	SYSTEM_MSTPCRB_MSTPB31_BIT,
146	} , /* UART0 */
147	#if TNUM_SIOP > 1
148	{
149	(volatile uint8_t *)SCI2_SCR_ADDR,
150	(volatile uint8_t *)SCI2_SMR_ADDR,
151	(volatile uint8_t *)SCI2_SEMR_ADDR,
152	(volatile uint8_t *)SCI2_SSR_ADDR,
153	(volatile uint8_t *)SCI2_TDR_ADDR,
154	(volatile uint8_t *)SCI2_RDR_ADDR,
155	(volatile uint8_t *)SCI2_BRR_ADDR,
156	(volatile uint32_t *)SYSTEM_MSTPCRB_ADDR,
157	(volatile uint8_t *)SCI2_SSR_ADDR,
158	(volatile uint8_t *)ICU_IR223_ADDR,
159	INT_SCI2_TXI,
160	INT_SCI2_RXI,
161	INT_SCI2_TEI,
162	2,
163	SYSTEM_MSTPCRB_MSTPB29_BIT,
164	} , /* UART2 */
165	#endif
166	};
167
168	/*
169	* VAI/O\|[gID©çÇubNðæèo·½ßÌ}N
170	*/
171	#define INDEX_SIOP(siopid) ((uint_t)((siopid) - 1))
172	#define get_siopcb(siopid) (&(siopcb_table[INDEX_SIOP(siopid)]))
173	#define get_siopinib(siopid) (&(siopinib_table[INDEX_SIOP(siopid)]))
174
175
176	/*
177	* SIOhCoÌVA[hWX^(SMR)
178	*/
179	static void
180	rx630_uart_setmode(const SIOPINIB *p_siopinib, uint8_t bitrate, uint8_t clksrc)
181	{
182	volatile uint8_t i;
183
184	/*
185	* SCIhCoÌú»[`
186	*/
187
188	/*
189	* èÝvæWX^ÌÝè(ISELRi)
190	*
191	* ZbglÆ¯¶lðÝè·é±ÆÉÈé½ß,
192	* ÍÈª·é.
193	*/
194
195	/*
196	* W
197	[Xgbv@\ÌÝè
198	*/
199	sil_wrh_mem((uint16_t )SYSTEM_PRCR_ADDR, (uint16_t)0xA502); / ÝÂ */
200	sil_wrw_mem((uint32_t *)p_siopinib->mstpcrreg,
201	sil_rew_mem((uint32_t *)p_siopinib->mstpcrreg) & ~p_siopinib->mstpcr_offset);
202	sil_wrh_mem((uint16_t )SYSTEM_PRCR_ADDR, (uint16_t)0xA500); / ÝÖ~ */
203
204	/* óMÖ~, SCKn[qÍüoÍ\|[gÆµÄgp */
205	sil_wrb_mem((uint8_t *)p_siopinib->ctlreg, 0x00U);
206
207	/* NbNIðrbg(SMR.CKS[1:0]rbgðÝè) */
208	sil_wrb_mem((uint8_t *)p_siopinib->modereg,
209	sil_reb_mem((uint8_t *)p_siopinib->modereg) \| clksrc);
210
211	/* SMRÉM^ óMtH[}bgðÝè) */
212	sil_wrb_mem((uint8_t *)p_siopinib->modereg,
213	sil_reb_mem((uint8_t *)p_siopinib->modereg) & (~SCI_SMR_FLG_ENABLE));
214
215	/* rbg[gðÝè */
216	sil_wrb_mem((uint8_t *)p_siopinib->bitratereg, bitrate);
217
218	/* rbgúÔ(î{NbN16TCNÌúÔª1rbgúÔÆÈé) */
219	for(i = 0; i < 16; i++) { }
220
221	/* óMÂ */
222	sil_wrb_mem((uint8_t *)p_siopinib->ctlreg,
223	(sil_reb_mem((uint8_t *)p_siopinib->ctlreg) \| SCI_SCR_FLG_ENABLE));
224	}
225
226
227	/*
228	* SIOhCoÌú»[`
229	*/
230	void
231	rx630_uart_initialize(void)
232	{
233	SIOPCB *p_siopcb;
234	uint_t i;
235
236	/*
237	* VAI/O\|[gÇubNÌú»
238	*/
239	for (p_siopcb = siopcb_table, i = 0; i < TNUM_SIOP; p_siopcb++, i++){
240	p_siopcb->p_siopinib = &(siopinib_table[i]);
241	p_siopcb->openflag = false;
242	p_siopcb->sendflag = false;
243	}
244	}
245
246	/*
247	* J[lN®Ìoi[oÍpÌú»
248	*/
249	void
250	rx630_uart_init(ID siopid, uint8_t bitrate, uint8_t clksrc)
251	{
252	SIOPCB *p_siopcb = get_siopcb(siopid);
253	const SIOPINIB *p_siopinib = get_siopinib(siopid);
254	/* ±Ì_ÅÍAp_siopcb->p_siopinibÍú»³êÄ¢È¢ */
255
256	/* ñdú»Ìh~ */
257	p_siopcb->is_initialized = true;
258
259	/* n[hEFAÌú»ÆMÂ */
260	rx630_uart_setmode(p_siopinib , bitrate, clksrc);
261	sil_wrb_mem((uint8_t *)p_siopinib->ctlreg,
262	(uint8_t)(sil_reb_mem((uint8_t *)p_siopinib->ctlreg) \| TE));
263	}
264
265	/*
266	* VAI/O\|[gÖÌ\|[OÅÌoÍ
267	*/
268	void
269	rx630_uart_pol_putc(char c, ID siopid)
270	{
271	const SIOPINIB *p_siopinib;
272
273	p_siopinib = get_siopinib(siopid);
274
275	/*
276	* MWX^ªóÉÈéÜÅÒÂ
277	*/
278	while((sil_reb_mem((uint8_t *)p_siopinib->ssrreg) & SCI_SSR_TEND_BIT) == 0U);
279
280	sil_wrb_mem((uint8_t *)p_siopinib->tdreg, (uint8_t)c);
281	}
282
283	/*
284	* VAI/O\|[gÌI[v
285	*/
286	SIOPCB *
287	rx630_uart_opn_por
288	(ID siopid, intptr_t exinf, uint8_t bitrate, uint8_t clksrc)
289	{
290	SIOPCB *p_siopcb;
291	const SIOPINIB *p_siopinib;
292
293	p_siopcb = get_siopcb(siopid);
294	p_siopinib = p_siopcb->p_siopinib;
295
296	/*
297	* n[hEFAÌú»
298	*
299	* ùÉú»µÄ¢éêÍ, ñdÉú»µÈ¢.
300	*/
301	if(!(p_siopcb->is_initialized)){
302	rx630_uart_setmode(p_siopinib, bitrate, clksrc);
303	p_siopcb->is_initialized = true;
304	}
305
306	p_siopcb->exinf = exinf;
307	p_siopcb->getready = p_siopcb->putready = false;
308	p_siopcb->openflag = true;
309
310	return (p_siopcb);
311	}
312
313	/*
314	* VAI/O\|[gÌN[Y
315	*/
316	void
317	rx630_uart_cls_por(SIOPCB *p_siopcb)
318	{
319	/*
320	* UARTâ~
321	*/
322	sil_wrh_mem((uint16_t *)p_siopcb->p_siopinib->ctlreg, 0x00U);
323	p_siopcb->openflag = false;
324	p_siopcb->is_initialized = false;
325	}
326
327	/*
328	* VAI/O\|[gÖÌ¶M
329	*/
330	bool_t
331	rx630_uart_snd_chr(SIOPCB *p_siopcb, char c)
332	{
333	bool_t ercd = false;
334
335	if((sil_reb_mem(
336	(uint8_t *)p_siopcb->p_siopinib->ssrreg) & SCI_SSR_TEND_BIT) != 0){
337	sil_wrb_mem((uint8_t *)p_siopcb->p_siopinib->tdreg, (uint8_t)c);
338	ercd = true;
339	}
340
341	return ercd;
342	}
343
344	/*
345	* VAI/O\|[g©çÌ¶óM
346	*/
347	int_t
348	rx630_uart_rcv_chr(SIOPCB *p_siopcb)
349	{
350	int_t c = -1;
351
352	/*
353	* óMtOªONÌÆ«ÌÝóMobt@©ç¶ðæ¾·é.
354	* ±êÍ, \|[OóMÉÎ·é½ßÅ é.
355	* µ©µ, RX600V[YÅÍóMtOªÈ¢±Æ, VXeT[rX
356	* ÅÍóMÝÌ©çµ©f[^ðóMµÉÈ¢±Æ©ç, íÉ
357	* óMobt@©ç¶ðæ¾·é.
358	*/
359	c = (int)(sil_reb_mem((uint8_t *)p_siopcb->p_siopinib->rdreg));
360
361	return c;
362	}
363
364	/*
365	* VAI/O\|[g©çÌR[obNÌÂ
366	*/
367	void
368	rx630_uart_ena_cbr(SIOPCB *p_siopcb, uint_t cbrtn)
369	{
370	switch (cbrtn) {
371	case SIO_RDY_SND:
372	sil_wrb_mem((uint8_t *)p_siopcb->p_siopinib->ctlreg,
373	(sil_reb_mem((uint8_t *)p_siopcb->p_siopinib->ctlreg) \| SCI_SCR_TEIE_BIT));
374	break;
375	case SIO_RDY_RCV:
376	sil_wrb_mem((uint8_t *)p_siopcb->p_siopinib->ctlreg,
377	(sil_reb_mem((uint8_t *)p_siopcb->p_siopinib->ctlreg) \| SCI_SCR_RIE_BIT));
378	break;
379	default:
380	assert(1);
381	break;
382	}
383	}
384
385	/*
386	* VAI/O\|[g©çÌR[obNÌÖ~
387	*/
388	void
389	rx630_uart_dis_cbr(SIOPCB *p_siopcb, uint_t cbrtn)
390	{
391	switch (cbrtn) {
392	case SIO_RDY_SND:
393	sil_wrb_mem((uint8_t *)p_siopcb->p_siopinib->ctlreg,
394	(sil_reb_mem((uint8_t *)p_siopcb->p_siopinib->ctlreg) & (~SCI_SCR_TEIE_BIT)));
395	break;
396	case SIO_RDY_RCV:
397	sil_wrb_mem((uint8_t *)p_siopcb->p_siopinib->ctlreg,
398	(sil_reb_mem((uint8_t *)p_siopcb->p_siopinib->ctlreg) & (~SCI_SCR_RIE_BIT)));
399	break;
400	default:
401	assert(1);
402	break;
403	}
404	}
405
406	/*
407	* SIOÌÝT[rX[`
408	*/
409	void
410	rx630_uart_tx_isr(ID siopid)
411	{
412	SIOPCB *p_siopcb = get_siopcb(siopid);
413
414	if((sil_reb_mem(
415	(void *)p_siopcb->p_siopinib->ssrreg) & SCI_SSR_TEND_BIT) != 0U){
416	/*
417	* MÂ\R[obN[`ðÄÑo·D
418	*/
419	rx630_uart_irdy_snd(p_siopcb->exinf);
420	}
421	}
422
423	void
424	rx630_uart_rx_isr(ID siopid)
425	{
426	SIOPCB *p_siopcb = get_siopcb(siopid);
427
428	/*
429	* óMtOªONÌÆ«ÌÝóMÊmR[obN[`ðÄÑo·.
430	* µ©µ, RX600V[YÅÍóMtOªÈ¢½ß, íÉóMÊm
431	* R[obN[`ðÄÑo·.
432	* ±±ÅÍóMÝÌ¶ðM¶é.
433	*/
434	/*
435	* óMÊmR[obN[`ðÄÑo·D
436	*/
437	rx630_uart_irdy_rcv(p_siopcb->exinf);
438	}
439
440
441	/*
442	* \|[gÔ©çÇubNÌæªÔnÖÌÏ·
443	*/
444	SIOPCB *
445	rx630_uart_get_siopcb(ID siopid) {
446	SIOPCB *p_siopcb = get_siopcb(siopid);
447	return(p_siopcb);
448	}
449
450	/*
451	* ÇubNÌæªÔn©çóMÝÔÖÌÏ·
452	*/
453	INTNO
454	rx630_uart_intno_rx(SIOPCB *p_siopcb) {
455	INTNO intno = p_siopcb->p_siopinib->rx_intno;
456	return(intno);
457	}
458
459	/*
460	* ÇubNÌæªÔn©çMÝÔÖÌÏ·
461	*/
462	INTNO
463	rx630_uart_intno_tx(SIOPCB *p_siopcb) {
464	INTNO intno = p_siopcb->p_siopinib->te_intno;
465	return(intno);
466	}

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