source: UsbWattMeter/trunk/asp_dcre/arch/rx630_msvc/rx630.h@ 164

Last change on this file since 164 was 164, checked in by coas-nagasima, 6 years ago

TOPPERS/ECNLサンプルアプリ「USB充電器電力計」を追加

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File size: 116.5 KB
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1/*
2 * TOPPERS/ASP Kernel
3 * Toyohashi Open Platform for Embedded Real-Time Systems/
4 * Advanced Standard Profile Kernel
5 *
6 * Copyright (C) 2008-2010 by Witz Corporation, JAPAN
7 * Copyright (C) 2013 by Mitsuhiro Matsuura
8 *
9 * ã‹L’˜ìŒ ŽÒ‚́CˆÈ‰º‚Ì(1)`(4)‚ÌðŒ‚ð–ž‚½‚·ê‡‚ÉŒÀ‚èC–{ƒ\ƒtƒgƒEƒF
10 * ƒAi–{ƒ\ƒtƒgƒEƒFƒA‚ð‰ü•Ï‚µ‚½‚à‚Ì‚ðŠÜ‚ށDˆÈ‰º“¯‚¶j‚ðŽg—pE•¡»E‰ü
11 * •ÏEÄ”z•ziˆÈ‰ºC—˜—p‚ƌĂԁj‚·‚邱‚Ƃ𖳏ž‚Å‹–‘ø‚·‚éD
12 * (1) –{ƒ\ƒtƒgƒEƒFƒA‚ðƒ\[ƒXƒR[ƒh‚ÌŒ`‚Å—˜—p‚·‚éê‡‚ɂ́Cã‹L‚Ì’˜ì
13 * Œ •\Ž¦C‚±‚Ì—˜—pðŒ‚¨‚æ‚щº‹L‚Ì–³•ÛØ‹K’肪C‚»‚Ì‚Ü‚Ü‚ÌŒ`‚Ń\[
14 * ƒXƒR[ƒh’†‚ÉŠÜ‚Ü‚ê‚Ä‚¢‚邱‚ƁD
15 * (2) –{ƒ\ƒtƒgƒEƒFƒA‚ðCƒ‰ƒCƒuƒ‰ƒŠŒ`Ž®‚ȂǁC‘¼‚̃\ƒtƒgƒEƒFƒAŠJ”­‚ÉŽg
16 * —p‚Å‚«‚éŒ`‚ōĔz•z‚·‚éê‡‚ɂ́CÄ”z•z‚É”º‚¤ƒhƒLƒ…
17ƒƒ“ƒgi—˜—p
18 * ŽÒƒ}ƒjƒ…
19ƒAƒ‹‚Ȃǁj‚ɁCã‹L‚Ì’˜ìŒ •\Ž¦C‚±‚Ì—˜—pðŒ‚¨‚æ‚щº‹L
20 * ‚Ì–³•ÛØ‹K’è‚ðŒfÚ‚·‚邱‚ƁD
21 * (3) –{ƒ\ƒtƒgƒEƒFƒA‚ðC‹@Ší‚É‘g‚ݍž‚ނȂǁC‘¼‚̃\ƒtƒgƒEƒFƒAŠJ”­‚ÉŽg
22 * —p‚Å‚«‚È‚¢Œ`‚ōĔz•z‚·‚éê‡‚ɂ́CŽŸ‚Ì‚¢‚¸‚ê‚©‚ÌðŒ‚ð–ž‚½‚·‚±
23 * ‚ƁD
24 * (a) Ä”z•z‚É”º‚¤ƒhƒLƒ…
25ƒƒ“ƒgi—˜—pŽÒƒ}ƒjƒ…
26ƒAƒ‹‚Ȃǁj‚ɁCã‹L‚Ì’˜
27 * ìŒ •\Ž¦C‚±‚Ì—˜—pðŒ‚¨‚æ‚щº‹L‚Ì–³•ÛØ‹K’è‚ðŒfÚ‚·‚邱‚ƁD
28 * (b) Ä”z•z‚ÌŒ`‘Ô‚ðC•Ê‚É’è‚ß‚é•û–@‚É‚æ‚Á‚āCTOPPERSƒvƒƒWƒFƒNƒg‚É
29 * •ñ‚·‚邱‚ƁD
30 * (4) –{ƒ\ƒtƒgƒEƒFƒA‚Ì—˜—p‚É‚æ‚è’¼Ú“I‚Ü‚½‚͊ԐړI‚ɐ¶‚¶‚é‚¢‚©‚Ȃ鑹
31 * ŠQ‚©‚ç‚àCã‹L’˜ìŒ ŽÒ‚¨‚æ‚ÑTOPPERSƒvƒƒWƒFƒNƒg‚ð–Ɛӂ·‚邱‚ƁD
32 * ‚Ü‚½C–{ƒ\ƒtƒgƒEƒFƒA‚̃†[ƒU‚Ü‚½‚̓Gƒ“ƒhƒ†[ƒU‚©‚ç‚Ì‚¢‚©‚Ȃ闝
33 * —R‚ÉŠî‚­¿‹‚©‚ç‚àCã‹L’˜ìŒ ŽÒ‚¨‚æ‚ÑTOPPERSƒvƒƒWƒFƒNƒg‚ð
34 * –Ɛӂ·‚邱‚ƁD
35 *
36 * –{ƒ\ƒtƒgƒEƒFƒA‚́C–³•ÛØ‚Å’ñ‹Ÿ‚³‚ê‚Ä‚¢‚é‚à‚Ì‚Å‚ ‚éDã‹L’˜ìŒ ŽÒ‚¨
37 * ‚æ‚ÑTOPPERSƒvƒƒWƒFƒNƒg‚́C–{ƒ\ƒtƒgƒEƒFƒA‚ÉŠÖ‚µ‚āC“Á’è‚ÌŽg—p–Ú“I
38 * ‚ɑ΂·‚é“K‡«‚àŠÜ‚߂āC‚¢‚©‚È‚é•ÛØ‚às‚í‚È‚¢D‚Ü‚½C–{ƒ\ƒtƒgƒEƒF
39 * ƒA‚Ì—˜—p‚É‚æ‚è’¼Ú“I‚Ü‚½‚͊ԐړI‚ɐ¶‚¶‚½‚¢‚©‚Ȃ鑹ŠQ‚ÉŠÖ‚µ‚Ä‚àC‚»
40 * ‚̐ӔC‚𕉂í‚È‚¢D
41 *
42 * @(#) $Id: rx630.h 164 2016-03-07 11:33:50Z coas-nagasima $
43 */
44
45/*
46 * RX630‚Ɉˑ¶‚·‚é’è‹`
47 */
48#ifndef TOPPERS_RX630_H
49#define TOPPERS_RX630_H
50
51/*
52 * CPU—áŠOƒnƒ“ƒhƒ‰”ԍ†‚Ì’è‹`(ŒÅ’èƒxƒNƒ^ƒe[ƒuƒ‹)
53 *
54 * ”ԍ†‚͈̔͂Í0 - 31
55 */
56#define INT_PRIVILEGED_INSTRUNCTION 20 /* “ÁŒ –½—ß—áŠO */
57#define INT_UNDEF_INSTRUNCTION 23 /* –¢’è‹`–½—ß—áŠO */
58#define INT_FLOATINGPOINT_INSTRUCTION 25 /* •‚“®¬”“_—áŠO */
59#define INT_NMI 30 /* ƒmƒ“ƒ}ƒXƒJƒuƒ‹Š„‚荞‚Ý */
60#define INT_RESET 31 /* ƒŠƒZƒbƒg */
61
62/*
63 * Š„ž‚ݔԍ†‚Ì’è‹`(‰Â•ÏƒxƒNƒ^ƒe[ƒuƒ‹)
64 */
65#define INT_BUSERR 16
66#define INT_FCU_FCUERR 21
67#define INT_FCU_FRDYI 23
68#define INT_ICU_SWINT 27
69#define INT_CMT0_CMI 28
70#define INT_CMT1_CMI 29
71#define INT_CMT2_CMI 30
72#define INT_CMT3_CMI 31
73#define INT_ETH_EINT 32
74#define INT_USB0_D0FIFO0 33
75#define INT_USB0_D1FIFO0 34
76#define INT_USB0_USBI0 35
77#define INT_USB1_D0FIFO1 36
78#define INT_USB1_D1FIFO1 37
79#define INT_USB1_USBI1 38
80#define INT_RSPI0_SPRI0 39
81#define INT_RSPI0_SPTI0 40
82#define INT_RSPI0_SPII0 41
83#define INT_RSPI1_SPRI1 42
84#define INT_RSPI1_SPTI1 43
85#define INT_RSPI1_SPII1 44
86#define INT_RSPI2_SPRI2 45
87#define INT_RSPI2_SPTI2 46
88#define INT_RSPI2_SPII2 47
89#define INT_CAN0_RXF0 48
90#define INT_CAN0_TXF0 49
91#define INT_CAN0_RXM0 50
92#define INT_CAN0_TXM0 51
93#define INT_CAN1_RXF1 52
94#define INT_CAN1_TXF1 53
95#define INT_CAN1_RXM1 54
96#define INT_CAN1_TXM1 55
97#define INT_CAN2_RXF2 56
98#define INT_CAN2_TXF2 57
99#define INT_CAN2_RXM2 58
100#define INT_CAN2_TXM2 59
101#define INT_RTC_CUP 62
102#define INT_IRQ0 64
103#define INT_IRQ1 65
104#define INT_IRQ2 66
105#define INT_IRQ3 67
106#define INT_IRQ4 68
107#define INT_IRQ5 69
108#define INT_IRQ6 70
109#define INT_IRQ7 71
110#define INT_IRQ8 72
111#define INT_IRQ9 73
112#define INT_IRQ10 74
113#define INT_IRQ11 75
114#define INT_IRQ12 76
115#define INT_IRQ13 77
116#define INT_IRQ14 78
117#define INT_IRQ15 79
118#define INT_USB_USBR0 90
119#define INT_USB_USBR1 91
120#define INT_RTC_ALM 92
121#define INT_RTC_PRD 93
122#define INT_AD0_ADI0 98
123#define INT_S12AD_S12ADI0 102
124#define INT_ICU_GROUP0 106
125#define INT_ICU_GROUP1 107
126#define INT_ICU_GROUP2 108
127#define INT_ICU_GROUP3 109
128#define INT_ICU_GROUP4 110
129#define INT_ICU_GROUP5 111
130#define INT_ICU_GROUP6 112
131#define INT_ICU_GROUP12 114
132#define INT_SCI12_SCIX0 122
133#define INT_SCI12_SCIX1 123
134#define INT_SCI12_SCIX2 124
135#define INT_SCI12_SCIX3 125
136#define INT_TPU0_TGI0A 126
137#define INT_TPU0_TGI0B 127
138#define INT_TPU0_TGI0C 128
139#define INT_TPU0_TGI0D 129
140#define INT_TPU1_TGI0A 130
141#define INT_TPU1_TGI0B 131
142#define INT_TPU2_TGI0A 132
143#define INT_TPU2_TGI0B 133
144#define INT_TPU3_TGI0A 134
145#define INT_TPU3_TGI0B 135
146#define INT_TPU3_TGI0C 136
147#define INT_TPU3_TGI0D 137
148#define INT_TPU4_TGI0A 138
149#define INT_TPU4_TGI0B 139
150#define INT_TPU5_TGI0A 140
151#define INT_TPU5_TGI0B 141
152#define INT_MTU0_TGIA0 142
153#define INT_MTU0_TGIB0 143
154#define INT_MTU0_TGIC0 144
155#define INT_MTU0_TGID0 145
156#define INT_MTU0_TCIE0 146
157#define INT_MTU0_TCIF0 147
158#define INT_MTU1_TGIA1 148
159#define INT_MTU1_TGIB1 149
160#define INT_MTU2_TGIA2 150
161#define INT_MTU2_TGIB2 151
162#define INT_MTU3_TGIA3 152
163#define INT_MTU3_TGIB3 153
164#define INT_MTU3_TGIC3 154
165#define INT_MTU3_TGID3 155
166#define INT_MTU4_TGIA4 156
167#define INT_MTU4_TGIB4 157
168#define INT_MTU4_TGIC4 158
169#define INT_MTU4_TGID4 159
170#define INT_MTU4_TCIV4 160
171#define INT_MTU5_TGIU5 161
172#define INT_MTU5_TGIV5 162
173#define INT_MTU5_TGIW5 163
174#define INT_MTU5_TGI11A 164
175#define INT_MTU5_TGI11B 165
176#define INT_POE_OEI1 166
177#define INT_POE_OEI2 167
178#define INT_TMR0_CMI0A 170
179#define INT_TMR0_CMI0B 171
180#define INT_TMR0_OV0I 172
181#define INT_TMR1_CMI1A 173
182#define INT_TMR1_CMI1B 174
183#define INT_TMR1_OV1I 175
184#define INT_TMR2_CMI2A 176
185#define INT_TMR2_CMI2B 177
186#define INT_TMR2_OV2I 178
187#define INT_TMR3_CMI3A 179
188#define INT_TMR3_CMI3B 180
189#define INT_TMR3_OV3I 181
190#define INT_RIIC0_EEI 182
191#define INT_RIIC0_RXI 183
192#define INT_RIIC0_TXI 184
193#define INT_RIIC0_TEI 185
194#define INT_RIIC1_EEI 186
195#define INT_RIIC1_RXI 187
196#define INT_RIIC1_TXI 188
197#define INT_RIIC1_TEI 189
198#define INT_RIIC2_EEI 190
199#define INT_RIIC2_RXI 191
200#define INT_RIIC2_TXI 192
201#define INT_RIIC2_TEI 193
202#define INT_RIIC3_EEI 194
203#define INT_RIIC3_RXI 195
204#define INT_RIIC3_TXI 196
205#define INT_RIIC3_TEI 197
206#define INT_DMAC_DMAC0I 198
207#define INT_DMAC_DMAC1I 199
208#define INT_DMAC_DMAC2I 200
209#define INT_DMAC_DMAC3I 201
210#define INT_SCI0_RXI 214
211#define INT_SCI0_TXI 215
212#define INT_SCI0_TEI 216
213#define INT_SCI1_RXI 217
214#define INT_SCI1_TXI 218
215#define INT_SCI1_TEI 219
216#define INT_SCI2_RXI 220
217#define INT_SCI2_TXI 221
218#define INT_SCI2_TEI 222
219#define INT_SCI3_RXI 223
220#define INT_SCI3_TXI 224
221#define INT_SCI3_TEI 225
222#define INT_SCI4_RXI 226
223#define INT_SCI4_TXI 227
224#define INT_SCI4_TEI 228
225#define INT_SCI5_RXI 229
226#define INT_SCI5_TXI 230
227#define INT_SCI5_TEI 231
228#define INT_SCI6_RXI 232
229#define INT_SCI6_TXI 233
230#define INT_SCI6_TEI 234
231#define INT_SCI7_RXI 235
232#define INT_SCI7_TXI 236
233#define INT_SCI7_TEI 237
234#define INT_SCI8_RXI 238
235#define INT_SCI8_TXI 239
236#define INT_SCI8_TEI 240
237#define INT_SCI9_RXI 241
238#define INT_SCI9_TXI 242
239#define INT_SCI9_TEI 243
240#define INT_SCI10_RXI 244
241#define INT_SCI10_TXI 245
242#define INT_SCI10_TEI 246
243#define INT_SCI11_RXI 247
244#define INT_SCI11_TXI 248
245#define INT_SCI11_TEI 249
246#define INT_SCI12_RXI 250
247#define INT_SCI12_TXI 251
248#define INT_SCI12_TEI 252
249#define INT_IEB_IEBINT 253
250
251/*
252 * Šeƒ‚ƒWƒ…
253[ƒ‹‚̃ŒƒWƒXƒ^‹y‚ѐݒèƒrƒbƒgî•ñ
254 */
255
256#define SYSTEM_SYSCR0_ADDR ( ( volatile uint16_t __evenaccess * )0x00080006 )
257
258/*
259 * ƒ‚ƒWƒ…
260[ƒ‹ƒXƒgƒbƒvƒRƒ“ƒgƒ[ƒ‹ƒŒƒWƒXƒ^AiMSTPCRAj
261 */
262#define SYSTEM_MSTPCRA_ADDR ( ( volatile uint32_t __evenaccess * )0x00080010 )
263#define SYSTEM_MSTPCRA_MSTPA0_BIT ( 1UL << 0U )
264#define SYSTEM_MSTPCRA_MSTPA1_BIT ( 1UL << 1U )
265#define SYSTEM_MSTPCRA_MSTPA2_BIT ( 1UL << 2U )
266#define SYSTEM_MSTPCRA_MSTPA3_BIT ( 1UL << 3U )
267#define SYSTEM_MSTPCRA_MSTPA4_BIT ( 1UL << 4U )
268#define SYSTEM_MSTPCRA_MSTPA5_BIT ( 1UL << 5U )
269#define SYSTEM_MSTPCRA_MSTPA6_BIT ( 1UL << 6U )
270#define SYSTEM_MSTPCRA_MSTPA7_BIT ( 1UL << 7U )
271#define SYSTEM_MSTPCRA_MSTPA8_BIT ( 1UL << 8U )
272#define SYSTEM_MSTPCRA_MSTPA9_BIT ( 1UL << 9U )
273#define SYSTEM_MSTPCRA_MSTPA10_BIT ( 1UL << 10U )
274#define SYSTEM_MSTPCRA_MSTPA11_BIT ( 1UL << 11U )
275#define SYSTEM_MSTPCRA_MSTPA12_BIT ( 1UL << 12U )
276#define SYSTEM_MSTPCRA_MSTPA13_BIT ( 1UL << 13U )
277#define SYSTEM_MSTPCRA_MSTPA14_BIT ( 1UL << 14U )
278#define SYSTEM_MSTPCRA_MSTPA15_BIT ( 1UL << 15U )
279#define SYSTEM_MSTPCRA_MSTPA16_BIT ( 1UL << 16U )
280#define SYSTEM_MSTPCRA_MSTPA17_BIT ( 1UL << 17U )
281#define SYSTEM_MSTPCRA_MSTPA18_BIT ( 1UL << 18U )
282#define SYSTEM_MSTPCRA_MSTPA19_BIT ( 1UL << 19U )
283#define SYSTEM_MSTPCRA_MSTPA20_BIT ( 1UL << 20U )
284#define SYSTEM_MSTPCRA_MSTPA21_BIT ( 1UL << 21U )
285#define SYSTEM_MSTPCRA_MSTPA22_BIT ( 1UL << 22U )
286#define SYSTEM_MSTPCRA_MSTPA23_BIT ( 1UL << 23U )
287#define SYSTEM_MSTPCRA_MSTPA24_BIT ( 1UL << 24U )
288#define SYSTEM_MSTPCRA_MSTPA25_BIT ( 1UL << 25U )
289#define SYSTEM_MSTPCRA_MSTPA26_BIT ( 1UL << 26U )
290#define SYSTEM_MSTPCRA_MSTPA27_BIT ( 1UL << 27U )
291#define SYSTEM_MSTPCRA_MSTPA28_BIT ( 1UL << 28U )
292#define SYSTEM_MSTPCRA_MSTPA29_BIT ( 1UL << 29U )
293#define SYSTEM_MSTPCRA_MSTPA30_BIT ( 1UL << 30U )
294#define SYSTEM_MSTPCRA_MSTPA31_BIT ( 1UL << 31U )
295#define SYSTEM_MSTPCRA_ACSE_BIT ( 1UL << 31U)
296
297/*
298 * ƒ‚ƒWƒ…
299[ƒ‹ƒXƒgƒbƒvƒRƒ“ƒgƒ[ƒ‹ƒŒƒWƒXƒ^BiMSTPCRBj
300 */
301#define SYSTEM_MSTPCRB_ADDR ( ( volatile uint32_t __evenaccess * )0x00080014 )
302#define SYSTEM_MSTPCRB_MSTPB0_BIT ( 1UL << 0U )
303#define SYSTEM_MSTPCRB_MSTPB1_BIT ( 1UL << 1U )
304#define SYSTEM_MSTPCRB_MSTPB2_BIT ( 1UL << 2U )
305#define SYSTEM_MSTPCRB_MSTPB3_BIT ( 1UL << 3U )
306#define SYSTEM_MSTPCRB_MSTPB4_BIT ( 1UL << 4U )
307#define SYSTEM_MSTPCRB_MSTPB5_BIT ( 1UL << 5U )
308#define SYSTEM_MSTPCRB_MSTPB6_BIT ( 1UL << 6U )
309#define SYSTEM_MSTPCRB_MSTPB7_BIT ( 1UL << 7U )
310#define SYSTEM_MSTPCRB_MSTPB8_BIT ( 1UL << 8U )
311#define SYSTEM_MSTPCRB_MSTPB9_BIT ( 1UL << 9U )
312#define SYSTEM_MSTPCRB_MSTPB10_BIT ( 1UL << 10U )
313#define SYSTEM_MSTPCRB_MSTPB11_BIT ( 1UL << 11U )
314#define SYSTEM_MSTPCRB_MSTPB12_BIT ( 1UL << 12U )
315#define SYSTEM_MSTPCRB_MSTPB13_BIT ( 1UL << 13U )
316#define SYSTEM_MSTPCRB_MSTPB14_BIT ( 1UL << 14U )
317#define SYSTEM_MSTPCRB_MSTPB15_BIT ( 1UL << 15U )
318#define SYSTEM_MSTPCRB_MSTPB16_BIT ( 1UL << 16U )
319#define SYSTEM_MSTPCRB_MSTPB17_BIT ( 1UL << 17U )
320#define SYSTEM_MSTPCRB_MSTPB18_BIT ( 1UL << 18U )
321#define SYSTEM_MSTPCRB_MSTPB19_BIT ( 1UL << 19U )
322#define SYSTEM_MSTPCRB_MSTPB20_BIT ( 1UL << 20U )
323#define SYSTEM_MSTPCRB_MSTPB21_BIT ( 1UL << 21U )
324#define SYSTEM_MSTPCRB_MSTPB22_BIT ( 1UL << 22U )
325#define SYSTEM_MSTPCRB_MSTPB23_BIT ( 1UL << 23U )
326#define SYSTEM_MSTPCRB_MSTPB24_BIT ( 1UL << 24U )
327#define SYSTEM_MSTPCRB_MSTPB25_BIT ( 1UL << 25U )
328#define SYSTEM_MSTPCRB_MSTPB26_BIT ( 1UL << 26U )
329#define SYSTEM_MSTPCRB_MSTPB27_BIT ( 1UL << 27U )
330#define SYSTEM_MSTPCRB_MSTPB28_BIT ( 1UL << 28U )
331#define SYSTEM_MSTPCRB_MSTPB29_BIT ( 1UL << 29U )
332#define SYSTEM_MSTPCRB_MSTPB30_BIT ( 1UL << 30U )
333#define SYSTEM_MSTPCRB_MSTPB31_BIT ( 1UL << 31U )
334
335/*
336 * ƒ‚ƒWƒ…
337[ƒ‹ƒXƒgƒbƒvƒRƒ“ƒgƒ[ƒ‹ƒŒƒWƒXƒ^CiMSTPCRCj
338 */
339#define SYSTEM_MSTPCRC_ADDR ( ( volatile uint32_t __evenaccess * )0x00080018 )
340#define SYSTEM_MSTPCRC_MSTPC0_BIT ( 1UL << 0U )
341#define SYSTEM_MSTPCRC_MSTPC1_BIT ( 1UL << 1U )
342#define SYSTEM_MSTPCRC_MSTPC2_BIT ( 1UL << 2U )
343#define SYSTEM_MSTPCRC_MSTPC3_BIT ( 1UL << 3U )
344#define SYSTEM_MSTPCRC_MSTPC4_BIT ( 1UL << 4U )
345#define SYSTEM_MSTPCRC_MSTPC5_BIT ( 1UL << 5U )
346#define SYSTEM_MSTPCRC_MSTPC6_BIT ( 1UL << 6U )
347#define SYSTEM_MSTPCRC_MSTPC7_BIT ( 1UL << 7U )
348#define SYSTEM_MSTPCRC_MSTPC8_BIT ( 1UL << 8U )
349#define SYSTEM_MSTPCRC_MSTPC9_BIT ( 1UL << 9U )
350#define SYSTEM_MSTPCRC_MSTPC10_BIT ( 1UL << 10U )
351#define SYSTEM_MSTPCRC_MSTPC11_BIT ( 1UL << 11U )
352#define SYSTEM_MSTPCRC_MSTPC12_BIT ( 1UL << 12U )
353#define SYSTEM_MSTPCRC_MSTPC13_BIT ( 1UL << 13U )
354#define SYSTEM_MSTPCRC_MSTPC14_BIT ( 1UL << 14U )
355#define SYSTEM_MSTPCRC_MSTPC15_BIT ( 1UL << 15U )
356#define SYSTEM_MSTPCRC_MSTPC16_BIT ( 1UL << 16U )
357#define SYSTEM_MSTPCRC_MSTPC17_BIT ( 1UL << 17U )
358#define SYSTEM_MSTPCRC_MSTPC18_BIT ( 1UL << 18U )
359#define SYSTEM_MSTPCRC_MSTPC19_BIT ( 1UL << 19U )
360#define SYSTEM_MSTPCRC_MSTPC20_BIT ( 1UL << 20U )
361#define SYSTEM_MSTPCRC_MSTPC21_BIT ( 1UL << 21U )
362#define SYSTEM_MSTPCRC_MSTPC22_BIT ( 1UL << 22U )
363#define SYSTEM_MSTPCRC_MSTPC23_BIT ( 1UL << 23U )
364#define SYSTEM_MSTPCRC_MSTPC24_BIT ( 1UL << 24U )
365#define SYSTEM_MSTPCRC_MSTPC25_BIT ( 1UL << 25U )
366#define SYSTEM_MSTPCRC_MSTPC26_BIT ( 1UL << 26U )
367#define SYSTEM_MSTPCRC_MSTPC27_BIT ( 1UL << 27U )
368#define SYSTEM_MSTPCRC_MSTPC28_BIT ( 1UL << 28U )
369#define SYSTEM_MSTPCRC_MSTPC29_BIT ( 1UL << 29U )
370#define SYSTEM_MSTPCRC_MSTPC30_BIT ( 1UL << 30U )
371#define SYSTEM_MSTPCRC_MSTPC31_BIT ( 1UL << 31U )
372
373/*
374 * ƒNƒƒbƒN”­¶‰ñ˜H
375 */
376#define SYSTEM_SCKCR_ADDR ( ( volatile uint32_t __evenaccess * )0x00080020 )
377#define SYSTEM_SCKCR2_ADDR ( ( volatile uint16_t __evenaccess * )0x00080024 )
378#define SYSTEM_SCKCR2_UCK_OFFSET ( 4U )
379#define SYSTEM_SCKCR2_UCK_MASK ( 0xFU << SYSTEM_SCKCR2_UCK_OFFSET )
380#define SYSTEM_SCKCR3_ADDR ( ( volatile uint16_t __evenaccess * )0x00080026 )
381#define SYSTEM_SCKCR3_CKSEL_OFFSET ( 8U )
382#define SYSTEM_SCKCR3_CKSEL_MASK ( 0x7U << SYSTEM_SCKCR3_CKSEL_OFFSET )
383#define SYSTEM_PLLCR_ADDR ( ( volatile uint16_t __evenaccess * )0x00080028 )
384#define SYSTEM_PLLCR_STC_OFFSET ( 8U )
385#define SYSTEM_PLLCR_STC_MASK ( 0x3FU << SYSTEM_PLLCR_STC_OFFSET )
386#define SYSTEM_PLLCR2_ADDR ( ( volatile uint8_t __evenaccess * )0x0008002A )
387#define SYSTEM_PLLCR2_PLLEN ( 1UL << 0U )
388#define SYSTEM_MOFCR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C293 )
389#define SYSTEM_MOFCR_MOFXIN ( 1UL << 0U )
390#define SYSTEM_MOSCCR_ADDR ( ( volatile uint8_t __evenaccess * )0x00080032 )
391#define SYSTEM_MOSCCR_MOSTP ( 1UL << 0U )
392
393/*
394 * ƒvƒƒeƒNƒgƒŒƒWƒXƒ^
395 */
396#define SYSTEM_PRCR_ADDR ( ( volatile uint16_t __evenaccess * )0x000803FE )
397
398/*
399 * Š„‚荞‚Ý—v‹ƒŒƒWƒXƒ^
400 */
401#define ICU_IR000_ADDR ( ( volatile uint8_t __evenaccess * )0x00087000 )
402#define ICU_IR001_ADDR ( ( volatile uint8_t __evenaccess * )0x00087001 )
403#define ICU_IR002_ADDR ( ( volatile uint8_t __evenaccess * )0x00087002 )
404#define ICU_IR003_ADDR ( ( volatile uint8_t __evenaccess * )0x00087003 )
405#define ICU_IR004_ADDR ( ( volatile uint8_t __evenaccess * )0x00087004 )
406#define ICU_IR005_ADDR ( ( volatile uint8_t __evenaccess * )0x00087005 )
407#define ICU_IR006_ADDR ( ( volatile uint8_t __evenaccess * )0x00087006 )
408#define ICU_IR007_ADDR ( ( volatile uint8_t __evenaccess * )0x00087007 )
409#define ICU_IR008_ADDR ( ( volatile uint8_t __evenaccess * )0x00087008 )
410#define ICU_IR009_ADDR ( ( volatile uint8_t __evenaccess * )0x00087009 )
411#define ICU_IR010_ADDR ( ( volatile uint8_t __evenaccess * )0x0008700A )
412#define ICU_IR011_ADDR ( ( volatile uint8_t __evenaccess * )0x0008700B )
413#define ICU_IR012_ADDR ( ( volatile uint8_t __evenaccess * )0x0008700C )
414#define ICU_IR013_ADDR ( ( volatile uint8_t __evenaccess * )0x0008700D )
415#define ICU_IR014_ADDR ( ( volatile uint8_t __evenaccess * )0x0008700E )
416#define ICU_IR015_ADDR ( ( volatile uint8_t __evenaccess * )0x0008700F )
417#define ICU_IR016_ADDR ( ( volatile uint8_t __evenaccess * )0x00087010 )
418#define ICU_IR017_ADDR ( ( volatile uint8_t __evenaccess * )0x00087011 )
419#define ICU_IR018_ADDR ( ( volatile uint8_t __evenaccess * )0x00087012 )
420#define ICU_IR019_ADDR ( ( volatile uint8_t __evenaccess * )0x00087013 )
421#define ICU_IR020_ADDR ( ( volatile uint8_t __evenaccess * )0x00087014 )
422#define ICU_IR021_ADDR ( ( volatile uint8_t __evenaccess * )0x00087015 )
423#define ICU_IR022_ADDR ( ( volatile uint8_t __evenaccess * )0x00087016 )
424#define ICU_IR023_ADDR ( ( volatile uint8_t __evenaccess * )0x00087017 )
425#define ICU_IR024_ADDR ( ( volatile uint8_t __evenaccess * )0x00087018 )
426#define ICU_IR025_ADDR ( ( volatile uint8_t __evenaccess * )0x00087019 )
427#define ICU_IR026_ADDR ( ( volatile uint8_t __evenaccess * )0x0008701A )
428#define ICU_IR027_ADDR ( ( volatile uint8_t __evenaccess * )0x0008701B )
429#define ICU_IR028_ADDR ( ( volatile uint8_t __evenaccess * )0x0008701C )
430#define ICU_IR029_ADDR ( ( volatile uint8_t __evenaccess * )0x0008701D )
431#define ICU_IR030_ADDR ( ( volatile uint8_t __evenaccess * )0x0008701E )
432#define ICU_IR031_ADDR ( ( volatile uint8_t __evenaccess * )0x0008701F )
433#define ICU_IR032_ADDR ( ( volatile uint8_t __evenaccess * )0x00087020 )
434#define ICU_IR033_ADDR ( ( volatile uint8_t __evenaccess * )0x00087021 )
435#define ICU_IR034_ADDR ( ( volatile uint8_t __evenaccess * )0x00087022 )
436#define ICU_IR035_ADDR ( ( volatile uint8_t __evenaccess * )0x00087023 )
437#define ICU_IR036_ADDR ( ( volatile uint8_t __evenaccess * )0x00087024 )
438#define ICU_IR037_ADDR ( ( volatile uint8_t __evenaccess * )0x00087025 )
439#define ICU_IR038_ADDR ( ( volatile uint8_t __evenaccess * )0x00087026 )
440#define ICU_IR039_ADDR ( ( volatile uint8_t __evenaccess * )0x00087027 )
441#define ICU_IR040_ADDR ( ( volatile uint8_t __evenaccess * )0x00087028 )
442#define ICU_IR041_ADDR ( ( volatile uint8_t __evenaccess * )0x00087029 )
443#define ICU_IR042_ADDR ( ( volatile uint8_t __evenaccess * )0x0008702A )
444#define ICU_IR043_ADDR ( ( volatile uint8_t __evenaccess * )0x0008702B )
445#define ICU_IR044_ADDR ( ( volatile uint8_t __evenaccess * )0x0008702C )
446#define ICU_IR045_ADDR ( ( volatile uint8_t __evenaccess * )0x0008702D )
447#define ICU_IR046_ADDR ( ( volatile uint8_t __evenaccess * )0x0008702E )
448#define ICU_IR047_ADDR ( ( volatile uint8_t __evenaccess * )0x0008702F )
449#define ICU_IR048_ADDR ( ( volatile uint8_t __evenaccess * )0x00087030 )
450#define ICU_IR049_ADDR ( ( volatile uint8_t __evenaccess * )0x00087031 )
451#define ICU_IR050_ADDR ( ( volatile uint8_t __evenaccess * )0x00087032 )
452#define ICU_IR051_ADDR ( ( volatile uint8_t __evenaccess * )0x00087033 )
453#define ICU_IR052_ADDR ( ( volatile uint8_t __evenaccess * )0x00087034 )
454#define ICU_IR053_ADDR ( ( volatile uint8_t __evenaccess * )0x00087035 )
455#define ICU_IR054_ADDR ( ( volatile uint8_t __evenaccess * )0x00087036 )
456#define ICU_IR055_ADDR ( ( volatile uint8_t __evenaccess * )0x00087037 )
457#define ICU_IR056_ADDR ( ( volatile uint8_t __evenaccess * )0x00087038 )
458#define ICU_IR057_ADDR ( ( volatile uint8_t __evenaccess * )0x00087039 )
459#define ICU_IR058_ADDR ( ( volatile uint8_t __evenaccess * )0x0008703A )
460#define ICU_IR059_ADDR ( ( volatile uint8_t __evenaccess * )0x0008703B )
461#define ICU_IR060_ADDR ( ( volatile uint8_t __evenaccess * )0x0008703C )
462#define ICU_IR061_ADDR ( ( volatile uint8_t __evenaccess * )0x0008703D )
463#define ICU_IR062_ADDR ( ( volatile uint8_t __evenaccess * )0x0008703E )
464#define ICU_IR063_ADDR ( ( volatile uint8_t __evenaccess * )0x0008703F )
465#define ICU_IR064_ADDR ( ( volatile uint8_t __evenaccess * )0x00087040 )
466#define ICU_IR065_ADDR ( ( volatile uint8_t __evenaccess * )0x00087041 )
467#define ICU_IR066_ADDR ( ( volatile uint8_t __evenaccess * )0x00087042 )
468#define ICU_IR067_ADDR ( ( volatile uint8_t __evenaccess * )0x00087043 )
469#define ICU_IR068_ADDR ( ( volatile uint8_t __evenaccess * )0x00087044 )
470#define ICU_IR069_ADDR ( ( volatile uint8_t __evenaccess * )0x00087045 )
471#define ICU_IR070_ADDR ( ( volatile uint8_t __evenaccess * )0x00087046 )
472#define ICU_IR071_ADDR ( ( volatile uint8_t __evenaccess * )0x00087047 )
473#define ICU_IR072_ADDR ( ( volatile uint8_t __evenaccess * )0x00087048 )
474#define ICU_IR073_ADDR ( ( volatile uint8_t __evenaccess * )0x00087049 )
475#define ICU_IR074_ADDR ( ( volatile uint8_t __evenaccess * )0x0008704A )
476#define ICU_IR075_ADDR ( ( volatile uint8_t __evenaccess * )0x0008704B )
477#define ICU_IR076_ADDR ( ( volatile uint8_t __evenaccess * )0x0008704C )
478#define ICU_IR077_ADDR ( ( volatile uint8_t __evenaccess * )0x0008704D )
479#define ICU_IR078_ADDR ( ( volatile uint8_t __evenaccess * )0x0008704E )
480#define ICU_IR079_ADDR ( ( volatile uint8_t __evenaccess * )0x0008704F )
481#define ICU_IR080_ADDR ( ( volatile uint8_t __evenaccess * )0x00087050 )
482#define ICU_IR081_ADDR ( ( volatile uint8_t __evenaccess * )0x00087051 )
483#define ICU_IR082_ADDR ( ( volatile uint8_t __evenaccess * )0x00087052 )
484#define ICU_IR083_ADDR ( ( volatile uint8_t __evenaccess * )0x00087053 )
485#define ICU_IR084_ADDR ( ( volatile uint8_t __evenaccess * )0x00087054 )
486#define ICU_IR085_ADDR ( ( volatile uint8_t __evenaccess * )0x00087055 )
487#define ICU_IR086_ADDR ( ( volatile uint8_t __evenaccess * )0x00087056 )
488#define ICU_IR087_ADDR ( ( volatile uint8_t __evenaccess * )0x00087057 )
489#define ICU_IR088_ADDR ( ( volatile uint8_t __evenaccess * )0x00087058 )
490#define ICU_IR089_ADDR ( ( volatile uint8_t __evenaccess * )0x00087059 )
491#define ICU_IR090_ADDR ( ( volatile uint8_t __evenaccess * )0x0008705A )
492#define ICU_IR091_ADDR ( ( volatile uint8_t __evenaccess * )0x0008705B )
493#define ICU_IR092_ADDR ( ( volatile uint8_t __evenaccess * )0x0008705C )
494#define ICU_IR093_ADDR ( ( volatile uint8_t __evenaccess * )0x0008705D )
495#define ICU_IR094_ADDR ( ( volatile uint8_t __evenaccess * )0x0008705E )
496#define ICU_IR095_ADDR ( ( volatile uint8_t __evenaccess * )0x0008705F )
497#define ICU_IR096_ADDR ( ( volatile uint8_t __evenaccess * )0x00087060 )
498#define ICU_IR097_ADDR ( ( volatile uint8_t __evenaccess * )0x00087061 )
499#define ICU_IR098_ADDR ( ( volatile uint8_t __evenaccess * )0x00087062 )
500#define ICU_IR099_ADDR ( ( volatile uint8_t __evenaccess * )0x00087063 )
501#define ICU_IR100_ADDR ( ( volatile uint8_t __evenaccess * )0x00087064 )
502#define ICU_IR101_ADDR ( ( volatile uint8_t __evenaccess * )0x00087065 )
503#define ICU_IR102_ADDR ( ( volatile uint8_t __evenaccess * )0x00087066 )
504#define ICU_IR103_ADDR ( ( volatile uint8_t __evenaccess * )0x00087067 )
505#define ICU_IR104_ADDR ( ( volatile uint8_t __evenaccess * )0x00087068 )
506#define ICU_IR105_ADDR ( ( volatile uint8_t __evenaccess * )0x00087069 )
507#define ICU_IR106_ADDR ( ( volatile uint8_t __evenaccess * )0x0008706A )
508#define ICU_IR107_ADDR ( ( volatile uint8_t __evenaccess * )0x0008706B )
509#define ICU_IR108_ADDR ( ( volatile uint8_t __evenaccess * )0x0008706C )
510#define ICU_IR109_ADDR ( ( volatile uint8_t __evenaccess * )0x0008706D )
511#define ICU_IR110_ADDR ( ( volatile uint8_t __evenaccess * )0x0008706E )
512#define ICU_IR111_ADDR ( ( volatile uint8_t __evenaccess * )0x0008706F )
513#define ICU_IR112_ADDR ( ( volatile uint8_t __evenaccess * )0x00087070 )
514#define ICU_IR113_ADDR ( ( volatile uint8_t __evenaccess * )0x00087071 )
515#define ICU_IR114_ADDR ( ( volatile uint8_t __evenaccess * )0x00087072 )
516#define ICU_IR115_ADDR ( ( volatile uint8_t __evenaccess * )0x00087073 )
517#define ICU_IR116_ADDR ( ( volatile uint8_t __evenaccess * )0x00087074 )
518#define ICU_IR117_ADDR ( ( volatile uint8_t __evenaccess * )0x00087075 )
519#define ICU_IR118_ADDR ( ( volatile uint8_t __evenaccess * )0x00087076 )
520#define ICU_IR119_ADDR ( ( volatile uint8_t __evenaccess * )0x00087077 )
521#define ICU_IR120_ADDR ( ( volatile uint8_t __evenaccess * )0x00087078 )
522#define ICU_IR121_ADDR ( ( volatile uint8_t __evenaccess * )0x00087079 )
523#define ICU_IR122_ADDR ( ( volatile uint8_t __evenaccess * )0x0008707A )
524#define ICU_IR123_ADDR ( ( volatile uint8_t __evenaccess * )0x0008707B )
525#define ICU_IR124_ADDR ( ( volatile uint8_t __evenaccess * )0x0008707C )
526#define ICU_IR125_ADDR ( ( volatile uint8_t __evenaccess * )0x0008707D )
527#define ICU_IR126_ADDR ( ( volatile uint8_t __evenaccess * )0x0008707E )
528#define ICU_IR127_ADDR ( ( volatile uint8_t __evenaccess * )0x0008707F )
529#define ICU_IR128_ADDR ( ( volatile uint8_t __evenaccess * )0x00087080 )
530#define ICU_IR129_ADDR ( ( volatile uint8_t __evenaccess * )0x00087081 )
531#define ICU_IR130_ADDR ( ( volatile uint8_t __evenaccess * )0x00087082 )
532#define ICU_IR131_ADDR ( ( volatile uint8_t __evenaccess * )0x00087083 )
533#define ICU_IR132_ADDR ( ( volatile uint8_t __evenaccess * )0x00087084 )
534#define ICU_IR133_ADDR ( ( volatile uint8_t __evenaccess * )0x00087085 )
535#define ICU_IR134_ADDR ( ( volatile uint8_t __evenaccess * )0x00087086 )
536#define ICU_IR135_ADDR ( ( volatile uint8_t __evenaccess * )0x00087087 )
537#define ICU_IR136_ADDR ( ( volatile uint8_t __evenaccess * )0x00087088 )
538#define ICU_IR137_ADDR ( ( volatile uint8_t __evenaccess * )0x00087089 )
539#define ICU_IR138_ADDR ( ( volatile uint8_t __evenaccess * )0x0008708A )
540#define ICU_IR139_ADDR ( ( volatile uint8_t __evenaccess * )0x0008708B )
541#define ICU_IR140_ADDR ( ( volatile uint8_t __evenaccess * )0x0008708C )
542#define ICU_IR141_ADDR ( ( volatile uint8_t __evenaccess * )0x0008708D )
543#define ICU_IR142_ADDR ( ( volatile uint8_t __evenaccess * )0x0008708E )
544#define ICU_IR143_ADDR ( ( volatile uint8_t __evenaccess * )0x0008708F )
545#define ICU_IR144_ADDR ( ( volatile uint8_t __evenaccess * )0x00087090 )
546#define ICU_IR145_ADDR ( ( volatile uint8_t __evenaccess * )0x00087091 )
547#define ICU_IR146_ADDR ( ( volatile uint8_t __evenaccess * )0x00087092 )
548#define ICU_IR147_ADDR ( ( volatile uint8_t __evenaccess * )0x00087093 )
549#define ICU_IR148_ADDR ( ( volatile uint8_t __evenaccess * )0x00087094 )
550#define ICU_IR149_ADDR ( ( volatile uint8_t __evenaccess * )0x00087095 )
551#define ICU_IR150_ADDR ( ( volatile uint8_t __evenaccess * )0x00087096 )
552#define ICU_IR151_ADDR ( ( volatile uint8_t __evenaccess * )0x00087097 )
553#define ICU_IR152_ADDR ( ( volatile uint8_t __evenaccess * )0x00087098 )
554#define ICU_IR153_ADDR ( ( volatile uint8_t __evenaccess * )0x00087099 )
555#define ICU_IR154_ADDR ( ( volatile uint8_t __evenaccess * )0x0008709A )
556#define ICU_IR155_ADDR ( ( volatile uint8_t __evenaccess * )0x0008709B )
557#define ICU_IR156_ADDR ( ( volatile uint8_t __evenaccess * )0x0008709C )
558#define ICU_IR157_ADDR ( ( volatile uint8_t __evenaccess * )0x0008709D )
559#define ICU_IR158_ADDR ( ( volatile uint8_t __evenaccess * )0x0008709E )
560#define ICU_IR159_ADDR ( ( volatile uint8_t __evenaccess * )0x0008709F )
561#define ICU_IR160_ADDR ( ( volatile uint8_t __evenaccess * )0x000870A0 )
562#define ICU_IR161_ADDR ( ( volatile uint8_t __evenaccess * )0x000870A1 )
563#define ICU_IR162_ADDR ( ( volatile uint8_t __evenaccess * )0x000870A2 )
564#define ICU_IR163_ADDR ( ( volatile uint8_t __evenaccess * )0x000870A3 )
565#define ICU_IR164_ADDR ( ( volatile uint8_t __evenaccess * )0x000870A4 )
566#define ICU_IR165_ADDR ( ( volatile uint8_t __evenaccess * )0x000870A5 )
567#define ICU_IR166_ADDR ( ( volatile uint8_t __evenaccess * )0x000870A6 )
568#define ICU_IR167_ADDR ( ( volatile uint8_t __evenaccess * )0x000870A7 )
569#define ICU_IR168_ADDR ( ( volatile uint8_t __evenaccess * )0x000870A8 )
570#define ICU_IR169_ADDR ( ( volatile uint8_t __evenaccess * )0x000870A9 )
571#define ICU_IR170_ADDR ( ( volatile uint8_t __evenaccess * )0x000870AA )
572#define ICU_IR171_ADDR ( ( volatile uint8_t __evenaccess * )0x000870AB )
573#define ICU_IR172_ADDR ( ( volatile uint8_t __evenaccess * )0x000870AC )
574#define ICU_IR173_ADDR ( ( volatile uint8_t __evenaccess * )0x000870AD )
575#define ICU_IR174_ADDR ( ( volatile uint8_t __evenaccess * )0x000870AE )
576#define ICU_IR175_ADDR ( ( volatile uint8_t __evenaccess * )0x000870AF )
577#define ICU_IR176_ADDR ( ( volatile uint8_t __evenaccess * )0x000870B0 )
578#define ICU_IR177_ADDR ( ( volatile uint8_t __evenaccess * )0x000870B1 )
579#define ICU_IR178_ADDR ( ( volatile uint8_t __evenaccess * )0x000870B2 )
580#define ICU_IR179_ADDR ( ( volatile uint8_t __evenaccess * )0x000870B3 )
581#define ICU_IR180_ADDR ( ( volatile uint8_t __evenaccess * )0x000870B4 )
582#define ICU_IR181_ADDR ( ( volatile uint8_t __evenaccess * )0x000870B5 )
583#define ICU_IR182_ADDR ( ( volatile uint8_t __evenaccess * )0x000870B6 )
584#define ICU_IR183_ADDR ( ( volatile uint8_t __evenaccess * )0x000870B7 )
585#define ICU_IR184_ADDR ( ( volatile uint8_t __evenaccess * )0x000870B8 )
586#define ICU_IR185_ADDR ( ( volatile uint8_t __evenaccess * )0x000870B9 )
587#define ICU_IR186_ADDR ( ( volatile uint8_t __evenaccess * )0x000870BA )
588#define ICU_IR187_ADDR ( ( volatile uint8_t __evenaccess * )0x000870BB )
589#define ICU_IR188_ADDR ( ( volatile uint8_t __evenaccess * )0x000870BC )
590#define ICU_IR189_ADDR ( ( volatile uint8_t __evenaccess * )0x000870BD )
591#define ICU_IR190_ADDR ( ( volatile uint8_t __evenaccess * )0x000870BE )
592#define ICU_IR191_ADDR ( ( volatile uint8_t __evenaccess * )0x000870BF )
593#define ICU_IR192_ADDR ( ( volatile uint8_t __evenaccess * )0x000870C0 )
594#define ICU_IR193_ADDR ( ( volatile uint8_t __evenaccess * )0x000870C1 )
595#define ICU_IR194_ADDR ( ( volatile uint8_t __evenaccess * )0x000870C2 )
596#define ICU_IR195_ADDR ( ( volatile uint8_t __evenaccess * )0x000870C3 )
597#define ICU_IR196_ADDR ( ( volatile uint8_t __evenaccess * )0x000870C4 )
598#define ICU_IR197_ADDR ( ( volatile uint8_t __evenaccess * )0x000870C5 )
599#define ICU_IR198_ADDR ( ( volatile uint8_t __evenaccess * )0x000870C6 )
600#define ICU_IR199_ADDR ( ( volatile uint8_t __evenaccess * )0x000870C7 )
601#define ICU_IR200_ADDR ( ( volatile uint8_t __evenaccess * )0x000870C8 )
602#define ICU_IR201_ADDR ( ( volatile uint8_t __evenaccess * )0x000870C9 )
603#define ICU_IR202_ADDR ( ( volatile uint8_t __evenaccess * )0x000870CA )
604#define ICU_IR203_ADDR ( ( volatile uint8_t __evenaccess * )0x000870CB )
605#define ICU_IR204_ADDR ( ( volatile uint8_t __evenaccess * )0x000870CC )
606#define ICU_IR205_ADDR ( ( volatile uint8_t __evenaccess * )0x000870CD )
607#define ICU_IR206_ADDR ( ( volatile uint8_t __evenaccess * )0x000870CE )
608#define ICU_IR207_ADDR ( ( volatile uint8_t __evenaccess * )0x000870CF )
609#define ICU_IR208_ADDR ( ( volatile uint8_t __evenaccess * )0x000870D0 )
610#define ICU_IR209_ADDR ( ( volatile uint8_t __evenaccess * )0x000870D1 )
611#define ICU_IR210_ADDR ( ( volatile uint8_t __evenaccess * )0x000870D2 )
612#define ICU_IR211_ADDR ( ( volatile uint8_t __evenaccess * )0x000870D3 )
613#define ICU_IR212_ADDR ( ( volatile uint8_t __evenaccess * )0x000870D4 )
614#define ICU_IR213_ADDR ( ( volatile uint8_t __evenaccess * )0x000870D5 )
615#define ICU_IR214_ADDR ( ( volatile uint8_t __evenaccess * )0x000870D6 )
616#define ICU_IR215_ADDR ( ( volatile uint8_t __evenaccess * )0x000870D7 )
617#define ICU_IR216_ADDR ( ( volatile uint8_t __evenaccess * )0x000870D8 )
618#define ICU_IR217_ADDR ( ( volatile uint8_t __evenaccess * )0x000870D9 )
619#define ICU_IR218_ADDR ( ( volatile uint8_t __evenaccess * )0x000870DA )
620#define ICU_IR219_ADDR ( ( volatile uint8_t __evenaccess * )0x000870DB )
621#define ICU_IR220_ADDR ( ( volatile uint8_t __evenaccess * )0x000870DC )
622#define ICU_IR221_ADDR ( ( volatile uint8_t __evenaccess * )0x000870DD )
623#define ICU_IR222_ADDR ( ( volatile uint8_t __evenaccess * )0x000870DE )
624#define ICU_IR223_ADDR ( ( volatile uint8_t __evenaccess * )0x000870DF )
625#define ICU_IR224_ADDR ( ( volatile uint8_t __evenaccess * )0x000870E0 )
626#define ICU_IR225_ADDR ( ( volatile uint8_t __evenaccess * )0x000870E1 )
627#define ICU_IR226_ADDR ( ( volatile uint8_t __evenaccess * )0x000870E2 )
628#define ICU_IR227_ADDR ( ( volatile uint8_t __evenaccess * )0x000870E3 )
629#define ICU_IR228_ADDR ( ( volatile uint8_t __evenaccess * )0x000870E4 )
630#define ICU_IR229_ADDR ( ( volatile uint8_t __evenaccess * )0x000870E5 )
631#define ICU_IR230_ADDR ( ( volatile uint8_t __evenaccess * )0x000870E6 )
632#define ICU_IR231_ADDR ( ( volatile uint8_t __evenaccess * )0x000870E7 )
633#define ICU_IR232_ADDR ( ( volatile uint8_t __evenaccess * )0x000870E8 )
634#define ICU_IR233_ADDR ( ( volatile uint8_t __evenaccess * )0x000870E9 )
635#define ICU_IR234_ADDR ( ( volatile uint8_t __evenaccess * )0x000870EA )
636#define ICU_IR235_ADDR ( ( volatile uint8_t __evenaccess * )0x000870EB )
637#define ICU_IR236_ADDR ( ( volatile uint8_t __evenaccess * )0x000870EC )
638#define ICU_IR237_ADDR ( ( volatile uint8_t __evenaccess * )0x000870ED )
639#define ICU_IR238_ADDR ( ( volatile uint8_t __evenaccess * )0x000870EE )
640#define ICU_IR239_ADDR ( ( volatile uint8_t __evenaccess * )0x000870EF )
641#define ICU_IR240_ADDR ( ( volatile uint8_t __evenaccess * )0x000870F0 )
642#define ICU_IR241_ADDR ( ( volatile uint8_t __evenaccess * )0x000870F1 )
643#define ICU_IR242_ADDR ( ( volatile uint8_t __evenaccess * )0x000870F2 )
644#define ICU_IR243_ADDR ( ( volatile uint8_t __evenaccess * )0x000870F3 )
645#define ICU_IR244_ADDR ( ( volatile uint8_t __evenaccess * )0x000870F4 )
646#define ICU_IR245_ADDR ( ( volatile uint8_t __evenaccess * )0x000870F5 )
647#define ICU_IR246_ADDR ( ( volatile uint8_t __evenaccess * )0x000870F6 )
648#define ICU_IR247_ADDR ( ( volatile uint8_t __evenaccess * )0x000870F7 )
649#define ICU_IR248_ADDR ( ( volatile uint8_t __evenaccess * )0x000870F8 )
650#define ICU_IR249_ADDR ( ( volatile uint8_t __evenaccess * )0x000870F9 )
651#define ICU_IR250_ADDR ( ( volatile uint8_t __evenaccess * )0x000870FA )
652#define ICU_IR251_ADDR ( ( volatile uint8_t __evenaccess * )0x000870FB )
653#define ICU_IR252_ADDR ( ( volatile uint8_t __evenaccess * )0x000870FC )
654#define ICU_IR253_ADDR ( ( volatile uint8_t __evenaccess * )0x000870FD )
655#define ICU_IR254_ADDR ( ( volatile uint8_t __evenaccess * )0x000870FE )
656#define ICU_IR255_ADDR ( ( volatile uint8_t __evenaccess * )0x000870FF )
657#define ICU_IR_BIT ( 1U << 0U )
658
659/*
660 * Š„‚荞‚Ý—v‹æÝ’背ƒWƒXƒ^
661 */
662#define ICU_ISELR000_ADDR ( ( volatile uint8_t __evenaccess * )0x00087100 )
663#define ICU_ISELR001_ADDR ( ( volatile uint8_t __evenaccess * )0x00087101 )
664#define ICU_ISELR002_ADDR ( ( volatile uint8_t __evenaccess * )0x00087102 )
665#define ICU_ISELR003_ADDR ( ( volatile uint8_t __evenaccess * )0x00087103 )
666#define ICU_ISELR004_ADDR ( ( volatile uint8_t __evenaccess * )0x00087104 )
667#define ICU_ISELR005_ADDR ( ( volatile uint8_t __evenaccess * )0x00087105 )
668#define ICU_ISELR006_ADDR ( ( volatile uint8_t __evenaccess * )0x00087106 )
669#define ICU_ISELR007_ADDR ( ( volatile uint8_t __evenaccess * )0x00087107 )
670#define ICU_ISELR008_ADDR ( ( volatile uint8_t __evenaccess * )0x00087108 )
671#define ICU_ISELR009_ADDR ( ( volatile uint8_t __evenaccess * )0x00087109 )
672#define ICU_ISELR010_ADDR ( ( volatile uint8_t __evenaccess * )0x0008710A )
673#define ICU_ISELR011_ADDR ( ( volatile uint8_t __evenaccess * )0x0008710B )
674#define ICU_ISELR012_ADDR ( ( volatile uint8_t __evenaccess * )0x0008710C )
675#define ICU_ISELR013_ADDR ( ( volatile uint8_t __evenaccess * )0x0008710D )
676#define ICU_ISELR014_ADDR ( ( volatile uint8_t __evenaccess * )0x0008710E )
677#define ICU_ISELR015_ADDR ( ( volatile uint8_t __evenaccess * )0x0008710F )
678#define ICU_ISELR016_ADDR ( ( volatile uint8_t __evenaccess * )0x00087110 )
679#define ICU_ISELR017_ADDR ( ( volatile uint8_t __evenaccess * )0x00087111 )
680#define ICU_ISELR018_ADDR ( ( volatile uint8_t __evenaccess * )0x00087112 )
681#define ICU_ISELR019_ADDR ( ( volatile uint8_t __evenaccess * )0x00087113 )
682#define ICU_ISELR020_ADDR ( ( volatile uint8_t __evenaccess * )0x00087114 )
683#define ICU_ISELR021_ADDR ( ( volatile uint8_t __evenaccess * )0x00087115 )
684#define ICU_ISELR022_ADDR ( ( volatile uint8_t __evenaccess * )0x00087116 )
685#define ICU_ISELR023_ADDR ( ( volatile uint8_t __evenaccess * )0x00087117 )
686#define ICU_ISELR024_ADDR ( ( volatile uint8_t __evenaccess * )0x00087118 )
687#define ICU_ISELR025_ADDR ( ( volatile uint8_t __evenaccess * )0x00087119 )
688#define ICU_ISELR026_ADDR ( ( volatile uint8_t __evenaccess * )0x0008711A )
689#define ICU_ISELR027_ADDR ( ( volatile uint8_t __evenaccess * )0x0008711B )
690#define ICU_ISELR028_ADDR ( ( volatile uint8_t __evenaccess * )0x0008711C )
691#define ICU_ISELR029_ADDR ( ( volatile uint8_t __evenaccess * )0x0008711D )
692#define ICU_ISELR030_ADDR ( ( volatile uint8_t __evenaccess * )0x0008711E )
693#define ICU_ISELR031_ADDR ( ( volatile uint8_t __evenaccess * )0x0008711F )
694#define ICU_ISELR032_ADDR ( ( volatile uint8_t __evenaccess * )0x00087120 )
695#define ICU_ISELR033_ADDR ( ( volatile uint8_t __evenaccess * )0x00087121 )
696#define ICU_ISELR034_ADDR ( ( volatile uint8_t __evenaccess * )0x00087122 )
697#define ICU_ISELR035_ADDR ( ( volatile uint8_t __evenaccess * )0x00087123 )
698#define ICU_ISELR036_ADDR ( ( volatile uint8_t __evenaccess * )0x00087124 )
699#define ICU_ISELR037_ADDR ( ( volatile uint8_t __evenaccess * )0x00087125 )
700#define ICU_ISELR038_ADDR ( ( volatile uint8_t __evenaccess * )0x00087126 )
701#define ICU_ISELR039_ADDR ( ( volatile uint8_t __evenaccess * )0x00087127 )
702#define ICU_ISELR040_ADDR ( ( volatile uint8_t __evenaccess * )0x00087128 )
703#define ICU_ISELR041_ADDR ( ( volatile uint8_t __evenaccess * )0x00087129 )
704#define ICU_ISELR042_ADDR ( ( volatile uint8_t __evenaccess * )0x0008712A )
705#define ICU_ISELR043_ADDR ( ( volatile uint8_t __evenaccess * )0x0008712B )
706#define ICU_ISELR044_ADDR ( ( volatile uint8_t __evenaccess * )0x0008712C )
707#define ICU_ISELR045_ADDR ( ( volatile uint8_t __evenaccess * )0x0008712D )
708#define ICU_ISELR046_ADDR ( ( volatile uint8_t __evenaccess * )0x0008712E )
709#define ICU_ISELR047_ADDR ( ( volatile uint8_t __evenaccess * )0x0008712F )
710#define ICU_ISELR048_ADDR ( ( volatile uint8_t __evenaccess * )0x00087130 )
711#define ICU_ISELR049_ADDR ( ( volatile uint8_t __evenaccess * )0x00087131 )
712#define ICU_ISELR050_ADDR ( ( volatile uint8_t __evenaccess * )0x00087132 )
713#define ICU_ISELR051_ADDR ( ( volatile uint8_t __evenaccess * )0x00087133 )
714#define ICU_ISELR052_ADDR ( ( volatile uint8_t __evenaccess * )0x00087134 )
715#define ICU_ISELR053_ADDR ( ( volatile uint8_t __evenaccess * )0x00087135 )
716#define ICU_ISELR054_ADDR ( ( volatile uint8_t __evenaccess * )0x00087136 )
717#define ICU_ISELR055_ADDR ( ( volatile uint8_t __evenaccess * )0x00087137 )
718#define ICU_ISELR056_ADDR ( ( volatile uint8_t __evenaccess * )0x00087138 )
719#define ICU_ISELR057_ADDR ( ( volatile uint8_t __evenaccess * )0x00087139 )
720#define ICU_ISELR058_ADDR ( ( volatile uint8_t __evenaccess * )0x0008713A )
721#define ICU_ISELR059_ADDR ( ( volatile uint8_t __evenaccess * )0x0008713B )
722#define ICU_ISELR060_ADDR ( ( volatile uint8_t __evenaccess * )0x0008713C )
723#define ICU_ISELR061_ADDR ( ( volatile uint8_t __evenaccess * )0x0008713D )
724#define ICU_ISELR062_ADDR ( ( volatile uint8_t __evenaccess * )0x0008713E )
725#define ICU_ISELR063_ADDR ( ( volatile uint8_t __evenaccess * )0x0008713F )
726#define ICU_ISELR064_ADDR ( ( volatile uint8_t __evenaccess * )0x00087140 )
727#define ICU_ISELR065_ADDR ( ( volatile uint8_t __evenaccess * )0x00087141 )
728#define ICU_ISELR066_ADDR ( ( volatile uint8_t __evenaccess * )0x00087142 )
729#define ICU_ISELR067_ADDR ( ( volatile uint8_t __evenaccess * )0x00087143 )
730#define ICU_ISELR068_ADDR ( ( volatile uint8_t __evenaccess * )0x00087144 )
731#define ICU_ISELR069_ADDR ( ( volatile uint8_t __evenaccess * )0x00087145 )
732#define ICU_ISELR070_ADDR ( ( volatile uint8_t __evenaccess * )0x00087146 )
733#define ICU_ISELR071_ADDR ( ( volatile uint8_t __evenaccess * )0x00087147 )
734#define ICU_ISELR072_ADDR ( ( volatile uint8_t __evenaccess * )0x00087148 )
735#define ICU_ISELR073_ADDR ( ( volatile uint8_t __evenaccess * )0x00087149 )
736#define ICU_ISELR074_ADDR ( ( volatile uint8_t __evenaccess * )0x0008714A )
737#define ICU_ISELR075_ADDR ( ( volatile uint8_t __evenaccess * )0x0008714B )
738#define ICU_ISELR076_ADDR ( ( volatile uint8_t __evenaccess * )0x0008714C )
739#define ICU_ISELR077_ADDR ( ( volatile uint8_t __evenaccess * )0x0008714D )
740#define ICU_ISELR078_ADDR ( ( volatile uint8_t __evenaccess * )0x0008714E )
741#define ICU_ISELR079_ADDR ( ( volatile uint8_t __evenaccess * )0x0008714F )
742#define ICU_ISELR080_ADDR ( ( volatile uint8_t __evenaccess * )0x00087150 )
743#define ICU_ISELR081_ADDR ( ( volatile uint8_t __evenaccess * )0x00087151 )
744#define ICU_ISELR082_ADDR ( ( volatile uint8_t __evenaccess * )0x00087152 )
745#define ICU_ISELR083_ADDR ( ( volatile uint8_t __evenaccess * )0x00087153 )
746#define ICU_ISELR084_ADDR ( ( volatile uint8_t __evenaccess * )0x00087154 )
747#define ICU_ISELR085_ADDR ( ( volatile uint8_t __evenaccess * )0x00087155 )
748#define ICU_ISELR086_ADDR ( ( volatile uint8_t __evenaccess * )0x00087156 )
749#define ICU_ISELR087_ADDR ( ( volatile uint8_t __evenaccess * )0x00087157 )
750#define ICU_ISELR088_ADDR ( ( volatile uint8_t __evenaccess * )0x00087158 )
751#define ICU_ISELR089_ADDR ( ( volatile uint8_t __evenaccess * )0x00087159 )
752#define ICU_ISELR090_ADDR ( ( volatile uint8_t __evenaccess * )0x0008715A )
753#define ICU_ISELR091_ADDR ( ( volatile uint8_t __evenaccess * )0x0008715B )
754#define ICU_ISELR092_ADDR ( ( volatile uint8_t __evenaccess * )0x0008715C )
755#define ICU_ISELR093_ADDR ( ( volatile uint8_t __evenaccess * )0x0008715D )
756#define ICU_ISELR094_ADDR ( ( volatile uint8_t __evenaccess * )0x0008715E )
757#define ICU_ISELR095_ADDR ( ( volatile uint8_t __evenaccess * )0x0008715F )
758#define ICU_ISELR096_ADDR ( ( volatile uint8_t __evenaccess * )0x00087160 )
759#define ICU_ISELR097_ADDR ( ( volatile uint8_t __evenaccess * )0x00087161 )
760#define ICU_ISELR098_ADDR ( ( volatile uint8_t __evenaccess * )0x00087162 )
761#define ICU_ISELR099_ADDR ( ( volatile uint8_t __evenaccess * )0x00087163 )
762#define ICU_ISELR100_ADDR ( ( volatile uint8_t __evenaccess * )0x00087164 )
763#define ICU_ISELR101_ADDR ( ( volatile uint8_t __evenaccess * )0x00087165 )
764#define ICU_ISELR102_ADDR ( ( volatile uint8_t __evenaccess * )0x00087166 )
765#define ICU_ISELR103_ADDR ( ( volatile uint8_t __evenaccess * )0x00087167 )
766#define ICU_ISELR104_ADDR ( ( volatile uint8_t __evenaccess * )0x00087168 )
767#define ICU_ISELR105_ADDR ( ( volatile uint8_t __evenaccess * )0x00087169 )
768#define ICU_ISELR106_ADDR ( ( volatile uint8_t __evenaccess * )0x0008716A )
769#define ICU_ISELR107_ADDR ( ( volatile uint8_t __evenaccess * )0x0008716B )
770#define ICU_ISELR108_ADDR ( ( volatile uint8_t __evenaccess * )0x0008716C )
771#define ICU_ISELR109_ADDR ( ( volatile uint8_t __evenaccess * )0x0008716D )
772#define ICU_ISELR110_ADDR ( ( volatile uint8_t __evenaccess * )0x0008716E )
773#define ICU_ISELR111_ADDR ( ( volatile uint8_t __evenaccess * )0x0008716F )
774#define ICU_ISELR112_ADDR ( ( volatile uint8_t __evenaccess * )0x00087170 )
775#define ICU_ISELR113_ADDR ( ( volatile uint8_t __evenaccess * )0x00087171 )
776#define ICU_ISELR114_ADDR ( ( volatile uint8_t __evenaccess * )0x00087172 )
777#define ICU_ISELR115_ADDR ( ( volatile uint8_t __evenaccess * )0x00087173 )
778#define ICU_ISELR116_ADDR ( ( volatile uint8_t __evenaccess * )0x00087174 )
779#define ICU_ISELR117_ADDR ( ( volatile uint8_t __evenaccess * )0x00087175 )
780#define ICU_ISELR118_ADDR ( ( volatile uint8_t __evenaccess * )0x00087176 )
781#define ICU_ISELR119_ADDR ( ( volatile uint8_t __evenaccess * )0x00087177 )
782#define ICU_ISELR120_ADDR ( ( volatile uint8_t __evenaccess * )0x00087178 )
783#define ICU_ISELR121_ADDR ( ( volatile uint8_t __evenaccess * )0x00087179 )
784#define ICU_ISELR122_ADDR ( ( volatile uint8_t __evenaccess * )0x0008717A )
785#define ICU_ISELR123_ADDR ( ( volatile uint8_t __evenaccess * )0x0008717B )
786#define ICU_ISELR124_ADDR ( ( volatile uint8_t __evenaccess * )0x0008717C )
787#define ICU_ISELR125_ADDR ( ( volatile uint8_t __evenaccess * )0x0008717D )
788#define ICU_ISELR126_ADDR ( ( volatile uint8_t __evenaccess * )0x0008717E )
789#define ICU_ISELR127_ADDR ( ( volatile uint8_t __evenaccess * )0x0008717F )
790#define ICU_ISELR128_ADDR ( ( volatile uint8_t __evenaccess * )0x00087180 )
791#define ICU_ISELR129_ADDR ( ( volatile uint8_t __evenaccess * )0x00087181 )
792#define ICU_ISELR130_ADDR ( ( volatile uint8_t __evenaccess * )0x00087182 )
793#define ICU_ISELR131_ADDR ( ( volatile uint8_t __evenaccess * )0x00087183 )
794#define ICU_ISELR132_ADDR ( ( volatile uint8_t __evenaccess * )0x00087184 )
795#define ICU_ISELR133_ADDR ( ( volatile uint8_t __evenaccess * )0x00087185 )
796#define ICU_ISELR134_ADDR ( ( volatile uint8_t __evenaccess * )0x00087186 )
797#define ICU_ISELR135_ADDR ( ( volatile uint8_t __evenaccess * )0x00087187 )
798#define ICU_ISELR136_ADDR ( ( volatile uint8_t __evenaccess * )0x00087188 )
799#define ICU_ISELR137_ADDR ( ( volatile uint8_t __evenaccess * )0x00087189 )
800#define ICU_ISELR138_ADDR ( ( volatile uint8_t __evenaccess * )0x0008718A )
801#define ICU_ISELR139_ADDR ( ( volatile uint8_t __evenaccess * )0x0008718B )
802#define ICU_ISELR140_ADDR ( ( volatile uint8_t __evenaccess * )0x0008718C )
803#define ICU_ISELR141_ADDR ( ( volatile uint8_t __evenaccess * )0x0008718D )
804#define ICU_ISELR142_ADDR ( ( volatile uint8_t __evenaccess * )0x0008718E )
805#define ICU_ISELR143_ADDR ( ( volatile uint8_t __evenaccess * )0x0008718F )
806#define ICU_ISELR144_ADDR ( ( volatile uint8_t __evenaccess * )0x00087190 )
807#define ICU_ISELR145_ADDR ( ( volatile uint8_t __evenaccess * )0x00087191 )
808#define ICU_ISELR146_ADDR ( ( volatile uint8_t __evenaccess * )0x00087192 )
809#define ICU_ISELR147_ADDR ( ( volatile uint8_t __evenaccess * )0x00087193 )
810#define ICU_ISELR148_ADDR ( ( volatile uint8_t __evenaccess * )0x00087194 )
811#define ICU_ISELR149_ADDR ( ( volatile uint8_t __evenaccess * )0x00087195 )
812#define ICU_ISELR150_ADDR ( ( volatile uint8_t __evenaccess * )0x00087196 )
813#define ICU_ISELR151_ADDR ( ( volatile uint8_t __evenaccess * )0x00087197 )
814#define ICU_ISELR152_ADDR ( ( volatile uint8_t __evenaccess * )0x00087198 )
815#define ICU_ISELR153_ADDR ( ( volatile uint8_t __evenaccess * )0x00087199 )
816#define ICU_ISELR154_ADDR ( ( volatile uint8_t __evenaccess * )0x0008719A )
817#define ICU_ISELR155_ADDR ( ( volatile uint8_t __evenaccess * )0x0008719B )
818#define ICU_ISELR156_ADDR ( ( volatile uint8_t __evenaccess * )0x0008719C )
819#define ICU_ISELR157_ADDR ( ( volatile uint8_t __evenaccess * )0x0008719D )
820#define ICU_ISELR158_ADDR ( ( volatile uint8_t __evenaccess * )0x0008719E )
821#define ICU_ISELR159_ADDR ( ( volatile uint8_t __evenaccess * )0x0008719F )
822#define ICU_ISELR160_ADDR ( ( volatile uint8_t __evenaccess * )0x000871A0 )
823#define ICU_ISELR161_ADDR ( ( volatile uint8_t __evenaccess * )0x000871A1 )
824#define ICU_ISELR162_ADDR ( ( volatile uint8_t __evenaccess * )0x000871A2 )
825#define ICU_ISELR163_ADDR ( ( volatile uint8_t __evenaccess * )0x000871A3 )
826#define ICU_ISELR164_ADDR ( ( volatile uint8_t __evenaccess * )0x000871A4 )
827#define ICU_ISELR165_ADDR ( ( volatile uint8_t __evenaccess * )0x000871A5 )
828#define ICU_ISELR166_ADDR ( ( volatile uint8_t __evenaccess * )0x000871A6 )
829#define ICU_ISELR167_ADDR ( ( volatile uint8_t __evenaccess * )0x000871A7 )
830#define ICU_ISELR168_ADDR ( ( volatile uint8_t __evenaccess * )0x000871A8 )
831#define ICU_ISELR169_ADDR ( ( volatile uint8_t __evenaccess * )0x000871A9 )
832#define ICU_ISELR170_ADDR ( ( volatile uint8_t __evenaccess * )0x000871AA )
833#define ICU_ISELR171_ADDR ( ( volatile uint8_t __evenaccess * )0x000871AB )
834#define ICU_ISELR172_ADDR ( ( volatile uint8_t __evenaccess * )0x000871AC )
835#define ICU_ISELR173_ADDR ( ( volatile uint8_t __evenaccess * )0x000871AD )
836#define ICU_ISELR174_ADDR ( ( volatile uint8_t __evenaccess * )0x000871AE )
837#define ICU_ISELR175_ADDR ( ( volatile uint8_t __evenaccess * )0x000871AF )
838#define ICU_ISELR176_ADDR ( ( volatile uint8_t __evenaccess * )0x000871B0 )
839#define ICU_ISELR177_ADDR ( ( volatile uint8_t __evenaccess * )0x000871B1 )
840#define ICU_ISELR178_ADDR ( ( volatile uint8_t __evenaccess * )0x000871B2 )
841#define ICU_ISELR179_ADDR ( ( volatile uint8_t __evenaccess * )0x000871B3 )
842#define ICU_ISELR180_ADDR ( ( volatile uint8_t __evenaccess * )0x000871B4 )
843#define ICU_ISELR181_ADDR ( ( volatile uint8_t __evenaccess * )0x000871B5 )
844#define ICU_ISELR182_ADDR ( ( volatile uint8_t __evenaccess * )0x000871B6 )
845#define ICU_ISELR183_ADDR ( ( volatile uint8_t __evenaccess * )0x000871B7 )
846#define ICU_ISELR184_ADDR ( ( volatile uint8_t __evenaccess * )0x000871B8 )
847#define ICU_ISELR185_ADDR ( ( volatile uint8_t __evenaccess * )0x000871B9 )
848#define ICU_ISELR186_ADDR ( ( volatile uint8_t __evenaccess * )0x000871BA )
849#define ICU_ISELR187_ADDR ( ( volatile uint8_t __evenaccess * )0x000871BB )
850#define ICU_ISELR188_ADDR ( ( volatile uint8_t __evenaccess * )0x000871BC )
851#define ICU_ISELR189_ADDR ( ( volatile uint8_t __evenaccess * )0x000871BD )
852#define ICU_ISELR190_ADDR ( ( volatile uint8_t __evenaccess * )0x000871BE )
853#define ICU_ISELR191_ADDR ( ( volatile uint8_t __evenaccess * )0x000871BF )
854#define ICU_ISELR192_ADDR ( ( volatile uint8_t __evenaccess * )0x000871C0 )
855#define ICU_ISELR193_ADDR ( ( volatile uint8_t __evenaccess * )0x000871C1 )
856#define ICU_ISELR194_ADDR ( ( volatile uint8_t __evenaccess * )0x000871C2 )
857#define ICU_ISELR195_ADDR ( ( volatile uint8_t __evenaccess * )0x000871C3 )
858#define ICU_ISELR196_ADDR ( ( volatile uint8_t __evenaccess * )0x000871C4 )
859#define ICU_ISELR197_ADDR ( ( volatile uint8_t __evenaccess * )0x000871C5 )
860#define ICU_ISELR198_ADDR ( ( volatile uint8_t __evenaccess * )0x000871C6 )
861#define ICU_ISELR199_ADDR ( ( volatile uint8_t __evenaccess * )0x000871C7 )
862#define ICU_ISELR200_ADDR ( ( volatile uint8_t __evenaccess * )0x000871C8 )
863#define ICU_ISELR201_ADDR ( ( volatile uint8_t __evenaccess * )0x000871C9 )
864#define ICU_ISELR202_ADDR ( ( volatile uint8_t __evenaccess * )0x000871CA )
865#define ICU_ISELR203_ADDR ( ( volatile uint8_t __evenaccess * )0x000871CB )
866#define ICU_ISELR204_ADDR ( ( volatile uint8_t __evenaccess * )0x000871CC )
867#define ICU_ISELR205_ADDR ( ( volatile uint8_t __evenaccess * )0x000871CD )
868#define ICU_ISELR206_ADDR ( ( volatile uint8_t __evenaccess * )0x000871CE )
869#define ICU_ISELR207_ADDR ( ( volatile uint8_t __evenaccess * )0x000871CF )
870#define ICU_ISELR208_ADDR ( ( volatile uint8_t __evenaccess * )0x000871D0 )
871#define ICU_ISELR209_ADDR ( ( volatile uint8_t __evenaccess * )0x000871D1 )
872#define ICU_ISELR210_ADDR ( ( volatile uint8_t __evenaccess * )0x000871D2 )
873#define ICU_ISELR211_ADDR ( ( volatile uint8_t __evenaccess * )0x000871D3 )
874#define ICU_ISELR212_ADDR ( ( volatile uint8_t __evenaccess * )0x000871D4 )
875#define ICU_ISELR213_ADDR ( ( volatile uint8_t __evenaccess * )0x000871D5 )
876#define ICU_ISELR214_ADDR ( ( volatile uint8_t __evenaccess * )0x000871D6 )
877#define ICU_ISELR215_ADDR ( ( volatile uint8_t __evenaccess * )0x000871D7 )
878#define ICU_ISELR216_ADDR ( ( volatile uint8_t __evenaccess * )0x000871D8 )
879#define ICU_ISELR217_ADDR ( ( volatile uint8_t __evenaccess * )0x000871D9 )
880#define ICU_ISELR218_ADDR ( ( volatile uint8_t __evenaccess * )0x000871DA )
881#define ICU_ISELR219_ADDR ( ( volatile uint8_t __evenaccess * )0x000871DB )
882#define ICU_ISELR220_ADDR ( ( volatile uint8_t __evenaccess * )0x000871DC )
883#define ICU_ISELR221_ADDR ( ( volatile uint8_t __evenaccess * )0x000871DD )
884#define ICU_ISELR222_ADDR ( ( volatile uint8_t __evenaccess * )0x000871DE )
885#define ICU_ISELR223_ADDR ( ( volatile uint8_t __evenaccess * )0x000871DF )
886#define ICU_ISELR224_ADDR ( ( volatile uint8_t __evenaccess * )0x000871E0 )
887#define ICU_ISELR225_ADDR ( ( volatile uint8_t __evenaccess * )0x000871E1 )
888#define ICU_ISELR226_ADDR ( ( volatile uint8_t __evenaccess * )0x000871E2 )
889#define ICU_ISELR227_ADDR ( ( volatile uint8_t __evenaccess * )0x000871E3 )
890#define ICU_ISELR228_ADDR ( ( volatile uint8_t __evenaccess * )0x000871E4 )
891#define ICU_ISELR229_ADDR ( ( volatile uint8_t __evenaccess * )0x000871E5 )
892#define ICU_ISELR230_ADDR ( ( volatile uint8_t __evenaccess * )0x000871E6 )
893#define ICU_ISELR231_ADDR ( ( volatile uint8_t __evenaccess * )0x000871E7 )
894#define ICU_ISELR232_ADDR ( ( volatile uint8_t __evenaccess * )0x000871E8 )
895#define ICU_ISELR233_ADDR ( ( volatile uint8_t __evenaccess * )0x000871E9 )
896#define ICU_ISELR234_ADDR ( ( volatile uint8_t __evenaccess * )0x000871EA )
897#define ICU_ISELR235_ADDR ( ( volatile uint8_t __evenaccess * )0x000871EB )
898#define ICU_ISELR236_ADDR ( ( volatile uint8_t __evenaccess * )0x000871EC )
899#define ICU_ISELR237_ADDR ( ( volatile uint8_t __evenaccess * )0x000871ED )
900#define ICU_ISELR238_ADDR ( ( volatile uint8_t __evenaccess * )0x000871EE )
901#define ICU_ISELR239_ADDR ( ( volatile uint8_t __evenaccess * )0x000871EF )
902#define ICU_ISELR240_ADDR ( ( volatile uint8_t __evenaccess * )0x000871F0 )
903#define ICU_ISELR241_ADDR ( ( volatile uint8_t __evenaccess * )0x000871F1 )
904#define ICU_ISELR242_ADDR ( ( volatile uint8_t __evenaccess * )0x000871F2 )
905#define ICU_ISELR243_ADDR ( ( volatile uint8_t __evenaccess * )0x000871F3 )
906#define ICU_ISELR244_ADDR ( ( volatile uint8_t __evenaccess * )0x000871F4 )
907#define ICU_ISELR245_ADDR ( ( volatile uint8_t __evenaccess * )0x000871F5 )
908#define ICU_ISELR246_ADDR ( ( volatile uint8_t __evenaccess * )0x000871F6 )
909#define ICU_ISELR247_ADDR ( ( volatile uint8_t __evenaccess * )0x000871F7 )
910#define ICU_ISELR248_ADDR ( ( volatile uint8_t __evenaccess * )0x000871F8 )
911#define ICU_ISELR249_ADDR ( ( volatile uint8_t __evenaccess * )0x000871F9 )
912#define ICU_ISELR250_ADDR ( ( volatile uint8_t __evenaccess * )0x000871FA )
913#define ICU_ISELR251_ADDR ( ( volatile uint8_t __evenaccess * )0x000871FB )
914#define ICU_ISELR252_ADDR ( ( volatile uint8_t __evenaccess * )0x000871FC )
915#define ICU_ISELR253_ADDR ( ( volatile uint8_t __evenaccess * )0x000871FD )
916#define ICU_ISELR254_ADDR ( ( volatile uint8_t __evenaccess * )0x000871FE )
917#define ICU_ISELR255_ADDR ( ( volatile uint8_t __evenaccess * )0x000871FF )
918#define ICU_ISEL_BIT ( 3U << 0U )
919
920/*
921 * Š„‚荞‚Ý—v‹‹–‰ÂƒŒƒWƒXƒ^
922 */
923#define ICU_IER02_ADDR ( ( volatile uint8_t __evenaccess * )0x00087202 )
924#define ICU_IER03_ADDR ( ( volatile uint8_t __evenaccess * )0x00087203 )
925#define ICU_IER04_ADDR ( ( volatile uint8_t __evenaccess * )0x00087204 )
926#define ICU_IER05_ADDR ( ( volatile uint8_t __evenaccess * )0x00087205 )
927#define ICU_IER06_ADDR ( ( volatile uint8_t __evenaccess * )0x00087206 )
928#define ICU_IER07_ADDR ( ( volatile uint8_t __evenaccess * )0x00087207 )
929#define ICU_IER08_ADDR ( ( volatile uint8_t __evenaccess * )0x00087208 )
930#define ICU_IER09_ADDR ( ( volatile uint8_t __evenaccess * )0x00087209 )
931#define ICU_IER0B_ADDR ( ( volatile uint8_t __evenaccess * )0x0008720B )
932#define ICU_IER0C_ADDR ( ( volatile uint8_t __evenaccess * )0x0008720C )
933#define ICU_IER0D_ADDR ( ( volatile uint8_t __evenaccess * )0x0008720D )
934#define ICU_IER0E_ADDR ( ( volatile uint8_t __evenaccess * )0x0008720E )
935#define ICU_IER0F_ADDR ( ( volatile uint8_t __evenaccess * )0x0008720F )
936#define ICU_IER10_ADDR ( ( volatile uint8_t __evenaccess * )0x00087210 )
937#define ICU_IER11_ADDR ( ( volatile uint8_t __evenaccess * )0x00087211 )
938#define ICU_IER12_ADDR ( ( volatile uint8_t __evenaccess * )0x00087212 )
939#define ICU_IER13_ADDR ( ( volatile uint8_t __evenaccess * )0x00087213 )
940#define ICU_IER14_ADDR ( ( volatile uint8_t __evenaccess * )0x00087214 )
941#define ICU_IER15_ADDR ( ( volatile uint8_t __evenaccess * )0x00087215 )
942#define ICU_IER16_ADDR ( ( volatile uint8_t __evenaccess * )0x00087216 )
943#define ICU_IER17_ADDR ( ( volatile uint8_t __evenaccess * )0x00087217 )
944#define ICU_IER18_ADDR ( ( volatile uint8_t __evenaccess * )0x00087218 )
945#define ICU_IER19_ADDR ( ( volatile uint8_t __evenaccess * )0x00087219 )
946#define ICU_IER1A_ADDR ( ( volatile uint8_t __evenaccess * )0x0008721A )
947#define ICU_IER1B_ADDR ( ( volatile uint8_t __evenaccess * )0x0008721B )
948#define ICU_IER1C_ADDR ( ( volatile uint8_t __evenaccess * )0x0008721C )
949#define ICU_IER1D_ADDR ( ( volatile uint8_t __evenaccess * )0x0008721D )
950#define ICU_IER1E_ADDR ( ( volatile uint8_t __evenaccess * )0x0008721E )
951#define ICU_IER1F_ADDR ( ( volatile uint8_t __evenaccess * )0x0008721F )
952#define ICU_IEN0_BIT ( 1U << 0U )
953#define ICU_IEN1_BIT ( 1U << 1U )
954#define ICU_IEN2_BIT ( 1U << 2U )
955#define ICU_IEN3_BIT ( 1U << 3U )
956#define ICU_IEN4_BIT ( 1U << 4U )
957#define ICU_IEN5_BIT ( 1U << 5U )
958#define ICU_IEN6_BIT ( 1U << 6U )
959#define ICU_IEN7_BIT ( 1U << 7U )
960
961/*
962 * Š„‚荞‚Ý—vˆöƒvƒ‰ƒCƒIƒŠƒeƒBƒŒƒWƒXƒ^i(i=0`253)‚̐ݒè
963 */
964#define ICU_IPR000_ADDR ( ( volatile uint8_t __evenaccess * )0x00087300 )
965#define ICU_IPR001_ADDR ( ( volatile uint8_t __evenaccess * )0x00087301 )
966#define ICU_IPR002_ADDR ( ( volatile uint8_t __evenaccess * )0x00087302 )
967#define ICU_IPR003_ADDR ( ( volatile uint8_t __evenaccess * )0x00087303 )
968#define ICU_IPR004_ADDR ( ( volatile uint8_t __evenaccess * )0x00087304 )
969#define ICU_IPR005_ADDR ( ( volatile uint8_t __evenaccess * )0x00087305 )
970#define ICU_IPR006_ADDR ( ( volatile uint8_t __evenaccess * )0x00087306 )
971#define ICU_IPR007_ADDR ( ( volatile uint8_t __evenaccess * )0x00087307 )
972#define ICU_IPR008_ADDR ( ( volatile uint8_t __evenaccess * )0x00087308 )
973#define ICU_IPR009_ADDR ( ( volatile uint8_t __evenaccess * )0x00087309 )
974#define ICU_IPR010_ADDR ( ( volatile uint8_t __evenaccess * )0x0008730A )
975#define ICU_IPR011_ADDR ( ( volatile uint8_t __evenaccess * )0x0008730B )
976#define ICU_IPR012_ADDR ( ( volatile uint8_t __evenaccess * )0x0008730C )
977#define ICU_IPR013_ADDR ( ( volatile uint8_t __evenaccess * )0x0008730D )
978#define ICU_IPR014_ADDR ( ( volatile uint8_t __evenaccess * )0x0008730E )
979#define ICU_IPR015_ADDR ( ( volatile uint8_t __evenaccess * )0x0008730F )
980#define ICU_IPR016_ADDR ( ( volatile uint8_t __evenaccess * )0x00087310 )
981#define ICU_IPR017_ADDR ( ( volatile uint8_t __evenaccess * )0x00087311 )
982#define ICU_IPR018_ADDR ( ( volatile uint8_t __evenaccess * )0x00087312 )
983#define ICU_IPR019_ADDR ( ( volatile uint8_t __evenaccess * )0x00087313 )
984#define ICU_IPR020_ADDR ( ( volatile uint8_t __evenaccess * )0x00087314 )
985#define ICU_IPR021_ADDR ( ( volatile uint8_t __evenaccess * )0x00087315 )
986#define ICU_IPR022_ADDR ( ( volatile uint8_t __evenaccess * )0x00087316 )
987#define ICU_IPR023_ADDR ( ( volatile uint8_t __evenaccess * )0x00087317 )
988#define ICU_IPR024_ADDR ( ( volatile uint8_t __evenaccess * )0x00087318 )
989#define ICU_IPR025_ADDR ( ( volatile uint8_t __evenaccess * )0x00087319 )
990#define ICU_IPR026_ADDR ( ( volatile uint8_t __evenaccess * )0x0008731A )
991#define ICU_IPR027_ADDR ( ( volatile uint8_t __evenaccess * )0x0008731B )
992#define ICU_IPR028_ADDR ( ( volatile uint8_t __evenaccess * )0x0008731C )
993#define ICU_IPR029_ADDR ( ( volatile uint8_t __evenaccess * )0x0008731D )
994#define ICU_IPR030_ADDR ( ( volatile uint8_t __evenaccess * )0x0008731E )
995#define ICU_IPR031_ADDR ( ( volatile uint8_t __evenaccess * )0x0008731F )
996#define ICU_IPR032_ADDR ( ( volatile uint8_t __evenaccess * )0x00087320 )
997#define ICU_IPR033_ADDR ( ( volatile uint8_t __evenaccess * )0x00087321 )
998#define ICU_IPR034_ADDR ( ( volatile uint8_t __evenaccess * )0x00087322 )
999#define ICU_IPR035_ADDR ( ( volatile uint8_t __evenaccess * )0x00087323 )
1000#define ICU_IPR036_ADDR ( ( volatile uint8_t __evenaccess * )0x00087324 )
1001#define ICU_IPR037_ADDR ( ( volatile uint8_t __evenaccess * )0x00087325 )
1002#define ICU_IPR038_ADDR ( ( volatile uint8_t __evenaccess * )0x00087326 )
1003#define ICU_IPR039_ADDR ( ( volatile uint8_t __evenaccess * )0x00087327 )
1004#define ICU_IPR040_ADDR ( ( volatile uint8_t __evenaccess * )0x00087328 )
1005#define ICU_IPR041_ADDR ( ( volatile uint8_t __evenaccess * )0x00087329 )
1006#define ICU_IPR042_ADDR ( ( volatile uint8_t __evenaccess * )0x0008732A )
1007#define ICU_IPR043_ADDR ( ( volatile uint8_t __evenaccess * )0x0008732B )
1008#define ICU_IPR044_ADDR ( ( volatile uint8_t __evenaccess * )0x0008732C )
1009#define ICU_IPR045_ADDR ( ( volatile uint8_t __evenaccess * )0x0008732D )
1010#define ICU_IPR046_ADDR ( ( volatile uint8_t __evenaccess * )0x0008732E )
1011#define ICU_IPR047_ADDR ( ( volatile uint8_t __evenaccess * )0x0008732F )
1012#define ICU_IPR048_ADDR ( ( volatile uint8_t __evenaccess * )0x00087330 )
1013#define ICU_IPR049_ADDR ( ( volatile uint8_t __evenaccess * )0x00087331 )
1014#define ICU_IPR050_ADDR ( ( volatile uint8_t __evenaccess * )0x00087332 )
1015#define ICU_IPR051_ADDR ( ( volatile uint8_t __evenaccess * )0x00087333 )
1016#define ICU_IPR052_ADDR ( ( volatile uint8_t __evenaccess * )0x00087334 )
1017#define ICU_IPR053_ADDR ( ( volatile uint8_t __evenaccess * )0x00087335 )
1018#define ICU_IPR054_ADDR ( ( volatile uint8_t __evenaccess * )0x00087336 )
1019#define ICU_IPR055_ADDR ( ( volatile uint8_t __evenaccess * )0x00087337 )
1020#define ICU_IPR056_ADDR ( ( volatile uint8_t __evenaccess * )0x00087338 )
1021#define ICU_IPR057_ADDR ( ( volatile uint8_t __evenaccess * )0x00087339 )
1022#define ICU_IPR058_ADDR ( ( volatile uint8_t __evenaccess * )0x0008733A )
1023#define ICU_IPR059_ADDR ( ( volatile uint8_t __evenaccess * )0x0008733B )
1024#define ICU_IPR060_ADDR ( ( volatile uint8_t __evenaccess * )0x0008733C )
1025#define ICU_IPR061_ADDR ( ( volatile uint8_t __evenaccess * )0x0008733D )
1026#define ICU_IPR062_ADDR ( ( volatile uint8_t __evenaccess * )0x0008733E )
1027#define ICU_IPR063_ADDR ( ( volatile uint8_t __evenaccess * )0x0008733F )
1028#define ICU_IPR064_ADDR ( ( volatile uint8_t __evenaccess * )0x00087340 )
1029#define ICU_IPR065_ADDR ( ( volatile uint8_t __evenaccess * )0x00087341 )
1030#define ICU_IPR066_ADDR ( ( volatile uint8_t __evenaccess * )0x00087342 )
1031#define ICU_IPR067_ADDR ( ( volatile uint8_t __evenaccess * )0x00087343 )
1032#define ICU_IPR068_ADDR ( ( volatile uint8_t __evenaccess * )0x00087344 )
1033#define ICU_IPR069_ADDR ( ( volatile uint8_t __evenaccess * )0x00087345 )
1034#define ICU_IPR070_ADDR ( ( volatile uint8_t __evenaccess * )0x00087346 )
1035#define ICU_IPR071_ADDR ( ( volatile uint8_t __evenaccess * )0x00087347 )
1036#define ICU_IPR072_ADDR ( ( volatile uint8_t __evenaccess * )0x00087348 )
1037#define ICU_IPR073_ADDR ( ( volatile uint8_t __evenaccess * )0x00087349 )
1038#define ICU_IPR074_ADDR ( ( volatile uint8_t __evenaccess * )0x0008734A )
1039#define ICU_IPR075_ADDR ( ( volatile uint8_t __evenaccess * )0x0008734B )
1040#define ICU_IPR076_ADDR ( ( volatile uint8_t __evenaccess * )0x0008734C )
1041#define ICU_IPR077_ADDR ( ( volatile uint8_t __evenaccess * )0x0008734D )
1042#define ICU_IPR078_ADDR ( ( volatile uint8_t __evenaccess * )0x0008734E )
1043#define ICU_IPR079_ADDR ( ( volatile uint8_t __evenaccess * )0x0008734F )
1044#define ICU_IPR080_ADDR ( ( volatile uint8_t __evenaccess * )0x00087350 )
1045#define ICU_IPR081_ADDR ( ( volatile uint8_t __evenaccess * )0x00087351 )
1046#define ICU_IPR082_ADDR ( ( volatile uint8_t __evenaccess * )0x00087352 )
1047#define ICU_IPR083_ADDR ( ( volatile uint8_t __evenaccess * )0x00087353 )
1048#define ICU_IPR084_ADDR ( ( volatile uint8_t __evenaccess * )0x00087354 )
1049#define ICU_IPR085_ADDR ( ( volatile uint8_t __evenaccess * )0x00087355 )
1050#define ICU_IPR086_ADDR ( ( volatile uint8_t __evenaccess * )0x00087356 )
1051#define ICU_IPR087_ADDR ( ( volatile uint8_t __evenaccess * )0x00087357 )
1052#define ICU_IPR088_ADDR ( ( volatile uint8_t __evenaccess * )0x00087358 )
1053#define ICU_IPR089_ADDR ( ( volatile uint8_t __evenaccess * )0x00087359 )
1054#define ICU_IPR090_ADDR ( ( volatile uint8_t __evenaccess * )0x0008735A )
1055#define ICU_IPR091_ADDR ( ( volatile uint8_t __evenaccess * )0x0008735B )
1056#define ICU_IPR092_ADDR ( ( volatile uint8_t __evenaccess * )0x0008735C )
1057#define ICU_IPR093_ADDR ( ( volatile uint8_t __evenaccess * )0x0008735D )
1058#define ICU_IPR094_ADDR ( ( volatile uint8_t __evenaccess * )0x0008735E )
1059#define ICU_IPR095_ADDR ( ( volatile uint8_t __evenaccess * )0x0008735F )
1060#define ICU_IPR096_ADDR ( ( volatile uint8_t __evenaccess * )0x00087360 )
1061#define ICU_IPR097_ADDR ( ( volatile uint8_t __evenaccess * )0x00087361 )
1062#define ICU_IPR098_ADDR ( ( volatile uint8_t __evenaccess * )0x00087362 )
1063#define ICU_IPR099_ADDR ( ( volatile uint8_t __evenaccess * )0x00087363 )
1064#define ICU_IPR100_ADDR ( ( volatile uint8_t __evenaccess * )0x00087364 )
1065#define ICU_IPR101_ADDR ( ( volatile uint8_t __evenaccess * )0x00087365 )
1066#define ICU_IPR102_ADDR ( ( volatile uint8_t __evenaccess * )0x00087366 )
1067#define ICU_IPR103_ADDR ( ( volatile uint8_t __evenaccess * )0x00087367 )
1068#define ICU_IPR104_ADDR ( ( volatile uint8_t __evenaccess * )0x00087368 )
1069#define ICU_IPR105_ADDR ( ( volatile uint8_t __evenaccess * )0x00087369 )
1070#define ICU_IPR106_ADDR ( ( volatile uint8_t __evenaccess * )0x0008736A )
1071#define ICU_IPR107_ADDR ( ( volatile uint8_t __evenaccess * )0x0008736B )
1072#define ICU_IPR108_ADDR ( ( volatile uint8_t __evenaccess * )0x0008736C )
1073#define ICU_IPR109_ADDR ( ( volatile uint8_t __evenaccess * )0x0008736D )
1074#define ICU_IPR110_ADDR ( ( volatile uint8_t __evenaccess * )0x0008736E )
1075#define ICU_IPR111_ADDR ( ( volatile uint8_t __evenaccess * )0x0008736F )
1076#define ICU_IPR112_ADDR ( ( volatile uint8_t __evenaccess * )0x00087370 )
1077#define ICU_IPR113_ADDR ( ( volatile uint8_t __evenaccess * )0x00087371 )
1078#define ICU_IPR114_ADDR ( ( volatile uint8_t __evenaccess * )0x00087372 )
1079#define ICU_IPR115_ADDR ( ( volatile uint8_t __evenaccess * )0x00087373 )
1080#define ICU_IPR116_ADDR ( ( volatile uint8_t __evenaccess * )0x00087374 )
1081#define ICU_IPR117_ADDR ( ( volatile uint8_t __evenaccess * )0x00087375 )
1082#define ICU_IPR118_ADDR ( ( volatile uint8_t __evenaccess * )0x00087376 )
1083#define ICU_IPR119_ADDR ( ( volatile uint8_t __evenaccess * )0x00087377 )
1084#define ICU_IPR120_ADDR ( ( volatile uint8_t __evenaccess * )0x00087378 )
1085#define ICU_IPR121_ADDR ( ( volatile uint8_t __evenaccess * )0x00087379 )
1086#define ICU_IPR122_ADDR ( ( volatile uint8_t __evenaccess * )0x0008737A )
1087#define ICU_IPR123_ADDR ( ( volatile uint8_t __evenaccess * )0x0008737B )
1088#define ICU_IPR124_ADDR ( ( volatile uint8_t __evenaccess * )0x0008737C )
1089#define ICU_IPR125_ADDR ( ( volatile uint8_t __evenaccess * )0x0008737D )
1090#define ICU_IPR126_ADDR ( ( volatile uint8_t __evenaccess * )0x0008737E )
1091#define ICU_IPR127_ADDR ( ( volatile uint8_t __evenaccess * )0x0008737F )
1092#define ICU_IPR128_ADDR ( ( volatile uint8_t __evenaccess * )0x00087380 )
1093#define ICU_IPR129_ADDR ( ( volatile uint8_t __evenaccess * )0x00087381 )
1094#define ICU_IPR130_ADDR ( ( volatile uint8_t __evenaccess * )0x00087382 )
1095#define ICU_IPR131_ADDR ( ( volatile uint8_t __evenaccess * )0x00087383 )
1096#define ICU_IPR132_ADDR ( ( volatile uint8_t __evenaccess * )0x00087384 )
1097#define ICU_IPR133_ADDR ( ( volatile uint8_t __evenaccess * )0x00087385 )
1098#define ICU_IPR134_ADDR ( ( volatile uint8_t __evenaccess * )0x00087386 )
1099#define ICU_IPR135_ADDR ( ( volatile uint8_t __evenaccess * )0x00087387 )
1100#define ICU_IPR136_ADDR ( ( volatile uint8_t __evenaccess * )0x00087388 )
1101#define ICU_IPR137_ADDR ( ( volatile uint8_t __evenaccess * )0x00087389 )
1102#define ICU_IPR138_ADDR ( ( volatile uint8_t __evenaccess * )0x0008738A )
1103#define ICU_IPR139_ADDR ( ( volatile uint8_t __evenaccess * )0x0008738B )
1104#define ICU_IPR140_ADDR ( ( volatile uint8_t __evenaccess * )0x0008738C )
1105#define ICU_IPR141_ADDR ( ( volatile uint8_t __evenaccess * )0x0008738D )
1106#define ICU_IPR142_ADDR ( ( volatile uint8_t __evenaccess * )0x0008738E )
1107#define ICU_IPR143_ADDR ( ( volatile uint8_t __evenaccess * )0x0008738F )
1108#define ICU_IPR144_ADDR ( ( volatile uint8_t __evenaccess * )0x00087390 )
1109#define ICU_IPR145_ADDR ( ( volatile uint8_t __evenaccess * )0x00087391 )
1110#define ICU_IPR146_ADDR ( ( volatile uint8_t __evenaccess * )0x00087392 )
1111#define ICU_IPR147_ADDR ( ( volatile uint8_t __evenaccess * )0x00087393 )
1112#define ICU_IPR148_ADDR ( ( volatile uint8_t __evenaccess * )0x00087394 )
1113#define ICU_IPR149_ADDR ( ( volatile uint8_t __evenaccess * )0x00087395 )
1114#define ICU_IPR150_ADDR ( ( volatile uint8_t __evenaccess * )0x00087396 )
1115#define ICU_IPR151_ADDR ( ( volatile uint8_t __evenaccess * )0x00087397 )
1116#define ICU_IPR152_ADDR ( ( volatile uint8_t __evenaccess * )0x00087398 )
1117#define ICU_IPR153_ADDR ( ( volatile uint8_t __evenaccess * )0x00087399 )
1118#define ICU_IPR154_ADDR ( ( volatile uint8_t __evenaccess * )0x0008739A )
1119#define ICU_IPR155_ADDR ( ( volatile uint8_t __evenaccess * )0x0008739B )
1120#define ICU_IPR156_ADDR ( ( volatile uint8_t __evenaccess * )0x0008739C )
1121#define ICU_IPR157_ADDR ( ( volatile uint8_t __evenaccess * )0x0008739D )
1122#define ICU_IPR158_ADDR ( ( volatile uint8_t __evenaccess * )0x0008739E )
1123#define ICU_IPR159_ADDR ( ( volatile uint8_t __evenaccess * )0x0008739F )
1124#define ICU_IPR160_ADDR ( ( volatile uint8_t __evenaccess * )0x000873A0 )
1125#define ICU_IPR161_ADDR ( ( volatile uint8_t __evenaccess * )0x000873A1 )
1126#define ICU_IPR162_ADDR ( ( volatile uint8_t __evenaccess * )0x000873A2 )
1127#define ICU_IPR163_ADDR ( ( volatile uint8_t __evenaccess * )0x000873A3 )
1128#define ICU_IPR164_ADDR ( ( volatile uint8_t __evenaccess * )0x000873A4 )
1129#define ICU_IPR165_ADDR ( ( volatile uint8_t __evenaccess * )0x000873A5 )
1130#define ICU_IPR166_ADDR ( ( volatile uint8_t __evenaccess * )0x000873A6 )
1131#define ICU_IPR167_ADDR ( ( volatile uint8_t __evenaccess * )0x000873A7 )
1132#define ICU_IPR168_ADDR ( ( volatile uint8_t __evenaccess * )0x000873A8 )
1133#define ICU_IPR169_ADDR ( ( volatile uint8_t __evenaccess * )0x000873A9 )
1134#define ICU_IPR170_ADDR ( ( volatile uint8_t __evenaccess * )0x000873AA )
1135#define ICU_IPR171_ADDR ( ( volatile uint8_t __evenaccess * )0x000873AB )
1136#define ICU_IPR172_ADDR ( ( volatile uint8_t __evenaccess * )0x000873AC )
1137#define ICU_IPR173_ADDR ( ( volatile uint8_t __evenaccess * )0x000873AD )
1138#define ICU_IPR174_ADDR ( ( volatile uint8_t __evenaccess * )0x000873AE )
1139#define ICU_IPR175_ADDR ( ( volatile uint8_t __evenaccess * )0x000873AF )
1140#define ICU_IPR176_ADDR ( ( volatile uint8_t __evenaccess * )0x000873B0 )
1141#define ICU_IPR177_ADDR ( ( volatile uint8_t __evenaccess * )0x000873B1 )
1142#define ICU_IPR178_ADDR ( ( volatile uint8_t __evenaccess * )0x000873B2 )
1143#define ICU_IPR179_ADDR ( ( volatile uint8_t __evenaccess * )0x000873B3 )
1144#define ICU_IPR180_ADDR ( ( volatile uint8_t __evenaccess * )0x000873B4 )
1145#define ICU_IPR181_ADDR ( ( volatile uint8_t __evenaccess * )0x000873B5 )
1146#define ICU_IPR182_ADDR ( ( volatile uint8_t __evenaccess * )0x000873B6 )
1147#define ICU_IPR183_ADDR ( ( volatile uint8_t __evenaccess * )0x000873B7 )
1148#define ICU_IPR184_ADDR ( ( volatile uint8_t __evenaccess * )0x000873B8 )
1149#define ICU_IPR185_ADDR ( ( volatile uint8_t __evenaccess * )0x000873B9 )
1150#define ICU_IPR186_ADDR ( ( volatile uint8_t __evenaccess * )0x000873BA )
1151#define ICU_IPR187_ADDR ( ( volatile uint8_t __evenaccess * )0x000873BB )
1152#define ICU_IPR188_ADDR ( ( volatile uint8_t __evenaccess * )0x000873BC )
1153#define ICU_IPR189_ADDR ( ( volatile uint8_t __evenaccess * )0x000873BD )
1154#define ICU_IPR190_ADDR ( ( volatile uint8_t __evenaccess * )0x000873BE )
1155#define ICU_IPR191_ADDR ( ( volatile uint8_t __evenaccess * )0x000873BF )
1156#define ICU_IPR192_ADDR ( ( volatile uint8_t __evenaccess * )0x000873C0 )
1157#define ICU_IPR193_ADDR ( ( volatile uint8_t __evenaccess * )0x000873C1 )
1158#define ICU_IPR194_ADDR ( ( volatile uint8_t __evenaccess * )0x000873C2 )
1159#define ICU_IPR195_ADDR ( ( volatile uint8_t __evenaccess * )0x000873C3 )
1160#define ICU_IPR196_ADDR ( ( volatile uint8_t __evenaccess * )0x000873C4 )
1161#define ICU_IPR197_ADDR ( ( volatile uint8_t __evenaccess * )0x000873C5 )
1162#define ICU_IPR198_ADDR ( ( volatile uint8_t __evenaccess * )0x000873C6 )
1163#define ICU_IPR199_ADDR ( ( volatile uint8_t __evenaccess * )0x000873C7 )
1164#define ICU_IPR200_ADDR ( ( volatile uint8_t __evenaccess * )0x000873C8 )
1165#define ICU_IPR201_ADDR ( ( volatile uint8_t __evenaccess * )0x000873C9 )
1166#define ICU_IPR202_ADDR ( ( volatile uint8_t __evenaccess * )0x000873CA )
1167#define ICU_IPR203_ADDR ( ( volatile uint8_t __evenaccess * )0x000873CB )
1168#define ICU_IPR204_ADDR ( ( volatile uint8_t __evenaccess * )0x000873CC )
1169#define ICU_IPR205_ADDR ( ( volatile uint8_t __evenaccess * )0x000873CD )
1170#define ICU_IPR206_ADDR ( ( volatile uint8_t __evenaccess * )0x000873CE )
1171#define ICU_IPR207_ADDR ( ( volatile uint8_t __evenaccess * )0x000873CF )
1172#define ICU_IPR208_ADDR ( ( volatile uint8_t __evenaccess * )0x000873D0 )
1173#define ICU_IPR209_ADDR ( ( volatile uint8_t __evenaccess * )0x000873D1 )
1174#define ICU_IPR210_ADDR ( ( volatile uint8_t __evenaccess * )0x000873D2 )
1175#define ICU_IPR211_ADDR ( ( volatile uint8_t __evenaccess * )0x000873D3 )
1176#define ICU_IPR212_ADDR ( ( volatile uint8_t __evenaccess * )0x000873D4 )
1177#define ICU_IPR213_ADDR ( ( volatile uint8_t __evenaccess * )0x000873D5 )
1178#define ICU_IPR214_ADDR ( ( volatile uint8_t __evenaccess * )0x000873D6 )
1179#define ICU_IPR215_ADDR ( ( volatile uint8_t __evenaccess * )0x000873D7 )
1180#define ICU_IPR216_ADDR ( ( volatile uint8_t __evenaccess * )0x000873D8 )
1181#define ICU_IPR217_ADDR ( ( volatile uint8_t __evenaccess * )0x000873D9 )
1182#define ICU_IPR218_ADDR ( ( volatile uint8_t __evenaccess * )0x000873DA )
1183#define ICU_IPR219_ADDR ( ( volatile uint8_t __evenaccess * )0x000873DB )
1184#define ICU_IPR220_ADDR ( ( volatile uint8_t __evenaccess * )0x000873DC )
1185#define ICU_IPR221_ADDR ( ( volatile uint8_t __evenaccess * )0x000873DD )
1186#define ICU_IPR222_ADDR ( ( volatile uint8_t __evenaccess * )0x000873DE )
1187#define ICU_IPR223_ADDR ( ( volatile uint8_t __evenaccess * )0x000873DF )
1188#define ICU_IPR224_ADDR ( ( volatile uint8_t __evenaccess * )0x000873E0 )
1189#define ICU_IPR225_ADDR ( ( volatile uint8_t __evenaccess * )0x000873E1 )
1190#define ICU_IPR226_ADDR ( ( volatile uint8_t __evenaccess * )0x000873E2 )
1191#define ICU_IPR227_ADDR ( ( volatile uint8_t __evenaccess * )0x000873E3 )
1192#define ICU_IPR228_ADDR ( ( volatile uint8_t __evenaccess * )0x000873E4 )
1193#define ICU_IPR229_ADDR ( ( volatile uint8_t __evenaccess * )0x000873E5 )
1194#define ICU_IPR230_ADDR ( ( volatile uint8_t __evenaccess * )0x000873E6 )
1195#define ICU_IPR231_ADDR ( ( volatile uint8_t __evenaccess * )0x000873E7 )
1196#define ICU_IPR232_ADDR ( ( volatile uint8_t __evenaccess * )0x000873E8 )
1197#define ICU_IPR233_ADDR ( ( volatile uint8_t __evenaccess * )0x000873E9 )
1198#define ICU_IPR234_ADDR ( ( volatile uint8_t __evenaccess * )0x000873EA )
1199#define ICU_IPR235_ADDR ( ( volatile uint8_t __evenaccess * )0x000873EB )
1200#define ICU_IPR236_ADDR ( ( volatile uint8_t __evenaccess * )0x000873EC )
1201#define ICU_IPR237_ADDR ( ( volatile uint8_t __evenaccess * )0x000873ED )
1202#define ICU_IPR238_ADDR ( ( volatile uint8_t __evenaccess * )0x000873EE )
1203#define ICU_IPR239_ADDR ( ( volatile uint8_t __evenaccess * )0x000873EF )
1204#define ICU_IPR240_ADDR ( ( volatile uint8_t __evenaccess * )0x000873F0 )
1205#define ICU_IPR241_ADDR ( ( volatile uint8_t __evenaccess * )0x000873F1 )
1206#define ICU_IPR242_ADDR ( ( volatile uint8_t __evenaccess * )0x000873F2 )
1207#define ICU_IPR243_ADDR ( ( volatile uint8_t __evenaccess * )0x000873F3 )
1208#define ICU_IPR244_ADDR ( ( volatile uint8_t __evenaccess * )0x000873F4 )
1209#define ICU_IPR245_ADDR ( ( volatile uint8_t __evenaccess * )0x000873F5 )
1210#define ICU_IPR246_ADDR ( ( volatile uint8_t __evenaccess * )0x000873F6 )
1211#define ICU_IPR247_ADDR ( ( volatile uint8_t __evenaccess * )0x000873F7 )
1212#define ICU_IPR248_ADDR ( ( volatile uint8_t __evenaccess * )0x000873F8 )
1213#define ICU_IPR249_ADDR ( ( volatile uint8_t __evenaccess * )0x000873F9 )
1214#define ICU_IPR250_ADDR ( ( volatile uint8_t __evenaccess * )0x000873FA )
1215#define ICU_IPR251_ADDR ( ( volatile uint8_t __evenaccess * )0x000873FB )
1216#define ICU_IPR252_ADDR ( ( volatile uint8_t __evenaccess * )0x000873FC )
1217#define ICU_IPR253_ADDR ( ( volatile uint8_t __evenaccess * )0x000873FD )
1218#define ICU_IPR254_ADDR ( ( volatile uint8_t __evenaccess * )0x000873FE )
1219#define ICU_IPR255_ADDR ( ( volatile uint8_t __evenaccess * )0x000873FF )
1220#define ICU_IPR_BIT ( 7U << 0U )
1221
1222
1223/*
1224 * IRQƒRƒ“ƒgƒ[ƒ‹ƒŒƒWƒXƒ^
1225 */
1226#define ICU_IRQ0_ADDR ( ( volatile uint8_t __evenaccess * )0x00087500 )
1227#define ICU_IRQ1_ADDR ( ( volatile uint8_t __evenaccess * )0x00087501 )
1228#define ICU_IRQ2_ADDR ( ( volatile uint8_t __evenaccess * )0x00087502 )
1229#define ICU_IRQ3_ADDR ( ( volatile uint8_t __evenaccess * )0x00087503 )
1230#define ICU_IRQ4_ADDR ( ( volatile uint8_t __evenaccess * )0x00087504 )
1231#define ICU_IRQ5_ADDR ( ( volatile uint8_t __evenaccess * )0x00087505 )
1232#define ICU_IRQ6_ADDR ( ( volatile uint8_t __evenaccess * )0x00087506 )
1233#define ICU_IRQ7_ADDR ( ( volatile uint8_t __evenaccess * )0x00087507 )
1234#define ICU_IRQ8_ADDR ( ( volatile uint8_t __evenaccess * )0x00087508 )
1235#define ICU_IRQ9_ADDR ( ( volatile uint8_t __evenaccess * )0x00087509 )
1236#define ICU_IRQ10_ADDR ( ( volatile uint8_t __evenaccess * )0x0008750A )
1237#define ICU_IRQ11_ADDR ( ( volatile uint8_t __evenaccess * )0x0008750B )
1238#define ICU_IRQ12_ADDR ( ( volatile uint8_t __evenaccess * )0x0008750C )
1239#define ICU_IRQ13_ADDR ( ( volatile uint8_t __evenaccess * )0x0008750D )
1240#define ICU_IRQ14_ADDR ( ( volatile uint8_t __evenaccess * )0x0008750E )
1241#define ICU_IRQ15_ADDR ( ( volatile uint8_t __evenaccess * )0x0008750F )
1242#define ICU_IRQMD_BIT ( 3U << 2U )
1243
1244
1245/*
1246 * Šeƒ`ƒƒƒ“ƒlƒ‹‚̃ŒƒWƒXƒ^‹y‚ѐݒèƒrƒbƒgî•ñ
1247 */
1248#define CMT_CMSTR0_ADDR ( ( volatile uint16_t __evenaccess * )0x00088000 )
1249#define CMT_CMSTR0_STR0_BIT ( 1U << 0U )
1250#define CMT_CMSTR0_STR1_BIT ( 1U << 1U )
1251#define CMT_CMSTR1_ADDR ( ( volatile uint16_t __evenaccess * )0x00088010 )
1252#define CMT_CMSTR1_STR2_BIT ( 1U << 0U )
1253#define CMT_CMSTR1_STR3_BIT ( 1U << 1U )
1254#define CMT0_CMCR_ADDR ( ( volatile uint16_t __evenaccess * )0x00088002 )
1255#define CMT0_CMCR_CKS_BIT ( 3U )
1256#define CMT0_CMCR_CMIE_BIT ( 1U << 6U )
1257#define CMT1_CMCR_ADDR ( ( volatile uint16_t __evenaccess * )0x00088008 )
1258#define CMT1_CMCR_CKS_BIT ( 3U )
1259#define CMT1_CMCR_CMIE_BIT ( 1U << 6U )
1260#define CMT2_CMCR_ADDR ( ( volatile uint16_t __evenaccess * )0x00088012 )
1261#define CMT2_CMCR_CKS_BIT ( 3U)
1262#define CMT2_CMCR_CMIE_BIT ( 1U << 6U )
1263#define CMT3_CMCR_ADDR ( ( volatile uint16_t __evenaccess * )0x00088018 )
1264#define CMT3_CMCR_CKS_BIT ( 3U )
1265#define CMT3_CMCR_CMIE_BIT ( 1U << 6U )
1266#define CMT0_CMCNT_ADDR ( ( volatile uint16_t __evenaccess * )0x00088004 )
1267#define CMT1_CMCNT_ADDR ( ( volatile uint16_t __evenaccess * )0x0008800A )
1268#define CMT2_CMCNT_ADDR ( ( volatile uint16_t __evenaccess * )0x00088014 )
1269#define CMT3_CMCNT_ADDR ( ( volatile uint16_t __evenaccess * )0x0008801A )
1270#define CMT0_CMCOR_ADDR ( ( volatile uint16_t __evenaccess * )0x00088006 )
1271#define CMT1_CMCOR_ADDR ( ( volatile uint16_t __evenaccess * )0x0008800C )
1272#define CMT2_CMCOR_ADDR ( ( volatile uint16_t __evenaccess * )0x00088016 )
1273#define CMT3_CMCOR_ADDR ( ( volatile uint16_t __evenaccess * )0x0008801C )
1274
1275#define SCI0_SMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A000 )
1276#define SCI0_BRR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A001 )
1277#define SCI0_SCR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A002 )
1278#define SCI0_TDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A003 )
1279#define SCI0_SSR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A004 )
1280#define SCI0_RDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A005 )
1281#define SCI0_SCMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A006 )
1282#define SCI0_SEMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A007 )
1283#define SCI1_SMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A020 )
1284#define SCI1_BRR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A021 )
1285#define SCI1_SCR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A022 )
1286#define SCI1_TDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A023 )
1287#define SCI1_SSR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A024 )
1288#define SCI1_RDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A025 )
1289#define SCI1_SCMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A026 )
1290#define SCI1_SEMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A027 )
1291#define SCI2_SMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A040 )
1292#define SCI2_BRR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A041 )
1293#define SCI2_SCR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A042 )
1294#define SCI2_TDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A043 )
1295#define SCI2_SSR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A044 )
1296#define SCI2_RDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A045 )
1297#define SCI2_SCMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A046 )
1298#define SCI2_SEMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A047 )
1299#define SCI3_SMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A060 )
1300#define SCI3_BRR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A061 )
1301#define SCI3_SCR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A062 )
1302#define SCI3_TDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A063 )
1303#define SCI3_SSR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A064 )
1304#define SCI3_RDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A065 )
1305#define SCI3_SCMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A066 )
1306#define SCI3_SEMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A067 )
1307#define SCI4_SMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A080 )
1308#define SCI4_BRR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A081 )
1309#define SCI4_SCR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A082 )
1310#define SCI4_TDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A083 )
1311#define SCI4_SSR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A084 )
1312#define SCI4_RDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A085 )
1313#define SCI4_SCMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A086 )
1314#define SCI4_SEMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A087 )
1315#define SCI5_SMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A0A0 )
1316#define SCI5_BRR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A0A1 )
1317#define SCI5_SCR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A0A2 )
1318#define SCI5_TDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A0A3 )
1319#define SCI5_SSR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A0A4 )
1320#define SCI5_RDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A0A5 )
1321#define SCI5_SCMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A0A6 )
1322#define SCI5_SEMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A0A7 )
1323#define SCI6_SMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A0C0 )
1324#define SCI6_BRR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A0C1 )
1325#define SCI6_SCR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A0C2 )
1326#define SCI6_TDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A0C3 )
1327#define SCI6_SSR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A0C4 )
1328#define SCI6_RDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A0C5 )
1329#define SCI6_SCMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A0C6 )
1330#define SCI6_SEMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008A0C7 )
1331#define SCI_SMR_CKS_BIT ( 3U << 0U )
1332#define SCI_SMR_STOP_BIT ( 1U << 3U )
1333#define SCI_SMR_PM_BIT ( 1U << 4U )
1334#define SCI_SMR_PE_BIT ( 1U << 5U )
1335#define SCI_SMR_CHR_BIT ( 1U << 6U )
1336#define SCI_SMR_CM_BIT ( 1U << 7U )
1337#define SCI_SCR_CKE_BIT ( 3U << 0U )
1338#define SCI_SCR_TEIE_BIT ( 1U << 2U )
1339#define SCI_SCR_RE_BIT ( 1U << 4U )
1340#define SCI_SCR_TE_BIT ( 1U << 5U )
1341#define SCI_SCR_RIE_BIT ( 1U << 6U )
1342#define SCI_SCR_TIE_BIT ( 1U << 7U )
1343#define SCI_SSR_TEND_BIT ( 1U << 2U )
1344#define SCI_SSR_PER_BIT ( 1U << 3U )
1345#define SCI_SSR_FER_BIT ( 1U << 4U )
1346#define SCI_SSR_ORER_BIT ( 1U << 5U )
1347#define SCI_SCMR_SMIF_BIT ( 1U << 0U )
1348#define SCI_SCMR_SINV_BIT ( 1U << 2U )
1349#define SCI_SCMR_SDIR_BIT ( 1U << 3U )
1350#define SCI_SCMR_BCP2_BIT ( 1U << 7U )
1351#define SCI_SEMR_ACS0_BIT ( 1U << 0U )
1352#define SCI_SEMR_ABCS_BIT ( 1U << 4U )
1353
1354/*
1355 * I/Oƒ|[ƒg‚̃ŒƒWƒXƒ^‹y‚ѐݒèƒrƒbƒgî•ñ
1356 */
1357#define PORT0_PDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C000 )
1358#define PORT1_PDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C001 )
1359#define PORT2_PDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C002 )
1360#define PORT3_PDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C003 )
1361#define PORT4_PDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C004 )
1362#define PORT5_PDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C005 )
1363#define PORT6_PDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C006 )
1364#define PORT7_PDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C007 )
1365#define PORT8_PDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C008 )
1366#define PORT9_PDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C009 )
1367#define PORTA_PDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C00A )
1368#define PORTB_PDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C00B )
1369#define PORTC_PDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C00C )
1370#define PORTD_PDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C00D )
1371#define PORTE_PDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C00E )
1372#define PORTF_PDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C00F )
1373#define PORTG_PDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C010 )
1374#define PORTJ_PDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C012 )
1375#define PORT_PDR_B0_BIT ( 0x01U << 0U )
1376#define PORT_PDR_B1_BIT ( 0x01U << 1U )
1377#define PORT_PDR_B2_BIT ( 0x01U << 2U )
1378#define PORT_PDR_B3_BIT ( 0x01U << 3U )
1379#define PORT_PDR_B4_BIT ( 0x01U << 4U )
1380#define PORT_PDR_B5_BIT ( 0x01U << 5U )
1381#define PORT_PDR_B6_BIT ( 0x01U << 6U )
1382#define PORT_PDR_B7_BIT ( 0x01U << 7U )
1383#define PORT0_PODR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C020 )
1384#define PORT1_PODR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C021 )
1385#define PORT2_PODR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C022 )
1386#define PORT3_PODR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C023 )
1387#define PORT4_PODR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C024 )
1388#define PORT5_PODR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C025 )
1389#define PORT6_PODR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C026 )
1390#define PORT7_PODR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C027 )
1391#define PORT8_PODR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C028 )
1392#define PORT9_PODR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C029 )
1393#define PORTA_PODR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C02A )
1394#define PORTB_PODR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C02B )
1395#define PORTC_PODR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C02C )
1396#define PORTD_PODR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C02D )
1397#define PORTE_PODR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C02E )
1398#define PORTF_PODR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C02F )
1399#define PORTG_PODR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C030 )
1400#define PORTJ_PODR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C032 )
1401#define PORT_PODR_B0_BIT ( 0x01U << 0U )
1402#define PORT_PODR_B1_BIT ( 0x01U << 1U )
1403#define PORT_PODR_B2_BIT ( 0x01U << 2U )
1404#define PORT_PODR_B3_BIT ( 0x01U << 3U )
1405#define PORT_PODR_B4_BIT ( 0x01U << 4U )
1406#define PORT_PODR_B5_BIT ( 0x01U << 5U )
1407#define PORT_PODR_B6_BIT ( 0x01U << 6U )
1408#define PORT_PODR_B7_BIT ( 0x01U << 7U )
1409#define PORT0_PIDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C040 )
1410#define PORT1_PIDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C041 )
1411#define PORT2_PIDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C042 )
1412#define PORT3_PIDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C043 )
1413#define PORT4_PIDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C044 )
1414#define PORT5_PIDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C045 )
1415#define PORT6_PIDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C046 )
1416#define PORT7_PIDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C047 )
1417#define PORT8_PIDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C048 )
1418#define PORT9_PIDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C049 )
1419#define PORTA_PIDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C04A )
1420#define PORTB_PIDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C04B )
1421#define PORTC_PIDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C04C )
1422#define PORTD_PIDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C04D )
1423#define PORTE_PIDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C04E )
1424#define PORTF_PIDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C04F )
1425#define PORTG_PIDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C050 )
1426#define PORTJ_PIDR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C052 )
1427#define PORT_PIDR_B0_BIT ( 0x01U << 0U )
1428#define PORT_PIDR_B1_BIT ( 0x01U << 1U )
1429#define PORT_PIDR_B2_BIT ( 0x01U << 2U )
1430#define PORT_PIDR_B3_BIT ( 0x01U << 3U )
1431#define PORT_PIDR_B4_BIT ( 0x01U << 4U )
1432#define PORT_PIDR_B5_BIT ( 0x01U << 5U )
1433#define PORT_PIDR_B6_BIT ( 0x01U << 6U )
1434#define PORT_PIDR_B7_BIT ( 0x01U << 7U )
1435#define PORT0_PMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C060 )
1436#define PORT1_PMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C061 )
1437#define PORT2_PMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C062 )
1438#define PORT3_PMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C063 )
1439#define PORT4_PMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C064 )
1440#define PORT5_PMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C065 )
1441#define PORT6_PMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C066 )
1442#define PORT7_PMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C067 )
1443#define PORT8_PMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C068 )
1444#define PORT9_PMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C069 )
1445#define PORTA_PMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C06A )
1446#define PORTB_PMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C06B )
1447#define PORTC_PMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C06C )
1448#define PORTD_PMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C06D )
1449#define PORTE_PMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C06E )
1450#define PORTF_PMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C06F )
1451#define PORTG_PMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C070 )
1452#define PORTJ_PMR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C072 )
1453#define PORT_PMR_B0_BIT ( 0x01U << 0U )
1454#define PORT_PMR_B1_BIT ( 0x01U << 1U )
1455#define PORT_PMR_B2_BIT ( 0x01U << 2U )
1456#define PORT_PMR_B3_BIT ( 0x01U << 3U )
1457#define PORT_PMR_B4_BIT ( 0x01U << 4U )
1458#define PORT_PMR_B5_BIT ( 0x01U << 5U )
1459#define PORT_PMR_B6_BIT ( 0x01U << 6U )
1460#define PORT_PMR_B7_BIT ( 0x01U << 7U )
1461#define PORT0_PCR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C0C0 )
1462#define PORT1_PCR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C0C1 )
1463#define PORT2_PCR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C0C2 )
1464#define PORT3_PCR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C0C3 )
1465#define PORT4_PCR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C0C4 )
1466#define PORT5_PCR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C0C5 )
1467#define PORT6_PCR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C0C6 )
1468#define PORT7_PCR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C0C7 )
1469#define PORT8_PCR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C0C8 )
1470#define PORT9_PCR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C0C9 )
1471#define PORTA_PCR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C0CA )
1472#define PORTB_PCR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C0CB )
1473#define PORTC_PCR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C0CC )
1474#define PORTD_PCR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C0CD )
1475#define PORTE_PCR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C0CE )
1476#define PORTF_PCR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C0CF )
1477#define PORTG_PCR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C0D0 )
1478#define PORTJ_PCR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C0D2 )
1479#define PORT_PCR_B0_BIT ( 0x01U << 0U )
1480#define PORT_PCR_B1_BIT ( 0x01U << 1U )
1481#define PORT_PCR_B2_BIT ( 0x01U << 2U )
1482#define PORT_PCR_B3_BIT ( 0x01U << 3U )
1483#define PORT_PCR_B4_BIT ( 0x01U << 4U )
1484#define PORT_PCR_B5_BIT ( 0x01U << 5U )
1485#define PORT_PCR_B6_BIT ( 0x01U << 6U )
1486#define PORT_PCR_B7_BIT ( 0x01U << 7U )
1487#define PORT0_ODR0_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C080 )
1488#define PORT1_ODR0_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C082 )
1489#define PORT2_ODR0_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C084 )
1490#define PORT3_ODR0_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C086 )
1491#define PORT4_ODR0_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C088 )
1492#define PORT5_ODR0_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C08A )
1493#define PORT6_ODR0_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C08C )
1494#define PORT7_ODR0_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C08E )
1495#define PORT8_ODR0_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C090 )
1496#define PORT9_ODR0_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C092 )
1497#define PORTA_ODR0_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C094 )
1498#define PORTB_ODR0_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C096 )
1499#define PORTC_ODR0_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C098 )
1500#define PORTD_ODR0_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C09A )
1501#define PORTE_ODR0_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C09C )
1502#define PORTF_ODR0_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C09E )
1503#define PORTG_ODR0_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C0A0 )
1504#define PORTJ_ODR0_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C0A4 )
1505#define PORT0_ODR1_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C081 )
1506#define PORT1_ODR1_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C083 )
1507#define PORT2_ODR1_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C085 )
1508#define PORT3_ODR1_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C087 )
1509#define PORT4_ODR1_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C089 )
1510#define PORT5_ODR1_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C08B )
1511#define PORT6_ODR1_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C08D )
1512#define PORT7_ODR1_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C08F )
1513#define PORT8_ODR1_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C091 )
1514#define PORT9_ODR1_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C093 )
1515#define PORTA_ODR1_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C095 )
1516#define PORTB_ODR1_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C097 )
1517#define PORTC_ODR1_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C099 )
1518#define PORTD_ODR1_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C09B )
1519#define PORTE_ODR1_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C09D )
1520#define PORTF_ODR1_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C09F )
1521#define PORTG_ODR1_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C0A1 )
1522#define PORTJ_ODR1_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C0A5 )
1523
1524/*
1525 * ƒ}ƒ‹ƒ`ƒtƒ@ƒ“ƒNƒVƒ‡ƒ“ƒsƒ“ƒRƒ“ƒgƒ[ƒ‰‚̃ŒƒWƒXƒ^î•ñ
1526 */
1527#define MPC_PFUSB0_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C114 )
1528#define MPC_PFUSB0_PDHZS_BIT ( 0x01U << 2U )
1529#define MPC_PFUSB0_PUPHZS_BIT ( 0x01U << 3U )
1530#define MPC_PWPR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C11F )
1531#define MPC_PWPR_PFSWE ( 0x01U << 6U )
1532#define MPC_PWPR_B0WI ( 0x01U << 7U )
1533#define MPC_P00PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C140 )
1534#define MPC_P01PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C141 )
1535#define MPC_P02PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C142 )
1536#define MPC_P03PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C143 )
1537#define MPC_P04PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C144 )
1538#define MPC_P05PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C145 )
1539#define MPC_P06PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C146 )
1540#define MPC_P07PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C147 )
1541#define MPC_P10PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C148 )
1542#define MPC_P11PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C149 )
1543#define MPC_P12PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C14A )
1544#define MPC_P13PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C14B )
1545#define MPC_P14PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C14C )
1546#define MPC_P15PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C14D )
1547#define MPC_P16PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C14E )
1548#define MPC_P17PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C14F )
1549#define MPC_P20PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C150 )
1550#define MPC_P21PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C151 )
1551#define MPC_P22PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C152 )
1552#define MPC_P23PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C153 )
1553#define MPC_P24PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C154 )
1554#define MPC_P25PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C155 )
1555#define MPC_P26PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C156 )
1556#define MPC_P27PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C157 )
1557#define MPC_P30PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C158 )
1558#define MPC_P31PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C159 )
1559#define MPC_P32PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C15A )
1560#define MPC_P33PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C15B )
1561#define MPC_P34PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C15C )
1562#define MPC_P35PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C15D )
1563#define MPC_P36PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C15E )
1564#define MPC_P37PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C15F )
1565#define MPC_P40PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C160 )
1566#define MPC_P41PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C161 )
1567#define MPC_P42PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C162 )
1568#define MPC_P43PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C163 )
1569#define MPC_P44PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C164 )
1570#define MPC_P45PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C165 )
1571#define MPC_P46PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C166 )
1572#define MPC_P47PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C167 )
1573#define MPC_P50PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C168 )
1574#define MPC_P51PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C169 )
1575#define MPC_P52PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C16A )
1576#define MPC_P53PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C16B )
1577#define MPC_P54PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C16C )
1578#define MPC_P55PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C16D )
1579#define MPC_P56PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C16E )
1580#define MPC_P57PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C16F )
1581#define MPC_P60PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C170 )
1582#define MPC_P61PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C171 )
1583#define MPC_P62PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C172 )
1584#define MPC_P63PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C173 )
1585#define MPC_P64PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C174 )
1586#define MPC_P65PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C175 )
1587#define MPC_P66PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C176 )
1588#define MPC_P67PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C177 )
1589#define MPC_P70PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C178 )
1590#define MPC_P71PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C179 )
1591#define MPC_P72PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C17A )
1592#define MPC_P73PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C17B )
1593#define MPC_P74PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C17C )
1594#define MPC_P75PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C17D )
1595#define MPC_P76PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C17E )
1596#define MPC_P77PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C17F )
1597#define MPC_P80PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C180 )
1598#define MPC_P81PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C181 )
1599#define MPC_P82PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C182 )
1600#define MPC_P83PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C183 )
1601#define MPC_P84PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C184 )
1602#define MPC_P85PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C185 )
1603#define MPC_P86PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C186 )
1604#define MPC_P87PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C187 )
1605#define MPC_P90PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C188 )
1606#define MPC_P91PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C189 )
1607#define MPC_P92PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C18A )
1608#define MPC_P93PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C18B )
1609#define MPC_P94PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C18C )
1610#define MPC_P95PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C18D )
1611#define MPC_P96PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C18E )
1612#define MPC_P97PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C18F )
1613#define MPC_PA0PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C190 )
1614#define MPC_PA1PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C191 )
1615#define MPC_PA2PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C192 )
1616#define MPC_PA3PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C193 )
1617#define MPC_PA4PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C194 )
1618#define MPC_PA5PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C195 )
1619#define MPC_PA6PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C196 )
1620#define MPC_PA7PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C197 )
1621#define MPC_PB0PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C198 )
1622#define MPC_PB1PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C199 )
1623#define MPC_PB2PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C19A )
1624#define MPC_PB3PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C19B )
1625#define MPC_PB4PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C19C )
1626#define MPC_PB5PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C19D )
1627#define MPC_PB6PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C19E )
1628#define MPC_PB7PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C19F )
1629#define MPC_PC0PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C1A0 )
1630#define MPC_PC1PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C1A1 )
1631#define MPC_PC2PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C1A2 )
1632#define MPC_PC3PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C1A3 )
1633#define MPC_PC4PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C1A4 )
1634#define MPC_PC5PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C1A5 )
1635#define MPC_PC6PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C1A6 )
1636#define MPC_PC7PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C1A7 )
1637#define MPC_PD0PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C1A8 )
1638#define MPC_PD1PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C1A9 )
1639#define MPC_PD2PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C1AA )
1640#define MPC_PD3PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C1AB )
1641#define MPC_PD4PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C1AC )
1642#define MPC_PD5PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C1AD )
1643#define MPC_PD6PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C1AE )
1644#define MPC_PD7PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C1AF )
1645#define MPC_PE0PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C1B0 )
1646#define MPC_PE1PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C1B1 )
1647#define MPC_PE2PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C1B2 )
1648#define MPC_PE3PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C1B3 )
1649#define MPC_PE4PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C1B4 )
1650#define MPC_PE5PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C1B5 )
1651#define MPC_PE6PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C1B6 )
1652#define MPC_PE7PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C1B7 )
1653#define MPC_PF0PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C1B8 )
1654#define MPC_PF1PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C1B9 )
1655#define MPC_PF2PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C1BA )
1656#define MPC_PF3PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C1BB )
1657#define MPC_PF4PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C1BC )
1658#define MPC_PF5PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C1BD )
1659#define MPC_PF6PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C1BE )
1660#define MPC_PF7PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C1BF )
1661#define MPC_PJ3PFS_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C1D3 )
1662
1663/*
1664 * ƒŠƒAƒ‹ƒ^ƒCƒ€ƒNƒƒbƒN
1665 */
1666#define RTC_R64CNT_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C400 )
1667#define RTC_RSECCNT_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C402 )
1668#define RTC_RMINCNT_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C404 )
1669#define RTC_RHRCNT_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C406 )
1670#define RTC_RWKCNT_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C408 )
1671#define RTC_RDAYCNT_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C40A )
1672#define RTC_RMONCNT_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C40C )
1673#define RTC_RYRCNT_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C40E )
1674
1675/*
1676 * 12 ƒrƒbƒgA/D ƒRƒ“ƒo[ƒ^
1677 */
1678#define S12AD_ADCSR_ADDR ( ( volatile uint8_t __evenaccess * )0x00089000 )
1679#define S12AD_ADCSR_ADST_BIT 0x80
1680#define S12AD_ADANS0_ADDR ( ( volatile uint16_t __evenaccess * )0x00089004 )
1681#define S12AD_ADANS1_ADDR ( ( volatile uint16_t __evenaccess * )0x00089006 )
1682#define S12AD_ADEXICR_ADDR ( ( volatile uint16_t __evenaccess * )0x00089012 )
1683#define S12AD_ADDR0_ADDR ( ( volatile uint16_t __evenaccess * )0x00089020 )
1684#define S12AD_ADDR1_ADDR ( ( volatile uint16_t __evenaccess * )0x00089022 )
1685#define S12AD_ADDR2_ADDR ( ( volatile uint16_t __evenaccess * )0x00089024 )
1686#define S12AD_ADDR3_ADDR ( ( volatile uint16_t __evenaccess * )0x00089026 )
1687#define S12AD_ADDR4_ADDR ( ( volatile uint16_t __evenaccess * )0x00089028 )
1688#define S12AD_ADDR5_ADDR ( ( volatile uint16_t __evenaccess * )0x0008902A )
1689#define S12AD_ADDR6_ADDR ( ( volatile uint16_t __evenaccess * )0x0008902C )
1690#define S12AD_ADDR7_ADDR ( ( volatile uint16_t __evenaccess * )0x0008902E )
1691#define S12AD_ADDR8_ADDR ( ( volatile uint16_t __evenaccess * )0x00089030 )
1692#define S12AD_ADDR9_ADDR ( ( volatile uint16_t __evenaccess * )0x00089032 )
1693#define S12AD_ADDR10_ADDR ( ( volatile uint16_t __evenaccess * )0x00089034 )
1694#define S12AD_ADDR11_ADDR ( ( volatile uint16_t __evenaccess * )0x00089036 )
1695#define S12AD_ADDR12_ADDR ( ( volatile uint16_t __evenaccess * )0x00089038 )
1696#define S12AD_ADDR13_ADDR ( ( volatile uint16_t __evenaccess * )0x0008903A )
1697#define S12AD_ADDR14_ADDR ( ( volatile uint16_t __evenaccess * )0x0008903C )
1698#define S12AD_ADDR15_ADDR ( ( volatile uint16_t __evenaccess * )0x0008903E )
1699#define S12AD_ADDR16_ADDR ( ( volatile uint16_t __evenaccess * )0x00089040 )
1700#define S12AD_ADDR17_ADDR ( ( volatile uint16_t __evenaccess * )0x00089042 )
1701#define S12AD_ADDR18_ADDR ( ( volatile uint16_t __evenaccess * )0x00089044 )
1702#define S12AD_ADDR19_ADDR ( ( volatile uint16_t __evenaccess * )0x00089046 )
1703#define S12AD_ADDR20_ADDR ( ( volatile uint16_t __evenaccess * )0x00089048 )
1704
1705#define TPU0_TCR_ADDR ( ( volatile uint8_t __evenaccess * )0x00088110 )
1706#define TPU1_TCR_ADDR ( ( volatile uint8_t __evenaccess * )0x00088120 )
1707#define TPU2_TCR_ADDR ( ( volatile uint8_t __evenaccess * )0x00088130 )
1708#define TPU3_TCR_ADDR ( ( volatile uint8_t __evenaccess * )0x00088140 )
1709#define TPU4_TCR_ADDR ( ( volatile uint8_t __evenaccess * )0x00088150 )
1710#define TPU5_TCR_ADDR ( ( volatile uint8_t __evenaccess * )0x00088160 )
1711#define TPU6_TCR_ADDR ( ( volatile uint8_t __evenaccess * )0x00088180 )
1712#define TPU7_TCR_ADDR ( ( volatile uint8_t __evenaccess * )0x00088190 )
1713#define TPU8_TCR_ADDR ( ( volatile uint8_t __evenaccess * )0x000881A0 )
1714#define TPU9_TCR_ADDR ( ( volatile uint8_t __evenaccess * )0x000881B0 )
1715#define TPU10_TCR_ADDR ( ( volatile uint8_t __evenaccess * )0x000881C0 )
1716#define TPU11_TCR_ADDR ( ( volatile uint8_t __evenaccess * )0x000881D0 )
1717#define TPU_TCR_TPSC_OFFSET ( 0U )
1718#define TPU_TCR_TPSC_MASK ( 0x7U << TPU_TCR_TPSC_OFFSET )
1719#define TPU_TCR_CKEG_OFFSET ( 3U )
1720#define TPU_TCR_CKEG_MASK ( 0x3U << TPU_TCR_CKEG_OFFSET )
1721#define TPU_TCR_CCLR_OFFSET ( 5U )
1722#define TPU_TCR_CCLR_MASK ( 0x7U << TPU_TCR_CCLR_OFFSET )
1723
1724#define TPU0_TMDR_ADDR ( ( volatile uint8_t __evenaccess * )0x00088111 )
1725#define TPU1_TMDR_ADDR ( ( volatile uint8_t __evenaccess * )0x00088121 )
1726#define TPU2_TMDR_ADDR ( ( volatile uint8_t __evenaccess * )0x00088131 )
1727#define TPU3_TMDR_ADDR ( ( volatile uint8_t __evenaccess * )0x00088141 )
1728#define TPU4_TMDR_ADDR ( ( volatile uint8_t __evenaccess * )0x00088151 )
1729#define TPU5_TMDR_ADDR ( ( volatile uint8_t __evenaccess * )0x00088161 )
1730#define TPU6_TMDR_ADDR ( ( volatile uint8_t __evenaccess * )0x00088181 )
1731#define TPU7_TMDR_ADDR ( ( volatile uint8_t __evenaccess * )0x00088191 )
1732#define TPU8_TMDR_ADDR ( ( volatile uint8_t __evenaccess * )0x000881A1 )
1733#define TPU9_TMDR_ADDR ( ( volatile uint8_t __evenaccess * )0x000881B1 )
1734#define TPU10_TMDR_ADDR ( ( volatile uint8_t __evenaccess * )0x000881C1 )
1735#define TPU11_TMDR_ADDR ( ( volatile uint8_t __evenaccess * )0x000881D1 )
1736
1737#define TPU0_TIOR_ADDR ( ( volatile uint8_t __evenaccess * )0x000881C0 )
1738#define TPU0_TIORH_ADDR ( ( volatile uint8_t __evenaccess * )0x00088112 )
1739#define TPU0_TIORL_ADDR ( ( volatile uint8_t __evenaccess * )0x00088113 )
1740#define TPU1_TIOR_ADDR ( ( volatile uint8_t __evenaccess * )0x00088122 )
1741#define TPU2_TIOR_ADDR ( ( volatile uint8_t __evenaccess * )0x00088132 )
1742#define TPU3_TIORH_ADDR ( ( volatile uint8_t __evenaccess * )0x00088142 )
1743#define TPU3_TIORL_ADDR ( ( volatile uint8_t __evenaccess * )0x00088143 )
1744#define TPU4_TIOR_ADDR ( ( volatile uint8_t __evenaccess * )0x00088152 )
1745#define TPU5_TIOR_ADDR ( ( volatile uint8_t __evenaccess * )0x00088162 )
1746#define TPU6_TIORH_ADDR ( ( volatile uint8_t __evenaccess * )0x00088182 )
1747#define TPU6_TIORL_ADDR ( ( volatile uint8_t __evenaccess * )0x00088183 )
1748#define TPU7_TIOR_ADDR ( ( volatile uint8_t __evenaccess * )0x00088192 )
1749#define TPU8_TIOR_ADDR ( ( volatile uint8_t __evenaccess * )0x000881A2 )
1750#define TPU9_TIORH_ADDR ( ( volatile uint8_t __evenaccess * )0x000881B2 )
1751#define TPU9_TIORL_ADDR ( ( volatile uint8_t __evenaccess * )0x000881B3 )
1752#define TPU10_TIOR_ADDR ( ( volatile uint8_t __evenaccess * )0x000881C2 )
1753#define TPU11_TIOR_ADDR ( ( volatile uint8_t __evenaccess * )0x000881D2 )
1754#define TPU_TIORL_IOA_OFFSET ( 0U )
1755#define TPU_TIORL_IOA_MASK ( 0xFU << TPU_TIORL_IOA_OFFSET )
1756#define TPU_TIORL_IOB_OFFSET ( 4U )
1757#define TPU_TIORL_IOB_MASK ( 0xFU << TPU_TIORL_IOB_OFFSET )
1758#define TPU_TIORL_IOC_OFFSET ( 0U )
1759#define TPU_TIORL_IOC_MASK ( 0xFU << TPU_TIORL_IOC_OFFSET )
1760#define TPU_TIORL_IOD_OFFSET ( 4U )
1761#define TPU_TIORL_IOD_MASK ( 0xFU << TPU_TIORL_IOD_OFFSET )
1762
1763#define TPU0_TGRA_ADDR ( ( volatile uint16_t __evenaccess * )0x00088118 )
1764#define TPU0_TGRB_ADDR ( ( volatile uint16_t __evenaccess * )0x0008811A )
1765#define TPU0_TGRC_ADDR ( ( volatile uint16_t __evenaccess * )0x0008811C )
1766#define TPU0_TGRD_ADDR ( ( volatile uint16_t __evenaccess * )0x0008811E )
1767#define TPU1_TGRA_ADDR ( ( volatile uint16_t __evenaccess * )0x00088128 )
1768#define TPU1_TGRB_ADDR ( ( volatile uint16_t __evenaccess * )0x0008812A )
1769#define TPU2_TGRA_ADDR ( ( volatile uint16_t __evenaccess * )0x00088138 )
1770#define TPU2_TGRB_ADDR ( ( volatile uint16_t __evenaccess * )0x0008813A )
1771#define TPU3_TGRA_ADDR ( ( volatile uint16_t __evenaccess * )0x00088148 )
1772#define TPU3_TGRB_ADDR ( ( volatile uint16_t __evenaccess * )0x0008814A )
1773#define TPU3_TGRC_ADDR ( ( volatile uint16_t __evenaccess * )0x0008814C )
1774#define TPU3_TGRD_ADDR ( ( volatile uint16_t __evenaccess * )0x0008814E )
1775#define TPU4_TGRA_ADDR ( ( volatile uint16_t __evenaccess * )0x00088158 )
1776#define TPU4_TGRB_ADDR ( ( volatile uint16_t __evenaccess * )0x0008815A )
1777#define TPU5_TGRA_ADDR ( ( volatile uint16_t __evenaccess * )0x00088168 )
1778#define TPU5_TGRB_ADDR ( ( volatile uint16_t __evenaccess * )0x0008816A )
1779#define TPU6_TGRA_ADDR ( ( volatile uint16_t __evenaccess * )0x00088188 )
1780#define TPU6_TGRB_ADDR ( ( volatile uint16_t __evenaccess * )0x0008818A )
1781#define TPU6_TGRC_ADDR ( ( volatile uint16_t __evenaccess * )0x0008818C )
1782#define TPU6_TGRD_ADDR ( ( volatile uint16_t __evenaccess * )0x0008818E )
1783#define TPU7_TGRA_ADDR ( ( volatile uint16_t __evenaccess * )0x00088198 )
1784#define TPU7_TGRB_ADDR ( ( volatile uint16_t __evenaccess * )0x0008819A )
1785#define TPU8_TGRA_ADDR ( ( volatile uint16_t __evenaccess * )0x000881A8 )
1786#define TPU8_TGRB_ADDR ( ( volatile uint16_t __evenaccess * )0x000881AA )
1787#define TPU9_TGRA_ADDR ( ( volatile uint16_t __evenaccess * )0x000881B8 )
1788#define TPU9_TGRB_ADDR ( ( volatile uint16_t __evenaccess * )0x000881BA )
1789#define TPU9_TGRC_ADDR ( ( volatile uint16_t __evenaccess * )0x000881BC )
1790#define TPU9_TGRD_ADDR ( ( volatile uint16_t __evenaccess * )0x000881BE )
1791#define TPU10_TGRA_ADDR ( ( volatile uint16_t __evenaccess * )0x000881C8 )
1792#define TPU10_TGRB_ADDR ( ( volatile uint16_t __evenaccess * )0x000881CA )
1793#define TPU11_TGRA_ADDR ( ( volatile uint16_t __evenaccess * )0x000881D8 )
1794#define TPU11_TGRB_ADDR ( ( volatile uint16_t __evenaccess * )0x000881DA )
1795
1796#define TPUA_TSTR_ADDR ( ( volatile uint8_t __evenaccess * )0x00088100 )
1797#define TPUB_TSTR_ADDR ( ( volatile uint8_t __evenaccess * )0x00088170 )
1798#define TPU_TSTR_CST0_BIT ( 0x01U << 0U )
1799#define TPU_TSTR_CST1_BIT ( 0x01U << 1U )
1800#define TPU_TSTR_CST2_BIT ( 0x01U << 2U )
1801#define TPU_TSTR_CST3_BIT ( 0x01U << 3U )
1802#define TPU_TSTR_CST4_BIT ( 0x01U << 4U )
1803#define TPU_TSTR_CST5_BIT ( 0x01U << 5U )
1804
1805#define TPUA_TSYR_ADDR ( ( volatile uint8_t __evenaccess * )0x00088101 )
1806#define TPUB_TSYR_ADDR ( ( volatile uint8_t __evenaccess * )0x00088171 )
1807#define TPU_TSYR_SYNC0_BIT ( 0x01U << 0U )
1808#define TPU_TSYR_SYNC1_BIT ( 0x01U << 1U )
1809#define TPU_TSYR_SYNC2_BIT ( 0x01U << 2U )
1810#define TPU_TSYR_SYNC3_BIT ( 0x01U << 3U )
1811#define TPU_TSYR_SYNC4_BIT ( 0x01U << 4U )
1812#define TPU_TSYR_SYNC5_BIT ( 0x01U << 5U )
1813
1814/*
1815 * RSPI
1816 */
1817#define RSPI0_SPCR_ADDR ( ( volatile uint8_t __evenaccess * )0x00088380 )
1818#define RSPI1_SPCR_ADDR ( ( volatile uint8_t __evenaccess * )0x000883A0 )
1819#define RSPI2_SPCR_ADDR ( ( volatile uint8_t __evenaccess * )0x000883C0 )
1820#define RSPI_SPCR_SPMS_BIT ( 0x01U << 0U )
1821#define RSPI_SPCR_TXMD_BIT ( 0x01U << 1U )
1822#define RSPI_SPCR_MODFEN_BIT ( 0x01U << 2U )
1823#define RSPI_SPCR_MSTR_BIT ( 0x01U << 3U )
1824#define RSPI_SPCR_SPEIE_BIT ( 0x01U << 4U )
1825#define RSPI_SPCR_SPTIE_BIT ( 0x01U << 5U )
1826#define RSPI_SPCR_SPE_BIT ( 0x01U << 6U )
1827#define RSPI_SPCR_SPRIE_BIT ( 0x01U << 7U )
1828
1829#define RSPI0_SSLP_ADDR ( ( volatile uint8_t __evenaccess * )0x00088381 )
1830#define RSPI1_SSLP_ADDR ( ( volatile uint8_t __evenaccess * )0x000883A1 )
1831#define RSPI2_SSLP_ADDR ( ( volatile uint8_t __evenaccess * )0x000883C1 )
1832
1833#define RSPI0_SPPCR_ADDR ( ( volatile uint8_t __evenaccess * )0x00088382 )
1834#define RSPI1_SPPCR_ADDR ( ( volatile uint8_t __evenaccess * )0x000883A2 )
1835#define RSPI2_SPPCR_ADDR ( ( volatile uint8_t __evenaccess * )0x000883C2 )
1836
1837#define RSPI0_SPSR_ADDR ( ( volatile uint8_t __evenaccess * )0x00088383 )
1838#define RSPI1_SPSR_ADDR ( ( volatile uint8_t __evenaccess * )0x000883A3 )
1839#define RSPI2_SPSR_ADDR ( ( volatile uint8_t __evenaccess * )0x000883C3 )
1840
1841#define RSPI0_SPDR_ADDR ( ( volatile uint32_t __evenaccess * )0x00088384 )
1842#define RSPI1_SPDR_ADDR ( ( volatile uint32_t __evenaccess * )0x000883A4 )
1843#define RSPI2_SPDR_ADDR ( ( volatile uint32_t __evenaccess * )0x000883C4 )
1844
1845#define RSPI0_SPSCR_ADDR ( ( volatile uint8_t __evenaccess * )0x00088388 )
1846#define RSPI1_SPSCR_ADDR ( ( volatile uint8_t __evenaccess * )0x000883A8 )
1847#define RSPI2_SPSCR_ADDR ( ( volatile uint8_t __evenaccess * )0x000883C8 )
1848
1849#define RSPI0_SPSSR_ADDR ( ( volatile uint8_t __evenaccess * )0x00088389 )
1850#define RSPI1_SPSSR_ADDR ( ( volatile uint8_t __evenaccess * )0x000883A9 )
1851#define RSPI2_SPSSR_ADDR ( ( volatile uint8_t __evenaccess * )0x000883C9 )
1852
1853#define RSPI0_SPBR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008838A )
1854#define RSPI1_SPBR_ADDR ( ( volatile uint8_t __evenaccess * )0x000883AA )
1855#define RSPI2_SPBR_ADDR ( ( volatile uint8_t __evenaccess * )0x000883CA )
1856
1857#define RSPI0_SPDCR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008838B )
1858#define RSPI1_SPDCR_ADDR ( ( volatile uint8_t __evenaccess * )0x000883AB )
1859#define RSPI2_SPDCR_ADDR ( ( volatile uint8_t __evenaccess * )0x000883CB )
1860
1861#define RSPI0_SPCKD_ADDR ( ( volatile uint8_t __evenaccess * )0x0008838C )
1862#define RSPI1_SPCKD_ADDR ( ( volatile uint8_t __evenaccess * )0x000883AC )
1863#define RSPI2_SPCKD_ADDR ( ( volatile uint8_t __evenaccess * )0x000883CC )
1864
1865#define RSPI0_SSLND_ADDR ( ( volatile uint8_t __evenaccess * )0x0008838D )
1866#define RSPI1_SSLND_ADDR ( ( volatile uint8_t __evenaccess * )0x000883AD )
1867#define RSPI2_SSLND_ADDR ( ( volatile uint8_t __evenaccess * )0x000883CD )
1868
1869#define RSPI0_SPND_ADDR ( ( volatile uint8_t __evenaccess * )0x0008838E )
1870#define RSPI1_SPND_ADDR ( ( volatile uint8_t __evenaccess * )0x000883AE )
1871#define RSPI2_SPND_ADDR ( ( volatile uint8_t __evenaccess * )0x000883CE )
1872
1873#define RSPI0_SPCR2_ADDR ( ( volatile uint8_t __evenaccess * )0x0008838F )
1874#define RSPI1_SPCR2_ADDR ( ( volatile uint8_t __evenaccess * )0x000883AF )
1875#define RSPI2_SPCR2_ADDR ( ( volatile uint8_t __evenaccess * )0x000883CF )
1876
1877#define RSPI0_SPCMD0_ADDR ( ( volatile uint16_t __evenaccess * )0x00088390 )
1878#define RSPI0_SPCMD1_ADDR ( ( volatile uint16_t __evenaccess * )0x00088392 )
1879#define RSPI0_SPCMD2_ADDR ( ( volatile uint16_t __evenaccess * )0x00088394 )
1880#define RSPI0_SPCMD3_ADDR ( ( volatile uint16_t __evenaccess * )0x00088396 )
1881#define RSPI0_SPCMD4_ADDR ( ( volatile uint16_t __evenaccess * )0x00088398 )
1882#define RSPI0_SPCMD5_ADDR ( ( volatile uint16_t __evenaccess * )0x0008839A )
1883#define RSPI0_SPCMD6_ADDR ( ( volatile uint16_t __evenaccess * )0x0008839C )
1884#define RSPI0_SPCMD7_ADDR ( ( volatile uint16_t __evenaccess * )0x0008839E )
1885#define RSPI1_SPCMD0_ADDR ( ( volatile uint16_t __evenaccess * )0x000883B0 )
1886#define RSPI1_SPCMD1_ADDR ( ( volatile uint16_t __evenaccess * )0x000883B2 )
1887#define RSPI1_SPCMD2_ADDR ( ( volatile uint16_t __evenaccess * )0x000883B4 )
1888#define RSPI1_SPCMD3_ADDR ( ( volatile uint16_t __evenaccess * )0x000883B6 )
1889#define RSPI1_SPCMD4_ADDR ( ( volatile uint16_t __evenaccess * )0x000883B8 )
1890#define RSPI1_SPCMD5_ADDR ( ( volatile uint16_t __evenaccess * )0x000883BA )
1891#define RSPI1_SPCMD6_ADDR ( ( volatile uint16_t __evenaccess * )0x000883BC )
1892#define RSPI1_SPCMD7_ADDR ( ( volatile uint16_t __evenaccess * )0x000883BE )
1893#define RSPI2_SPCMD0_ADDR ( ( volatile uint16_t __evenaccess * )0x000883D0 )
1894#define RSPI2_SPCMD1_ADDR ( ( volatile uint16_t __evenaccess * )0x000883D2 )
1895#define RSPI2_SPCMD2_ADDR ( ( volatile uint16_t __evenaccess * )0x000883D4 )
1896#define RSPI2_SPCMD3_ADDR ( ( volatile uint16_t __evenaccess * )0x000883D6 )
1897#define RSPI2_SPCMD4_ADDR ( ( volatile uint16_t __evenaccess * )0x000883D8 )
1898#define RSPI2_SPCMD5_ADDR ( ( volatile uint16_t __evenaccess * )0x000883DA )
1899#define RSPI2_SPCMD6_ADDR ( ( volatile uint16_t __evenaccess * )0x000883DC )
1900#define RSPI2_SPCMD7_ADDR ( ( volatile uint16_t __evenaccess * )0x000883DE )
1901#define RSPI_SPCMD_SPB_OFFSET (8)
1902#define RSPI_SPCMD_SPB_MASK (0xF << RSPI_SPCMD_SPB_OFFSET)
1903
1904/*
1905 * UARTŠÖ˜A‚Ì’è‹`
1906 *
1907 * pdic‚Ìrx600/rx630_uart.c‚ÅŽg—p‚·‚éD
1908 */
1909/*
1910 * ƒVƒŠƒAƒ‹I/O‚̌”
1911 */
1912#define TNUM_SIOP ( 2 )
1913
1914#endif /* TOPPERS_RX630_H */
1915
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