source: EcnlProtoTool/trunk/tcc-0.9.27/x86_64-gen.c@ 331

Last change on this file since 331 was 331, checked in by coas-nagasima, 6 years ago

prototoolに関連するプロジェクトをnewlibからmuslを使うよう変更・更新
ntshellをnewlibの下位の実装から、muslのsyscallの実装に変更・更新
以下のOSSをアップデート
・mruby-1.3.0
・musl-1.1.18
・onigmo-6.1.3
・tcc-0.9.27
以下のOSSを追加
・openssl-1.1.0e
・curl-7.57.0
・zlib-1.2.11
以下のmrbgemsを追加
・iij/mruby-digest
・iij/mruby-env
・iij/mruby-errno
・iij/mruby-iijson
・iij/mruby-ipaddr
・iij/mruby-mock
・iij/mruby-require
・iij/mruby-tls-openssl
  • Property svn:eol-style set to native
  • Property svn:mime-type set to text/x-csrc;charset=UTF-8
File size: 63.3 KB
Line 
1/*
2 * x86-64 code generator for TCC
3 *
4 * Copyright (c) 2008 Shinichiro Hamaji
5 *
6 * Based on i386-gen.c by Fabrice Bellard
7 *
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
12 *
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
17 *
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
23#ifdef TARGET_DEFS_ONLY
24
25/* number of available registers */
26#define NB_REGS 25
27#define NB_ASM_REGS 16
28#define CONFIG_TCC_ASM
29
30/* a register can belong to several classes. The classes must be
31 sorted from more general to more precise (see gv2() code which does
32 assumptions on it). */
33#define RC_INT 0x0001 /* generic integer register */
34#define RC_FLOAT 0x0002 /* generic float register */
35#define RC_RAX 0x0004
36#define RC_RCX 0x0008
37#define RC_RDX 0x0010
38#define RC_ST0 0x0080 /* only for long double */
39#define RC_R8 0x0100
40#define RC_R9 0x0200
41#define RC_R10 0x0400
42#define RC_R11 0x0800
43#define RC_XMM0 0x1000
44#define RC_XMM1 0x2000
45#define RC_XMM2 0x4000
46#define RC_XMM3 0x8000
47#define RC_XMM4 0x10000
48#define RC_XMM5 0x20000
49#define RC_XMM6 0x40000
50#define RC_XMM7 0x80000
51#define RC_IRET RC_RAX /* function return: integer register */
52#define RC_LRET RC_RDX /* function return: second integer register */
53#define RC_FRET RC_XMM0 /* function return: float register */
54#define RC_QRET RC_XMM1 /* function return: second float register */
55
56/* pretty names for the registers */
57enum {
58 TREG_RAX = 0,
59 TREG_RCX = 1,
60 TREG_RDX = 2,
61 TREG_RSP = 4,
62 TREG_RSI = 6,
63 TREG_RDI = 7,
64
65 TREG_R8 = 8,
66 TREG_R9 = 9,
67 TREG_R10 = 10,
68 TREG_R11 = 11,
69
70 TREG_XMM0 = 16,
71 TREG_XMM1 = 17,
72 TREG_XMM2 = 18,
73 TREG_XMM3 = 19,
74 TREG_XMM4 = 20,
75 TREG_XMM5 = 21,
76 TREG_XMM6 = 22,
77 TREG_XMM7 = 23,
78
79 TREG_ST0 = 24,
80
81 TREG_MEM = 0x20
82};
83
84#define REX_BASE(reg) (((reg) >> 3) & 1)
85#define REG_VALUE(reg) ((reg) & 7)
86
87/* return registers for function */
88#define REG_IRET TREG_RAX /* single word int return register */
89#define REG_LRET TREG_RDX /* second word return register (for long long) */
90#define REG_FRET TREG_XMM0 /* float return register */
91#define REG_QRET TREG_XMM1 /* second float return register */
92
93/* defined if function parameters must be evaluated in reverse order */
94#define INVERT_FUNC_PARAMS
95
96/* pointer size, in bytes */
97#define PTR_SIZE 8
98
99/* long double size and alignment, in bytes */
100#define LDOUBLE_SIZE 16
101#define LDOUBLE_ALIGN 16
102/* maximum alignment (for aligned attribute support) */
103#define MAX_ALIGN 16
104
105/******************************************************/
106#else /* ! TARGET_DEFS_ONLY */
107/******************************************************/
108#include "tcc.h"
109#include <assert.h>
110
111ST_DATA const int reg_classes[NB_REGS] = {
112 /* eax */ RC_INT | RC_RAX,
113 /* ecx */ RC_INT | RC_RCX,
114 /* edx */ RC_INT | RC_RDX,
115 0,
116 0,
117 0,
118 0,
119 0,
120 RC_R8,
121 RC_R9,
122 RC_R10,
123 RC_R11,
124 0,
125 0,
126 0,
127 0,
128 /* xmm0 */ RC_FLOAT | RC_XMM0,
129 /* xmm1 */ RC_FLOAT | RC_XMM1,
130 /* xmm2 */ RC_FLOAT | RC_XMM2,
131 /* xmm3 */ RC_FLOAT | RC_XMM3,
132 /* xmm4 */ RC_FLOAT | RC_XMM4,
133 /* xmm5 */ RC_FLOAT | RC_XMM5,
134 /* xmm6 an xmm7 are included so gv() can be used on them,
135 but they are not tagged with RC_FLOAT because they are
136 callee saved on Windows */
137 RC_XMM6,
138 RC_XMM7,
139 /* st0 */ RC_ST0
140};
141
142static unsigned long func_sub_sp_offset;
143static int func_ret_sub;
144
145/* XXX: make it faster ? */
146ST_FUNC void g(int c)
147{
148 int ind1;
149 if (nocode_wanted)
150 return;
151 ind1 = ind + 1;
152 if (ind1 > cur_text_section->data_allocated)
153 section_realloc(cur_text_section, ind1);
154 cur_text_section->data[ind] = c;
155 ind = ind1;
156}
157
158ST_FUNC void o(unsigned int c)
159{
160 while (c) {
161 g(c);
162 c = c >> 8;
163 }
164}
165
166ST_FUNC void gen_le16(int v)
167{
168 g(v);
169 g(v >> 8);
170}
171
172ST_FUNC void gen_le32(int c)
173{
174 g(c);
175 g(c >> 8);
176 g(c >> 16);
177 g(c >> 24);
178}
179
180ST_FUNC void gen_le64(int64_t c)
181{
182 g(c);
183 g(c >> 8);
184 g(c >> 16);
185 g(c >> 24);
186 g(c >> 32);
187 g(c >> 40);
188 g(c >> 48);
189 g(c >> 56);
190}
191
192static void orex(int ll, int r, int r2, int b)
193{
194 if ((r & VT_VALMASK) >= VT_CONST)
195 r = 0;
196 if ((r2 & VT_VALMASK) >= VT_CONST)
197 r2 = 0;
198 if (ll || REX_BASE(r) || REX_BASE(r2))
199 o(0x40 | REX_BASE(r) | (REX_BASE(r2) << 2) | (ll << 3));
200 o(b);
201}
202
203/* output a symbol and patch all calls to it */
204ST_FUNC void gsym_addr(int t, int a)
205{
206 while (t) {
207 unsigned char *ptr = cur_text_section->data + t;
208 uint32_t n = read32le(ptr); /* next value */
209 write32le(ptr, a - t - 4);
210 t = n;
211 }
212}
213
214void gsym(int t)
215{
216 gsym_addr(t, ind);
217}
218
219
220static int is64_type(int t)
221{
222 return ((t & VT_BTYPE) == VT_PTR ||
223 (t & VT_BTYPE) == VT_FUNC ||
224 (t & VT_BTYPE) == VT_LLONG);
225}
226
227/* instruction + 4 bytes data. Return the address of the data */
228static int oad(int c, int s)
229{
230 int t;
231 if (nocode_wanted)
232 return s;
233 o(c);
234 t = ind;
235 gen_le32(s);
236 return t;
237}
238
239/* generate jmp to a label */
240#define gjmp2(instr,lbl) oad(instr,lbl)
241
242ST_FUNC void gen_addr32(int r, Sym *sym, int c)
243{
244 if (r & VT_SYM)
245 greloca(cur_text_section, sym, ind, R_X86_64_32S, c), c=0;
246 gen_le32(c);
247}
248
249/* output constant with relocation if 'r & VT_SYM' is true */
250ST_FUNC void gen_addr64(int r, Sym *sym, int64_t c)
251{
252 if (r & VT_SYM)
253 greloca(cur_text_section, sym, ind, R_X86_64_64, c), c=0;
254 gen_le64(c);
255}
256
257/* output constant with relocation if 'r & VT_SYM' is true */
258ST_FUNC void gen_addrpc32(int r, Sym *sym, int c)
259{
260 if (r & VT_SYM)
261 greloca(cur_text_section, sym, ind, R_X86_64_PC32, c-4), c=4;
262 gen_le32(c-4);
263}
264
265/* output got address with relocation */
266static void gen_gotpcrel(int r, Sym *sym, int c)
267{
268#ifdef TCC_TARGET_PE
269 tcc_error("internal error: no GOT on PE: %s %x %x | %02x %02x %02x\n",
270 get_tok_str(sym->v, NULL), c, r,
271 cur_text_section->data[ind-3],
272 cur_text_section->data[ind-2],
273 cur_text_section->data[ind-1]
274 );
275#endif
276 greloca(cur_text_section, sym, ind, R_X86_64_GOTPCREL, -4);
277 gen_le32(0);
278 if (c) {
279 /* we use add c, %xxx for displacement */
280 orex(1, r, 0, 0x81);
281 o(0xc0 + REG_VALUE(r));
282 gen_le32(c);
283 }
284}
285
286static void gen_modrm_impl(int op_reg, int r, Sym *sym, int c, int is_got)
287{
288 op_reg = REG_VALUE(op_reg) << 3;
289 if ((r & VT_VALMASK) == VT_CONST) {
290 /* constant memory reference */
291 if (!(r & VT_SYM)) {
292 /* Absolute memory reference */
293 o(0x04 | op_reg); /* [sib] | destreg */
294 oad(0x25, c); /* disp32 */
295 } else {
296 o(0x05 | op_reg); /* (%rip)+disp32 | destreg */
297 if (is_got) {
298 gen_gotpcrel(r, sym, c);
299 } else {
300 gen_addrpc32(r, sym, c);
301 }
302 }
303 } else if ((r & VT_VALMASK) == VT_LOCAL) {
304 /* currently, we use only ebp as base */
305 if (c == (char)c) {
306 /* short reference */
307 o(0x45 | op_reg);
308 g(c);
309 } else {
310 oad(0x85 | op_reg, c);
311 }
312 } else if ((r & VT_VALMASK) >= TREG_MEM) {
313 if (c) {
314 g(0x80 | op_reg | REG_VALUE(r));
315 gen_le32(c);
316 } else {
317 g(0x00 | op_reg | REG_VALUE(r));
318 }
319 } else {
320 g(0x00 | op_reg | REG_VALUE(r));
321 }
322}
323
324/* generate a modrm reference. 'op_reg' contains the additional 3
325 opcode bits */
326static void gen_modrm(int op_reg, int r, Sym *sym, int c)
327{
328 gen_modrm_impl(op_reg, r, sym, c, 0);
329}
330
331/* generate a modrm reference. 'op_reg' contains the additional 3
332 opcode bits */
333static void gen_modrm64(int opcode, int op_reg, int r, Sym *sym, int c)
334{
335 int is_got;
336 is_got = (op_reg & TREG_MEM) && !(sym->type.t & VT_STATIC);
337 orex(1, r, op_reg, opcode);
338 gen_modrm_impl(op_reg, r, sym, c, is_got);
339}
340
341
342/* load 'r' from value 'sv' */
343void load(int r, SValue *sv)
344{
345 int v, t, ft, fc, fr;
346 SValue v1;
347
348#ifdef TCC_TARGET_PE
349 SValue v2;
350 sv = pe_getimport(sv, &v2);
351#endif
352
353 fr = sv->r;
354 ft = sv->type.t & ~VT_DEFSIGN;
355 fc = sv->c.i;
356 if (fc != sv->c.i && (fr & VT_SYM))
357 tcc_error("64 bit addend in load");
358
359 ft &= ~(VT_VOLATILE | VT_CONSTANT);
360
361#ifndef TCC_TARGET_PE
362 /* we use indirect access via got */
363 if ((fr & VT_VALMASK) == VT_CONST && (fr & VT_SYM) &&
364 (fr & VT_LVAL) && !(sv->sym->type.t & VT_STATIC)) {
365 /* use the result register as a temporal register */
366 int tr = r | TREG_MEM;
367 if (is_float(ft)) {
368 /* we cannot use float registers as a temporal register */
369 tr = get_reg(RC_INT) | TREG_MEM;
370 }
371 gen_modrm64(0x8b, tr, fr, sv->sym, 0);
372
373 /* load from the temporal register */
374 fr = tr | VT_LVAL;
375 }
376#endif
377
378 v = fr & VT_VALMASK;
379 if (fr & VT_LVAL) {
380 int b, ll;
381 if (v == VT_LLOCAL) {
382 v1.type.t = VT_PTR;
383 v1.r = VT_LOCAL | VT_LVAL;
384 v1.c.i = fc;
385 fr = r;
386 if (!(reg_classes[fr] & (RC_INT|RC_R11)))
387 fr = get_reg(RC_INT);
388 load(fr, &v1);
389 }
390 if (fc != sv->c.i) {
391 /* If the addends doesn't fit into a 32bit signed
392 we must use a 64bit move. We've checked above
393 that this doesn't have a sym associated. */
394 v1.type.t = VT_LLONG;
395 v1.r = VT_CONST;
396 v1.c.i = sv->c.i;
397 fr = r;
398 if (!(reg_classes[fr] & (RC_INT|RC_R11)))
399 fr = get_reg(RC_INT);
400 load(fr, &v1);
401 fc = 0;
402 }
403 ll = 0;
404 /* Like GCC we can load from small enough properly sized
405 structs and unions as well.
406 XXX maybe move to generic operand handling, but should
407 occur only with asm, so tccasm.c might also be a better place */
408 if ((ft & VT_BTYPE) == VT_STRUCT) {
409 int align;
410 switch (type_size(&sv->type, &align)) {
411 case 1: ft = VT_BYTE; break;
412 case 2: ft = VT_SHORT; break;
413 case 4: ft = VT_INT; break;
414 case 8: ft = VT_LLONG; break;
415 default:
416 tcc_error("invalid aggregate type for register load");
417 break;
418 }
419 }
420 if ((ft & VT_BTYPE) == VT_FLOAT) {
421 b = 0x6e0f66;
422 r = REG_VALUE(r); /* movd */
423 } else if ((ft & VT_BTYPE) == VT_DOUBLE) {
424 b = 0x7e0ff3; /* movq */
425 r = REG_VALUE(r);
426 } else if ((ft & VT_BTYPE) == VT_LDOUBLE) {
427 b = 0xdb, r = 5; /* fldt */
428 } else if ((ft & VT_TYPE) == VT_BYTE || (ft & VT_TYPE) == VT_BOOL) {
429 b = 0xbe0f; /* movsbl */
430 } else if ((ft & VT_TYPE) == (VT_BYTE | VT_UNSIGNED)) {
431 b = 0xb60f; /* movzbl */
432 } else if ((ft & VT_TYPE) == VT_SHORT) {
433 b = 0xbf0f; /* movswl */
434 } else if ((ft & VT_TYPE) == (VT_SHORT | VT_UNSIGNED)) {
435 b = 0xb70f; /* movzwl */
436 } else {
437 assert(((ft & VT_BTYPE) == VT_INT)
438 || ((ft & VT_BTYPE) == VT_LLONG)
439 || ((ft & VT_BTYPE) == VT_PTR)
440 || ((ft & VT_BTYPE) == VT_FUNC)
441 );
442 ll = is64_type(ft);
443 b = 0x8b;
444 }
445 if (ll) {
446 gen_modrm64(b, r, fr, sv->sym, fc);
447 } else {
448 orex(ll, fr, r, b);
449 gen_modrm(r, fr, sv->sym, fc);
450 }
451 } else {
452 if (v == VT_CONST) {
453 if (fr & VT_SYM) {
454#ifdef TCC_TARGET_PE
455 orex(1,0,r,0x8d);
456 o(0x05 + REG_VALUE(r) * 8); /* lea xx(%rip), r */
457 gen_addrpc32(fr, sv->sym, fc);
458#else
459 if (sv->sym->type.t & VT_STATIC) {
460 orex(1,0,r,0x8d);
461 o(0x05 + REG_VALUE(r) * 8); /* lea xx(%rip), r */
462 gen_addrpc32(fr, sv->sym, fc);
463 } else {
464 orex(1,0,r,0x8b);
465 o(0x05 + REG_VALUE(r) * 8); /* mov xx(%rip), r */
466 gen_gotpcrel(r, sv->sym, fc);
467 }
468#endif
469 } else if (is64_type(ft)) {
470 orex(1,r,0, 0xb8 + REG_VALUE(r)); /* mov $xx, r */
471 gen_le64(sv->c.i);
472 } else {
473 orex(0,r,0, 0xb8 + REG_VALUE(r)); /* mov $xx, r */
474 gen_le32(fc);
475 }
476 } else if (v == VT_LOCAL) {
477 orex(1,0,r,0x8d); /* lea xxx(%ebp), r */
478 gen_modrm(r, VT_LOCAL, sv->sym, fc);
479 } else if (v == VT_CMP) {
480 orex(0,r,0,0);
481 if ((fc & ~0x100) != TOK_NE)
482 oad(0xb8 + REG_VALUE(r), 0); /* mov $0, r */
483 else
484 oad(0xb8 + REG_VALUE(r), 1); /* mov $1, r */
485 if (fc & 0x100)
486 {
487 /* This was a float compare. If the parity bit is
488 set the result was unordered, meaning false for everything
489 except TOK_NE, and true for TOK_NE. */
490 fc &= ~0x100;
491 o(0x037a + (REX_BASE(r) << 8));
492 }
493 orex(0,r,0, 0x0f); /* setxx %br */
494 o(fc);
495 o(0xc0 + REG_VALUE(r));
496 } else if (v == VT_JMP || v == VT_JMPI) {
497 t = v & 1;
498 orex(0,r,0,0);
499 oad(0xb8 + REG_VALUE(r), t); /* mov $1, r */
500 o(0x05eb + (REX_BASE(r) << 8)); /* jmp after */
501 gsym(fc);
502 orex(0,r,0,0);
503 oad(0xb8 + REG_VALUE(r), t ^ 1); /* mov $0, r */
504 } else if (v != r) {
505 if ((r >= TREG_XMM0) && (r <= TREG_XMM7)) {
506 if (v == TREG_ST0) {
507 /* gen_cvt_ftof(VT_DOUBLE); */
508 o(0xf0245cdd); /* fstpl -0x10(%rsp) */
509 /* movsd -0x10(%rsp),%xmmN */
510 o(0x100ff2);
511 o(0x44 + REG_VALUE(r)*8); /* %xmmN */
512 o(0xf024);
513 } else {
514 assert((v >= TREG_XMM0) && (v <= TREG_XMM7));
515 if ((ft & VT_BTYPE) == VT_FLOAT) {
516 o(0x100ff3);
517 } else {
518 assert((ft & VT_BTYPE) == VT_DOUBLE);
519 o(0x100ff2);
520 }
521 o(0xc0 + REG_VALUE(v) + REG_VALUE(r)*8);
522 }
523 } else if (r == TREG_ST0) {
524 assert((v >= TREG_XMM0) && (v <= TREG_XMM7));
525 /* gen_cvt_ftof(VT_LDOUBLE); */
526 /* movsd %xmmN,-0x10(%rsp) */
527 o(0x110ff2);
528 o(0x44 + REG_VALUE(r)*8); /* %xmmN */
529 o(0xf024);
530 o(0xf02444dd); /* fldl -0x10(%rsp) */
531 } else {
532 orex(1,r,v, 0x89);
533 o(0xc0 + REG_VALUE(r) + REG_VALUE(v) * 8); /* mov v, r */
534 }
535 }
536 }
537}
538
539/* store register 'r' in lvalue 'v' */
540void store(int r, SValue *v)
541{
542 int fr, bt, ft, fc;
543 int op64 = 0;
544 /* store the REX prefix in this variable when PIC is enabled */
545 int pic = 0;
546
547#ifdef TCC_TARGET_PE
548 SValue v2;
549 v = pe_getimport(v, &v2);
550#endif
551
552 fr = v->r & VT_VALMASK;
553 ft = v->type.t;
554 fc = v->c.i;
555 if (fc != v->c.i && (fr & VT_SYM))
556 tcc_error("64 bit addend in store");
557 ft &= ~(VT_VOLATILE | VT_CONSTANT);
558 bt = ft & VT_BTYPE;
559
560#ifndef TCC_TARGET_PE
561 /* we need to access the variable via got */
562 if (fr == VT_CONST && (v->r & VT_SYM)) {
563 /* mov xx(%rip), %r11 */
564 o(0x1d8b4c);
565 gen_gotpcrel(TREG_R11, v->sym, v->c.i);
566 pic = is64_type(bt) ? 0x49 : 0x41;
567 }
568#endif
569
570 /* XXX: incorrect if float reg to reg */
571 if (bt == VT_FLOAT) {
572 o(0x66);
573 o(pic);
574 o(0x7e0f); /* movd */
575 r = REG_VALUE(r);
576 } else if (bt == VT_DOUBLE) {
577 o(0x66);
578 o(pic);
579 o(0xd60f); /* movq */
580 r = REG_VALUE(r);
581 } else if (bt == VT_LDOUBLE) {
582 o(0xc0d9); /* fld %st(0) */
583 o(pic);
584 o(0xdb); /* fstpt */
585 r = 7;
586 } else {
587 if (bt == VT_SHORT)
588 o(0x66);
589 o(pic);
590 if (bt == VT_BYTE || bt == VT_BOOL)
591 orex(0, 0, r, 0x88);
592 else if (is64_type(bt))
593 op64 = 0x89;
594 else
595 orex(0, 0, r, 0x89);
596 }
597 if (pic) {
598 /* xxx r, (%r11) where xxx is mov, movq, fld, or etc */
599 if (op64)
600 o(op64);
601 o(3 + (r << 3));
602 } else if (op64) {
603 if (fr == VT_CONST || fr == VT_LOCAL || (v->r & VT_LVAL)) {
604 gen_modrm64(op64, r, v->r, v->sym, fc);
605 } else if (fr != r) {
606 /* XXX: don't we really come here? */
607 abort();
608 o(0xc0 + fr + r * 8); /* mov r, fr */
609 }
610 } else {
611 if (fr == VT_CONST || fr == VT_LOCAL || (v->r & VT_LVAL)) {
612 gen_modrm(r, v->r, v->sym, fc);
613 } else if (fr != r) {
614 /* XXX: don't we really come here? */
615 abort();
616 o(0xc0 + fr + r * 8); /* mov r, fr */
617 }
618 }
619}
620
621/* 'is_jmp' is '1' if it is a jump */
622static void gcall_or_jmp(int is_jmp)
623{
624 int r;
625 if ((vtop->r & (VT_VALMASK | VT_LVAL)) == VT_CONST &&
626 ((vtop->r & VT_SYM) || (vtop->c.i-4) == (int)(vtop->c.i-4))) {
627 /* constant case */
628 if (vtop->r & VT_SYM) {
629 /* relocation case */
630#ifdef TCC_TARGET_PE
631 greloca(cur_text_section, vtop->sym, ind + 1, R_X86_64_PC32, (int)(vtop->c.i-4));
632#else
633 greloca(cur_text_section, vtop->sym, ind + 1, R_X86_64_PLT32, (int)(vtop->c.i-4));
634#endif
635 } else {
636 /* put an empty PC32 relocation */
637 put_elf_reloca(symtab_section, cur_text_section,
638 ind + 1, R_X86_64_PC32, 0, (int)(vtop->c.i-4));
639 }
640 oad(0xe8 + is_jmp, 0); /* call/jmp im */
641 } else {
642 /* otherwise, indirect call */
643 r = TREG_R11;
644 load(r, vtop);
645 o(0x41); /* REX */
646 o(0xff); /* call/jmp *r */
647 o(0xd0 + REG_VALUE(r) + (is_jmp << 4));
648 }
649}
650
651#if defined(CONFIG_TCC_BCHECK)
652#ifndef TCC_TARGET_PE
653static addr_t func_bound_offset;
654static unsigned long func_bound_ind;
655#endif
656
657static void gen_static_call(int v)
658{
659 Sym *sym = external_global_sym(v, &func_old_type, 0);
660 oad(0xe8, 0);
661 greloca(cur_text_section, sym, ind-4, R_X86_64_PC32, -4);
662}
663
664/* generate a bounded pointer addition */
665ST_FUNC void gen_bounded_ptr_add(void)
666{
667 /* save all temporary registers */
668 save_regs(0);
669
670 /* prepare fast x86_64 function call */
671 gv(RC_RAX);
672 o(0xc68948); // mov %rax,%rsi ## second arg in %rsi, this must be size
673 vtop--;
674
675 gv(RC_RAX);
676 o(0xc78948); // mov %rax,%rdi ## first arg in %rdi, this must be ptr
677 vtop--;
678
679 /* do a fast function call */
680 gen_static_call(TOK___bound_ptr_add);
681
682 /* returned pointer is in rax */
683 vtop++;
684 vtop->r = TREG_RAX | VT_BOUNDED;
685
686
687 /* relocation offset of the bounding function call point */
688 vtop->c.i = (cur_text_section->reloc->data_offset - sizeof(ElfW(Rela)));
689}
690
691/* patch pointer addition in vtop so that pointer dereferencing is
692 also tested */
693ST_FUNC void gen_bounded_ptr_deref(void)
694{
695 addr_t func;
696 int size, align;
697 ElfW(Rela) *rel;
698 Sym *sym;
699
700 size = 0;
701 /* XXX: put that code in generic part of tcc */
702 if (!is_float(vtop->type.t)) {
703 if (vtop->r & VT_LVAL_BYTE)
704 size = 1;
705 else if (vtop->r & VT_LVAL_SHORT)
706 size = 2;
707 }
708 if (!size)
709 size = type_size(&vtop->type, &align);
710 switch(size) {
711 case 1: func = TOK___bound_ptr_indir1; break;
712 case 2: func = TOK___bound_ptr_indir2; break;
713 case 4: func = TOK___bound_ptr_indir4; break;
714 case 8: func = TOK___bound_ptr_indir8; break;
715 case 12: func = TOK___bound_ptr_indir12; break;
716 case 16: func = TOK___bound_ptr_indir16; break;
717 default:
718 tcc_error("unhandled size when dereferencing bounded pointer");
719 func = 0;
720 break;
721 }
722
723 sym = external_global_sym(func, &func_old_type, 0);
724 if (!sym->c)
725 put_extern_sym(sym, NULL, 0, 0);
726
727 /* patch relocation */
728 /* XXX: find a better solution ? */
729
730 rel = (ElfW(Rela) *)(cur_text_section->reloc->data + vtop->c.i);
731 rel->r_info = ELF64_R_INFO(sym->c, ELF64_R_TYPE(rel->r_info));
732}
733#endif
734
735#ifdef TCC_TARGET_PE
736
737#define REGN 4
738static const uint8_t arg_regs[REGN] = {
739 TREG_RCX, TREG_RDX, TREG_R8, TREG_R9
740};
741
742/* Prepare arguments in R10 and R11 rather than RCX and RDX
743 because gv() will not ever use these */
744static int arg_prepare_reg(int idx) {
745 if (idx == 0 || idx == 1)
746 /* idx=0: r10, idx=1: r11 */
747 return idx + 10;
748 else
749 return arg_regs[idx];
750}
751
752static int func_scratch, func_alloca;
753
754/* Generate function call. The function address is pushed first, then
755 all the parameters in call order. This functions pops all the
756 parameters and the function address. */
757
758static void gen_offs_sp(int b, int r, int d)
759{
760 orex(1,0,r & 0x100 ? 0 : r, b);
761 if (d == (char)d) {
762 o(0x2444 | (REG_VALUE(r) << 3));
763 g(d);
764 } else {
765 o(0x2484 | (REG_VALUE(r) << 3));
766 gen_le32(d);
767 }
768}
769
770static int using_regs(int size)
771{
772 return !(size > 8 || (size & (size - 1)));
773}
774
775/* Return the number of registers needed to return the struct, or 0 if
776 returning via struct pointer. */
777ST_FUNC int gfunc_sret(CType *vt, int variadic, CType *ret, int *ret_align, int *regsize)
778{
779 int size, align;
780 *ret_align = 1; // Never have to re-align return values for x86-64
781 *regsize = 8;
782 size = type_size(vt, &align);
783 if (!using_regs(size))
784 return 0;
785 if (size == 8)
786 ret->t = VT_LLONG;
787 else if (size == 4)
788 ret->t = VT_INT;
789 else if (size == 2)
790 ret->t = VT_SHORT;
791 else
792 ret->t = VT_BYTE;
793 ret->ref = NULL;
794 return 1;
795}
796
797static int is_sse_float(int t) {
798 int bt;
799 bt = t & VT_BTYPE;
800 return bt == VT_DOUBLE || bt == VT_FLOAT;
801}
802
803static int gfunc_arg_size(CType *type) {
804 int align;
805 if (type->t & (VT_ARRAY|VT_BITFIELD))
806 return 8;
807 return type_size(type, &align);
808}
809
810void gfunc_call(int nb_args)
811{
812 int size, r, args_size, i, d, bt, struct_size;
813 int arg;
814
815 args_size = (nb_args < REGN ? REGN : nb_args) * PTR_SIZE;
816 arg = nb_args;
817
818 /* for struct arguments, we need to call memcpy and the function
819 call breaks register passing arguments we are preparing.
820 So, we process arguments which will be passed by stack first. */
821 struct_size = args_size;
822 for(i = 0; i < nb_args; i++) {
823 SValue *sv;
824
825 --arg;
826 sv = &vtop[-i];
827 bt = (sv->type.t & VT_BTYPE);
828 size = gfunc_arg_size(&sv->type);
829
830 if (using_regs(size))
831 continue; /* arguments smaller than 8 bytes passed in registers or on stack */
832
833 if (bt == VT_STRUCT) {
834 /* align to stack align size */
835 size = (size + 15) & ~15;
836 /* generate structure store */
837 r = get_reg(RC_INT);
838 gen_offs_sp(0x8d, r, struct_size);
839 struct_size += size;
840
841 /* generate memcpy call */
842 vset(&sv->type, r | VT_LVAL, 0);
843 vpushv(sv);
844 vstore();
845 --vtop;
846 } else if (bt == VT_LDOUBLE) {
847 gv(RC_ST0);
848 gen_offs_sp(0xdb, 0x107, struct_size);
849 struct_size += 16;
850 }
851 }
852
853 if (func_scratch < struct_size)
854 func_scratch = struct_size;
855
856 arg = nb_args;
857 struct_size = args_size;
858
859 for(i = 0; i < nb_args; i++) {
860 --arg;
861 bt = (vtop->type.t & VT_BTYPE);
862
863 size = gfunc_arg_size(&vtop->type);
864 if (!using_regs(size)) {
865 /* align to stack align size */
866 size = (size + 15) & ~15;
867 if (arg >= REGN) {
868 d = get_reg(RC_INT);
869 gen_offs_sp(0x8d, d, struct_size);
870 gen_offs_sp(0x89, d, arg*8);
871 } else {
872 d = arg_prepare_reg(arg);
873 gen_offs_sp(0x8d, d, struct_size);
874 }
875 struct_size += size;
876 } else {
877 if (is_sse_float(vtop->type.t)) {
878 if (tcc_state->nosse)
879 tcc_error("SSE disabled");
880 gv(RC_XMM0); /* only use one float register */
881 if (arg >= REGN) {
882 /* movq %xmm0, j*8(%rsp) */
883 gen_offs_sp(0xd60f66, 0x100, arg*8);
884 } else {
885 /* movaps %xmm0, %xmmN */
886 o(0x280f);
887 o(0xc0 + (arg << 3));
888 d = arg_prepare_reg(arg);
889 /* mov %xmm0, %rxx */
890 o(0x66);
891 orex(1,d,0, 0x7e0f);
892 o(0xc0 + REG_VALUE(d));
893 }
894 } else {
895 if (bt == VT_STRUCT) {
896 vtop->type.ref = NULL;
897 vtop->type.t = size > 4 ? VT_LLONG : size > 2 ? VT_INT
898 : size > 1 ? VT_SHORT : VT_BYTE;
899 }
900
901 r = gv(RC_INT);
902 if (arg >= REGN) {
903 gen_offs_sp(0x89, r, arg*8);
904 } else {
905 d = arg_prepare_reg(arg);
906 orex(1,d,r,0x89); /* mov */
907 o(0xc0 + REG_VALUE(r) * 8 + REG_VALUE(d));
908 }
909 }
910 }
911 vtop--;
912 }
913 save_regs(0);
914
915 /* Copy R10 and R11 into RCX and RDX, respectively */
916 if (nb_args > 0) {
917 o(0xd1894c); /* mov %r10, %rcx */
918 if (nb_args > 1) {
919 o(0xda894c); /* mov %r11, %rdx */
920 }
921 }
922
923 gcall_or_jmp(0);
924
925 if ((vtop->r & VT_SYM) && vtop->sym->v == TOK_alloca) {
926 /* need to add the "func_scratch" area after alloca */
927 o(0x0548), gen_le32(func_alloca), func_alloca = ind - 4;
928 }
929
930 /* other compilers don't clear the upper bits when returning char/short */
931 bt = vtop->type.ref->type.t & (VT_BTYPE | VT_UNSIGNED);
932 if (bt == (VT_BYTE | VT_UNSIGNED))
933 o(0xc0b60f); /* movzbl %al, %eax */
934 else if (bt == VT_BYTE)
935 o(0xc0be0f); /* movsbl %al, %eax */
936 else if (bt == VT_SHORT)
937 o(0x98); /* cwtl */
938 else if (bt == (VT_SHORT | VT_UNSIGNED))
939 o(0xc0b70f); /* movzbl %al, %eax */
940#if 0 /* handled in gen_cast() */
941 else if (bt == VT_INT)
942 o(0x9848); /* cltq */
943 else if (bt == (VT_INT | VT_UNSIGNED))
944 o(0xc089); /* mov %eax,%eax */
945#endif
946 vtop--;
947}
948
949
950#define FUNC_PROLOG_SIZE 11
951
952/* generate function prolog of type 't' */
953void gfunc_prolog(CType *func_type)
954{
955 int addr, reg_param_index, bt, size;
956 Sym *sym;
957 CType *type;
958
959 func_ret_sub = 0;
960 func_scratch = 0;
961 func_alloca = 0;
962 loc = 0;
963
964 addr = PTR_SIZE * 2;
965 ind += FUNC_PROLOG_SIZE;
966 func_sub_sp_offset = ind;
967 reg_param_index = 0;
968
969 sym = func_type->ref;
970
971 /* if the function returns a structure, then add an
972 implicit pointer parameter */
973 func_vt = sym->type;
974 func_var = (sym->f.func_type == FUNC_ELLIPSIS);
975 size = gfunc_arg_size(&func_vt);
976 if (!using_regs(size)) {
977 gen_modrm64(0x89, arg_regs[reg_param_index], VT_LOCAL, NULL, addr);
978 func_vc = addr;
979 reg_param_index++;
980 addr += 8;
981 }
982
983 /* define parameters */
984 while ((sym = sym->next) != NULL) {
985 type = &sym->type;
986 bt = type->t & VT_BTYPE;
987 size = gfunc_arg_size(type);
988 if (!using_regs(size)) {
989 if (reg_param_index < REGN) {
990 gen_modrm64(0x89, arg_regs[reg_param_index], VT_LOCAL, NULL, addr);
991 }
992 sym_push(sym->v & ~SYM_FIELD, type, VT_LLOCAL | VT_LVAL, addr);
993 } else {
994 if (reg_param_index < REGN) {
995 /* save arguments passed by register */
996 if ((bt == VT_FLOAT) || (bt == VT_DOUBLE)) {
997 if (tcc_state->nosse)
998 tcc_error("SSE disabled");
999 o(0xd60f66); /* movq */
1000 gen_modrm(reg_param_index, VT_LOCAL, NULL, addr);
1001 } else {
1002 gen_modrm64(0x89, arg_regs[reg_param_index], VT_LOCAL, NULL, addr);
1003 }
1004 }
1005 sym_push(sym->v & ~SYM_FIELD, type, VT_LOCAL | VT_LVAL, addr);
1006 }
1007 addr += 8;
1008 reg_param_index++;
1009 }
1010
1011 while (reg_param_index < REGN) {
1012 if (func_type->ref->f.func_type == FUNC_ELLIPSIS) {
1013 gen_modrm64(0x89, arg_regs[reg_param_index], VT_LOCAL, NULL, addr);
1014 addr += 8;
1015 }
1016 reg_param_index++;
1017 }
1018}
1019
1020/* generate function epilog */
1021void gfunc_epilog(void)
1022{
1023 int v, saved_ind;
1024
1025 o(0xc9); /* leave */
1026 if (func_ret_sub == 0) {
1027 o(0xc3); /* ret */
1028 } else {
1029 o(0xc2); /* ret n */
1030 g(func_ret_sub);
1031 g(func_ret_sub >> 8);
1032 }
1033
1034 saved_ind = ind;
1035 ind = func_sub_sp_offset - FUNC_PROLOG_SIZE;
1036 /* align local size to word & save local variables */
1037 func_scratch = (func_scratch + 15) & -16;
1038 v = (func_scratch + -loc + 15) & -16;
1039
1040 if (v >= 4096) {
1041 Sym *sym = external_global_sym(TOK___chkstk, &func_old_type, 0);
1042 oad(0xb8, v); /* mov stacksize, %eax */
1043 oad(0xe8, 0); /* call __chkstk, (does the stackframe too) */
1044 greloca(cur_text_section, sym, ind-4, R_X86_64_PC32, -4);
1045 o(0x90); /* fill for FUNC_PROLOG_SIZE = 11 bytes */
1046 } else {
1047 o(0xe5894855); /* push %rbp, mov %rsp, %rbp */
1048 o(0xec8148); /* sub rsp, stacksize */
1049 gen_le32(v);
1050 }
1051
1052 /* add the "func_scratch" area after each alloca seen */
1053 while (func_alloca) {
1054 unsigned char *ptr = cur_text_section->data + func_alloca;
1055 func_alloca = read32le(ptr);
1056 write32le(ptr, func_scratch);
1057 }
1058
1059 cur_text_section->data_offset = saved_ind;
1060 pe_add_unwind_data(ind, saved_ind, v);
1061 ind = cur_text_section->data_offset;
1062}
1063
1064#else
1065
1066static void gadd_sp(int val)
1067{
1068 if (val == (char)val) {
1069 o(0xc48348);
1070 g(val);
1071 } else {
1072 oad(0xc48148, val); /* add $xxx, %rsp */
1073 }
1074}
1075
1076typedef enum X86_64_Mode {
1077 x86_64_mode_none,
1078 x86_64_mode_memory,
1079 x86_64_mode_integer,
1080 x86_64_mode_sse,
1081 x86_64_mode_x87
1082} X86_64_Mode;
1083
1084static X86_64_Mode classify_x86_64_merge(X86_64_Mode a, X86_64_Mode b)
1085{
1086 if (a == b)
1087 return a;
1088 else if (a == x86_64_mode_none)
1089 return b;
1090 else if (b == x86_64_mode_none)
1091 return a;
1092 else if ((a == x86_64_mode_memory) || (b == x86_64_mode_memory))
1093 return x86_64_mode_memory;
1094 else if ((a == x86_64_mode_integer) || (b == x86_64_mode_integer))
1095 return x86_64_mode_integer;
1096 else if ((a == x86_64_mode_x87) || (b == x86_64_mode_x87))
1097 return x86_64_mode_memory;
1098 else
1099 return x86_64_mode_sse;
1100}
1101
1102static X86_64_Mode classify_x86_64_inner(CType *ty)
1103{
1104 X86_64_Mode mode;
1105 Sym *f;
1106
1107 switch (ty->t & VT_BTYPE) {
1108 case VT_VOID: return x86_64_mode_none;
1109
1110 case VT_INT:
1111 case VT_BYTE:
1112 case VT_SHORT:
1113 case VT_LLONG:
1114 case VT_BOOL:
1115 case VT_PTR:
1116 case VT_FUNC:
1117 return x86_64_mode_integer;
1118
1119 case VT_FLOAT:
1120 case VT_DOUBLE: return x86_64_mode_sse;
1121
1122 case VT_LDOUBLE: return x86_64_mode_x87;
1123
1124 case VT_STRUCT:
1125 f = ty->ref;
1126
1127 mode = x86_64_mode_none;
1128 for (f = f->next; f; f = f->next)
1129 mode = classify_x86_64_merge(mode, classify_x86_64_inner(&f->type));
1130
1131 return mode;
1132 }
1133 assert(0);
1134 return 0;
1135}
1136
1137static X86_64_Mode classify_x86_64_arg(CType *ty, CType *ret, int *psize, int *palign, int *reg_count)
1138{
1139 X86_64_Mode mode;
1140 int size, align, ret_t = 0;
1141
1142 if (ty->t & (VT_BITFIELD|VT_ARRAY)) {
1143 *psize = 8;
1144 *palign = 8;
1145 *reg_count = 1;
1146 ret_t = ty->t;
1147 mode = x86_64_mode_integer;
1148 } else {
1149 size = type_size(ty, &align);
1150 *psize = (size + 7) & ~7;
1151 *palign = (align + 7) & ~7;
1152
1153 if (size > 16) {
1154 mode = x86_64_mode_memory;
1155 } else {
1156 mode = classify_x86_64_inner(ty);
1157 switch (mode) {
1158 case x86_64_mode_integer:
1159 if (size > 8) {
1160 *reg_count = 2;
1161 ret_t = VT_QLONG;
1162 } else {
1163 *reg_count = 1;
1164 ret_t = (size > 4) ? VT_LLONG : VT_INT;
1165 }
1166 break;
1167
1168 case x86_64_mode_x87:
1169 *reg_count = 1;
1170 ret_t = VT_LDOUBLE;
1171 break;
1172
1173 case x86_64_mode_sse:
1174 if (size > 8) {
1175 *reg_count = 2;
1176 ret_t = VT_QFLOAT;
1177 } else {
1178 *reg_count = 1;
1179 ret_t = (size > 4) ? VT_DOUBLE : VT_FLOAT;
1180 }
1181 break;
1182 default: break; /* nothing to be done for x86_64_mode_memory and x86_64_mode_none*/
1183 }
1184 }
1185 }
1186
1187 if (ret) {
1188 ret->ref = NULL;
1189 ret->t = ret_t;
1190 }
1191
1192 return mode;
1193}
1194
1195ST_FUNC int classify_x86_64_va_arg(CType *ty)
1196{
1197 /* This definition must be synced with stdarg.h */
1198 enum __va_arg_type {
1199 __va_gen_reg, __va_float_reg, __va_stack
1200 };
1201 int size, align, reg_count;
1202 X86_64_Mode mode = classify_x86_64_arg(ty, NULL, &size, &align, &reg_count);
1203 switch (mode) {
1204 default: return __va_stack;
1205 case x86_64_mode_integer: return __va_gen_reg;
1206 case x86_64_mode_sse: return __va_float_reg;
1207 }
1208}
1209
1210/* Return the number of registers needed to return the struct, or 0 if
1211 returning via struct pointer. */
1212ST_FUNC int gfunc_sret(CType *vt, int variadic, CType *ret, int *ret_align, int *regsize)
1213{
1214 int size, align, reg_count;
1215 *ret_align = 1; // Never have to re-align return values for x86-64
1216 *regsize = 8;
1217 return (classify_x86_64_arg(vt, ret, &size, &align, &reg_count) != x86_64_mode_memory);
1218}
1219
1220#define REGN 6
1221static const uint8_t arg_regs[REGN] = {
1222 TREG_RDI, TREG_RSI, TREG_RDX, TREG_RCX, TREG_R8, TREG_R9
1223};
1224
1225static int arg_prepare_reg(int idx) {
1226 if (idx == 2 || idx == 3)
1227 /* idx=2: r10, idx=3: r11 */
1228 return idx + 8;
1229 else
1230 return arg_regs[idx];
1231}
1232
1233/* Generate function call. The function address is pushed first, then
1234 all the parameters in call order. This functions pops all the
1235 parameters and the function address. */
1236void gfunc_call(int nb_args)
1237{
1238 X86_64_Mode mode;
1239 CType type;
1240 int size, align, r, args_size, stack_adjust, i, reg_count;
1241 int nb_reg_args = 0;
1242 int nb_sse_args = 0;
1243 int sse_reg, gen_reg;
1244 char _onstack[nb_args], *onstack = _onstack;
1245
1246 /* calculate the number of integer/float register arguments, remember
1247 arguments to be passed via stack (in onstack[]), and also remember
1248 if we have to align the stack pointer to 16 (onstack[i] == 2). Needs
1249 to be done in a left-to-right pass over arguments. */
1250 stack_adjust = 0;
1251 for(i = nb_args - 1; i >= 0; i--) {
1252 mode = classify_x86_64_arg(&vtop[-i].type, NULL, &size, &align, &reg_count);
1253 if (mode == x86_64_mode_sse && nb_sse_args + reg_count <= 8) {
1254 nb_sse_args += reg_count;
1255 onstack[i] = 0;
1256 } else if (mode == x86_64_mode_integer && nb_reg_args + reg_count <= REGN) {
1257 nb_reg_args += reg_count;
1258 onstack[i] = 0;
1259 } else if (mode == x86_64_mode_none) {
1260 onstack[i] = 0;
1261 } else {
1262 if (align == 16 && (stack_adjust &= 15)) {
1263 onstack[i] = 2;
1264 stack_adjust = 0;
1265 } else
1266 onstack[i] = 1;
1267 stack_adjust += size;
1268 }
1269 }
1270
1271 if (nb_sse_args && tcc_state->nosse)
1272 tcc_error("SSE disabled but floating point arguments passed");
1273
1274 /* fetch cpu flag before generating any code */
1275 if (vtop >= vstack && (vtop->r & VT_VALMASK) == VT_CMP)
1276 gv(RC_INT);
1277
1278 /* for struct arguments, we need to call memcpy and the function
1279 call breaks register passing arguments we are preparing.
1280 So, we process arguments which will be passed by stack first. */
1281 gen_reg = nb_reg_args;
1282 sse_reg = nb_sse_args;
1283 args_size = 0;
1284 stack_adjust &= 15;
1285 for (i = 0; i < nb_args;) {
1286 mode = classify_x86_64_arg(&vtop[-i].type, NULL, &size, &align, &reg_count);
1287 if (!onstack[i]) {
1288 ++i;
1289 continue;
1290 }
1291 /* Possibly adjust stack to align SSE boundary. We're processing
1292 args from right to left while allocating happens left to right
1293 (stack grows down), so the adjustment needs to happen _after_
1294 an argument that requires it. */
1295 if (stack_adjust) {
1296 o(0x50); /* push %rax; aka sub $8,%rsp */
1297 args_size += 8;
1298 stack_adjust = 0;
1299 }
1300 if (onstack[i] == 2)
1301 stack_adjust = 1;
1302
1303 vrotb(i+1);
1304
1305 switch (vtop->type.t & VT_BTYPE) {
1306 case VT_STRUCT:
1307 /* allocate the necessary size on stack */
1308 o(0x48);
1309 oad(0xec81, size); /* sub $xxx, %rsp */
1310 /* generate structure store */
1311 r = get_reg(RC_INT);
1312 orex(1, r, 0, 0x89); /* mov %rsp, r */
1313 o(0xe0 + REG_VALUE(r));
1314 vset(&vtop->type, r | VT_LVAL, 0);
1315 vswap();
1316 vstore();
1317 break;
1318
1319 case VT_LDOUBLE:
1320 gv(RC_ST0);
1321 oad(0xec8148, size); /* sub $xxx, %rsp */
1322 o(0x7cdb); /* fstpt 0(%rsp) */
1323 g(0x24);
1324 g(0x00);
1325 break;
1326
1327 case VT_FLOAT:
1328 case VT_DOUBLE:
1329 assert(mode == x86_64_mode_sse);
1330 r = gv(RC_FLOAT);
1331 o(0x50); /* push $rax */
1332 /* movq %xmmN, (%rsp) */
1333 o(0xd60f66);
1334 o(0x04 + REG_VALUE(r)*8);
1335 o(0x24);
1336 break;
1337
1338 default:
1339 assert(mode == x86_64_mode_integer);
1340 /* simple type */
1341 /* XXX: implicit cast ? */
1342 r = gv(RC_INT);
1343 orex(0,r,0,0x50 + REG_VALUE(r)); /* push r */
1344 break;
1345 }
1346 args_size += size;
1347
1348 vpop();
1349 --nb_args;
1350 onstack++;
1351 }
1352
1353 /* XXX This should be superfluous. */
1354 save_regs(0); /* save used temporary registers */
1355
1356 /* then, we prepare register passing arguments.
1357 Note that we cannot set RDX and RCX in this loop because gv()
1358 may break these temporary registers. Let's use R10 and R11
1359 instead of them */
1360 assert(gen_reg <= REGN);
1361 assert(sse_reg <= 8);
1362 for(i = 0; i < nb_args; i++) {
1363 mode = classify_x86_64_arg(&vtop->type, &type, &size, &align, &reg_count);
1364 /* Alter stack entry type so that gv() knows how to treat it */
1365 vtop->type = type;
1366 if (mode == x86_64_mode_sse) {
1367 if (reg_count == 2) {
1368 sse_reg -= 2;
1369 gv(RC_FRET); /* Use pair load into xmm0 & xmm1 */
1370 if (sse_reg) { /* avoid redundant movaps %xmm0, %xmm0 */
1371 /* movaps %xmm0, %xmmN */
1372 o(0x280f);
1373 o(0xc0 + (sse_reg << 3));
1374 /* movaps %xmm1, %xmmN */
1375 o(0x280f);
1376 o(0xc1 + ((sse_reg+1) << 3));
1377 }
1378 } else {
1379 assert(reg_count == 1);
1380 --sse_reg;
1381 /* Load directly to register */
1382 gv(RC_XMM0 << sse_reg);
1383 }
1384 } else if (mode == x86_64_mode_integer) {
1385 /* simple type */
1386 /* XXX: implicit cast ? */
1387 int d;
1388 gen_reg -= reg_count;
1389 r = gv(RC_INT);
1390 d = arg_prepare_reg(gen_reg);
1391 orex(1,d,r,0x89); /* mov */
1392 o(0xc0 + REG_VALUE(r) * 8 + REG_VALUE(d));
1393 if (reg_count == 2) {
1394 d = arg_prepare_reg(gen_reg+1);
1395 orex(1,d,vtop->r2,0x89); /* mov */
1396 o(0xc0 + REG_VALUE(vtop->r2) * 8 + REG_VALUE(d));
1397 }
1398 }
1399 vtop--;
1400 }
1401 assert(gen_reg == 0);
1402 assert(sse_reg == 0);
1403
1404 /* We shouldn't have many operands on the stack anymore, but the
1405 call address itself is still there, and it might be in %eax
1406 (or edx/ecx) currently, which the below writes would clobber.
1407 So evict all remaining operands here. */
1408 save_regs(0);
1409
1410 /* Copy R10 and R11 into RDX and RCX, respectively */
1411 if (nb_reg_args > 2) {
1412 o(0xd2894c); /* mov %r10, %rdx */
1413 if (nb_reg_args > 3) {
1414 o(0xd9894c); /* mov %r11, %rcx */
1415 }
1416 }
1417
1418 if (vtop->type.ref->f.func_type != FUNC_NEW) /* implies FUNC_OLD or FUNC_ELLIPSIS */
1419 oad(0xb8, nb_sse_args < 8 ? nb_sse_args : 8); /* mov nb_sse_args, %eax */
1420 gcall_or_jmp(0);
1421 if (args_size)
1422 gadd_sp(args_size);
1423 vtop--;
1424}
1425
1426
1427#define FUNC_PROLOG_SIZE 11
1428
1429static void push_arg_reg(int i) {
1430 loc -= 8;
1431 gen_modrm64(0x89, arg_regs[i], VT_LOCAL, NULL, loc);
1432}
1433
1434/* generate function prolog of type 't' */
1435void gfunc_prolog(CType *func_type)
1436{
1437 X86_64_Mode mode;
1438 int i, addr, align, size, reg_count;
1439 int param_addr = 0, reg_param_index, sse_param_index;
1440 Sym *sym;
1441 CType *type;
1442
1443 sym = func_type->ref;
1444 addr = PTR_SIZE * 2;
1445 loc = 0;
1446 ind += FUNC_PROLOG_SIZE;
1447 func_sub_sp_offset = ind;
1448 func_ret_sub = 0;
1449
1450 if (sym->f.func_type == FUNC_ELLIPSIS) {
1451 int seen_reg_num, seen_sse_num, seen_stack_size;
1452 seen_reg_num = seen_sse_num = 0;
1453 /* frame pointer and return address */
1454 seen_stack_size = PTR_SIZE * 2;
1455 /* count the number of seen parameters */
1456 sym = func_type->ref;
1457 while ((sym = sym->next) != NULL) {
1458 type = &sym->type;
1459 mode = classify_x86_64_arg(type, NULL, &size, &align, &reg_count);
1460 switch (mode) {
1461 default:
1462 stack_arg:
1463 seen_stack_size = ((seen_stack_size + align - 1) & -align) + size;
1464 break;
1465
1466 case x86_64_mode_integer:
1467 if (seen_reg_num + reg_count > REGN)
1468 goto stack_arg;
1469 seen_reg_num += reg_count;
1470 break;
1471
1472 case x86_64_mode_sse:
1473 if (seen_sse_num + reg_count > 8)
1474 goto stack_arg;
1475 seen_sse_num += reg_count;
1476 break;
1477 }
1478 }
1479
1480 loc -= 16;
1481 /* movl $0x????????, -0x10(%rbp) */
1482 o(0xf045c7);
1483 gen_le32(seen_reg_num * 8);
1484 /* movl $0x????????, -0xc(%rbp) */
1485 o(0xf445c7);
1486 gen_le32(seen_sse_num * 16 + 48);
1487 /* movl $0x????????, -0x8(%rbp) */
1488 o(0xf845c7);
1489 gen_le32(seen_stack_size);
1490
1491 /* save all register passing arguments */
1492 for (i = 0; i < 8; i++) {
1493 loc -= 16;
1494 if (!tcc_state->nosse) {
1495 o(0xd60f66); /* movq */
1496 gen_modrm(7 - i, VT_LOCAL, NULL, loc);
1497 }
1498 /* movq $0, loc+8(%rbp) */
1499 o(0x85c748);
1500 gen_le32(loc + 8);
1501 gen_le32(0);
1502 }
1503 for (i = 0; i < REGN; i++) {
1504 push_arg_reg(REGN-1-i);
1505 }
1506 }
1507
1508 sym = func_type->ref;
1509 reg_param_index = 0;
1510 sse_param_index = 0;
1511
1512 /* if the function returns a structure, then add an
1513 implicit pointer parameter */
1514 func_vt = sym->type;
1515 mode = classify_x86_64_arg(&func_vt, NULL, &size, &align, &reg_count);
1516 if (mode == x86_64_mode_memory) {
1517 push_arg_reg(reg_param_index);
1518 func_vc = loc;
1519 reg_param_index++;
1520 }
1521 /* define parameters */
1522 while ((sym = sym->next) != NULL) {
1523 type = &sym->type;
1524 mode = classify_x86_64_arg(type, NULL, &size, &align, &reg_count);
1525 switch (mode) {
1526 case x86_64_mode_sse:
1527 if (tcc_state->nosse)
1528 tcc_error("SSE disabled but floating point arguments used");
1529 if (sse_param_index + reg_count <= 8) {
1530 /* save arguments passed by register */
1531 loc -= reg_count * 8;
1532 param_addr = loc;
1533 for (i = 0; i < reg_count; ++i) {
1534 o(0xd60f66); /* movq */
1535 gen_modrm(sse_param_index, VT_LOCAL, NULL, param_addr + i*8);
1536 ++sse_param_index;
1537 }
1538 } else {
1539 addr = (addr + align - 1) & -align;
1540 param_addr = addr;
1541 addr += size;
1542 }
1543 break;
1544
1545 case x86_64_mode_memory:
1546 case x86_64_mode_x87:
1547 addr = (addr + align - 1) & -align;
1548 param_addr = addr;
1549 addr += size;
1550 break;
1551
1552 case x86_64_mode_integer: {
1553 if (reg_param_index + reg_count <= REGN) {
1554 /* save arguments passed by register */
1555 loc -= reg_count * 8;
1556 param_addr = loc;
1557 for (i = 0; i < reg_count; ++i) {
1558 gen_modrm64(0x89, arg_regs[reg_param_index], VT_LOCAL, NULL, param_addr + i*8);
1559 ++reg_param_index;
1560 }
1561 } else {
1562 addr = (addr + align - 1) & -align;
1563 param_addr = addr;
1564 addr += size;
1565 }
1566 break;
1567 }
1568 default: break; /* nothing to be done for x86_64_mode_none */
1569 }
1570 sym_push(sym->v & ~SYM_FIELD, type,
1571 VT_LOCAL | VT_LVAL, param_addr);
1572 }
1573
1574#ifdef CONFIG_TCC_BCHECK
1575 /* leave some room for bound checking code */
1576 if (tcc_state->do_bounds_check) {
1577 func_bound_offset = lbounds_section->data_offset;
1578 func_bound_ind = ind;
1579 oad(0xb8, 0); /* lbound section pointer */
1580 o(0xc78948); /* mov %rax,%rdi ## first arg in %rdi, this must be ptr */
1581 oad(0xb8, 0); /* call to function */
1582 }
1583#endif
1584}
1585
1586/* generate function epilog */
1587void gfunc_epilog(void)
1588{
1589 int v, saved_ind;
1590
1591#ifdef CONFIG_TCC_BCHECK
1592 if (tcc_state->do_bounds_check
1593 && func_bound_offset != lbounds_section->data_offset)
1594 {
1595 addr_t saved_ind;
1596 addr_t *bounds_ptr;
1597 Sym *sym_data;
1598
1599 /* add end of table info */
1600 bounds_ptr = section_ptr_add(lbounds_section, sizeof(addr_t));
1601 *bounds_ptr = 0;
1602
1603 /* generate bound local allocation */
1604 sym_data = get_sym_ref(&char_pointer_type, lbounds_section,
1605 func_bound_offset, lbounds_section->data_offset);
1606 saved_ind = ind;
1607 ind = func_bound_ind;
1608 greloca(cur_text_section, sym_data, ind + 1, R_X86_64_64, 0);
1609 ind = ind + 5 + 3;
1610 gen_static_call(TOK___bound_local_new);
1611 ind = saved_ind;
1612
1613 /* generate bound check local freeing */
1614 o(0x5250); /* save returned value, if any */
1615 greloca(cur_text_section, sym_data, ind + 1, R_X86_64_64, 0);
1616 oad(0xb8, 0); /* mov xxx, %rax */
1617 o(0xc78948); /* mov %rax,%rdi # first arg in %rdi, this must be ptr */
1618 gen_static_call(TOK___bound_local_delete);
1619 o(0x585a); /* restore returned value, if any */
1620 }
1621#endif
1622 o(0xc9); /* leave */
1623 if (func_ret_sub == 0) {
1624 o(0xc3); /* ret */
1625 } else {
1626 o(0xc2); /* ret n */
1627 g(func_ret_sub);
1628 g(func_ret_sub >> 8);
1629 }
1630 /* align local size to word & save local variables */
1631 v = (-loc + 15) & -16;
1632 saved_ind = ind;
1633 ind = func_sub_sp_offset - FUNC_PROLOG_SIZE;
1634 o(0xe5894855); /* push %rbp, mov %rsp, %rbp */
1635 o(0xec8148); /* sub rsp, stacksize */
1636 gen_le32(v);
1637 ind = saved_ind;
1638}
1639
1640#endif /* not PE */
1641
1642/* generate a jump to a label */
1643int gjmp(int t)
1644{
1645 return gjmp2(0xe9, t);
1646}
1647
1648/* generate a jump to a fixed address */
1649void gjmp_addr(int a)
1650{
1651 int r;
1652 r = a - ind - 2;
1653 if (r == (char)r) {
1654 g(0xeb);
1655 g(r);
1656 } else {
1657 oad(0xe9, a - ind - 5);
1658 }
1659}
1660
1661ST_FUNC void gtst_addr(int inv, int a)
1662{
1663 int v = vtop->r & VT_VALMASK;
1664 if (v == VT_CMP) {
1665 inv ^= (vtop--)->c.i;
1666 a -= ind + 2;
1667 if (a == (char)a) {
1668 g(inv - 32);
1669 g(a);
1670 } else {
1671 g(0x0f);
1672 oad(inv - 16, a - 4);
1673 }
1674 } else if ((v & ~1) == VT_JMP) {
1675 if ((v & 1) != inv) {
1676 gjmp_addr(a);
1677 gsym(vtop->c.i);
1678 } else {
1679 gsym(vtop->c.i);
1680 o(0x05eb);
1681 gjmp_addr(a);
1682 }
1683 vtop--;
1684 }
1685}
1686
1687/* generate a test. set 'inv' to invert test. Stack entry is popped */
1688ST_FUNC int gtst(int inv, int t)
1689{
1690 int v = vtop->r & VT_VALMASK;
1691
1692 if (nocode_wanted) {
1693 ;
1694 } else if (v == VT_CMP) {
1695 /* fast case : can jump directly since flags are set */
1696 if (vtop->c.i & 0x100)
1697 {
1698 /* This was a float compare. If the parity flag is set
1699 the result was unordered. For anything except != this
1700 means false and we don't jump (anding both conditions).
1701 For != this means true (oring both).
1702 Take care about inverting the test. We need to jump
1703 to our target if the result was unordered and test wasn't NE,
1704 otherwise if unordered we don't want to jump. */
1705 vtop->c.i &= ~0x100;
1706 if (inv == (vtop->c.i == TOK_NE))
1707 o(0x067a); /* jp +6 */
1708 else
1709 {
1710 g(0x0f);
1711 t = gjmp2(0x8a, t); /* jp t */
1712 }
1713 }
1714 g(0x0f);
1715 t = gjmp2((vtop->c.i - 16) ^ inv, t);
1716 } else if (v == VT_JMP || v == VT_JMPI) {
1717 /* && or || optimization */
1718 if ((v & 1) == inv) {
1719 /* insert vtop->c jump list in t */
1720 uint32_t n1, n = vtop->c.i;
1721 if (n) {
1722 while ((n1 = read32le(cur_text_section->data + n)))
1723 n = n1;
1724 write32le(cur_text_section->data + n, t);
1725 t = vtop->c.i;
1726 }
1727 } else {
1728 t = gjmp(t);
1729 gsym(vtop->c.i);
1730 }
1731 }
1732 vtop--;
1733 return t;
1734}
1735
1736/* generate an integer binary operation */
1737void gen_opi(int op)
1738{
1739 int r, fr, opc, c;
1740 int ll, uu, cc;
1741
1742 ll = is64_type(vtop[-1].type.t);
1743 uu = (vtop[-1].type.t & VT_UNSIGNED) != 0;
1744 cc = (vtop->r & (VT_VALMASK | VT_LVAL | VT_SYM)) == VT_CONST;
1745
1746 switch(op) {
1747 case '+':
1748 case TOK_ADDC1: /* add with carry generation */
1749 opc = 0;
1750 gen_op8:
1751 if (cc && (!ll || (int)vtop->c.i == vtop->c.i)) {
1752 /* constant case */
1753 vswap();
1754 r = gv(RC_INT);
1755 vswap();
1756 c = vtop->c.i;
1757 if (c == (char)c) {
1758 /* XXX: generate inc and dec for smaller code ? */
1759 orex(ll, r, 0, 0x83);
1760 o(0xc0 | (opc << 3) | REG_VALUE(r));
1761 g(c);
1762 } else {
1763 orex(ll, r, 0, 0x81);
1764 oad(0xc0 | (opc << 3) | REG_VALUE(r), c);
1765 }
1766 } else {
1767 gv2(RC_INT, RC_INT);
1768 r = vtop[-1].r;
1769 fr = vtop[0].r;
1770 orex(ll, r, fr, (opc << 3) | 0x01);
1771 o(0xc0 + REG_VALUE(r) + REG_VALUE(fr) * 8);
1772 }
1773 vtop--;
1774 if (op >= TOK_ULT && op <= TOK_GT) {
1775 vtop->r = VT_CMP;
1776 vtop->c.i = op;
1777 }
1778 break;
1779 case '-':
1780 case TOK_SUBC1: /* sub with carry generation */
1781 opc = 5;
1782 goto gen_op8;
1783 case TOK_ADDC2: /* add with carry use */
1784 opc = 2;
1785 goto gen_op8;
1786 case TOK_SUBC2: /* sub with carry use */
1787 opc = 3;
1788 goto gen_op8;
1789 case '&':
1790 opc = 4;
1791 goto gen_op8;
1792 case '^':
1793 opc = 6;
1794 goto gen_op8;
1795 case '|':
1796 opc = 1;
1797 goto gen_op8;
1798 case '*':
1799 gv2(RC_INT, RC_INT);
1800 r = vtop[-1].r;
1801 fr = vtop[0].r;
1802 orex(ll, fr, r, 0xaf0f); /* imul fr, r */
1803 o(0xc0 + REG_VALUE(fr) + REG_VALUE(r) * 8);
1804 vtop--;
1805 break;
1806 case TOK_SHL:
1807 opc = 4;
1808 goto gen_shift;
1809 case TOK_SHR:
1810 opc = 5;
1811 goto gen_shift;
1812 case TOK_SAR:
1813 opc = 7;
1814 gen_shift:
1815 opc = 0xc0 | (opc << 3);
1816 if (cc) {
1817 /* constant case */
1818 vswap();
1819 r = gv(RC_INT);
1820 vswap();
1821 orex(ll, r, 0, 0xc1); /* shl/shr/sar $xxx, r */
1822 o(opc | REG_VALUE(r));
1823 g(vtop->c.i & (ll ? 63 : 31));
1824 } else {
1825 /* we generate the shift in ecx */
1826 gv2(RC_INT, RC_RCX);
1827 r = vtop[-1].r;
1828 orex(ll, r, 0, 0xd3); /* shl/shr/sar %cl, r */
1829 o(opc | REG_VALUE(r));
1830 }
1831 vtop--;
1832 break;
1833 case TOK_UDIV:
1834 case TOK_UMOD:
1835 uu = 1;
1836 goto divmod;
1837 case '/':
1838 case '%':
1839 case TOK_PDIV:
1840 uu = 0;
1841 divmod:
1842 /* first operand must be in eax */
1843 /* XXX: need better constraint for second operand */
1844 gv2(RC_RAX, RC_RCX);
1845 r = vtop[-1].r;
1846 fr = vtop[0].r;
1847 vtop--;
1848 save_reg(TREG_RDX);
1849 orex(ll, 0, 0, uu ? 0xd231 : 0x99); /* xor %edx,%edx : cqto */
1850 orex(ll, fr, 0, 0xf7); /* div fr, %eax */
1851 o((uu ? 0xf0 : 0xf8) + REG_VALUE(fr));
1852 if (op == '%' || op == TOK_UMOD)
1853 r = TREG_RDX;
1854 else
1855 r = TREG_RAX;
1856 vtop->r = r;
1857 break;
1858 default:
1859 opc = 7;
1860 goto gen_op8;
1861 }
1862}
1863
1864void gen_opl(int op)
1865{
1866 gen_opi(op);
1867}
1868
1869/* generate a floating point operation 'v = t1 op t2' instruction. The
1870 two operands are guaranteed to have the same floating point type */
1871/* XXX: need to use ST1 too */
1872void gen_opf(int op)
1873{
1874 int a, ft, fc, swapped, r;
1875 int float_type =
1876 (vtop->type.t & VT_BTYPE) == VT_LDOUBLE ? RC_ST0 : RC_FLOAT;
1877
1878 /* convert constants to memory references */
1879 if ((vtop[-1].r & (VT_VALMASK | VT_LVAL)) == VT_CONST) {
1880 vswap();
1881 gv(float_type);
1882 vswap();
1883 }
1884 if ((vtop[0].r & (VT_VALMASK | VT_LVAL)) == VT_CONST)
1885 gv(float_type);
1886
1887 /* must put at least one value in the floating point register */
1888 if ((vtop[-1].r & VT_LVAL) &&
1889 (vtop[0].r & VT_LVAL)) {
1890 vswap();
1891 gv(float_type);
1892 vswap();
1893 }
1894 swapped = 0;
1895 /* swap the stack if needed so that t1 is the register and t2 is
1896 the memory reference */
1897 if (vtop[-1].r & VT_LVAL) {
1898 vswap();
1899 swapped = 1;
1900 }
1901 if ((vtop->type.t & VT_BTYPE) == VT_LDOUBLE) {
1902 if (op >= TOK_ULT && op <= TOK_GT) {
1903 /* load on stack second operand */
1904 load(TREG_ST0, vtop);
1905 save_reg(TREG_RAX); /* eax is used by FP comparison code */
1906 if (op == TOK_GE || op == TOK_GT)
1907 swapped = !swapped;
1908 else if (op == TOK_EQ || op == TOK_NE)
1909 swapped = 0;
1910 if (swapped)
1911 o(0xc9d9); /* fxch %st(1) */
1912 if (op == TOK_EQ || op == TOK_NE)
1913 o(0xe9da); /* fucompp */
1914 else
1915 o(0xd9de); /* fcompp */
1916 o(0xe0df); /* fnstsw %ax */
1917 if (op == TOK_EQ) {
1918 o(0x45e480); /* and $0x45, %ah */
1919 o(0x40fC80); /* cmp $0x40, %ah */
1920 } else if (op == TOK_NE) {
1921 o(0x45e480); /* and $0x45, %ah */
1922 o(0x40f480); /* xor $0x40, %ah */
1923 op = TOK_NE;
1924 } else if (op == TOK_GE || op == TOK_LE) {
1925 o(0x05c4f6); /* test $0x05, %ah */
1926 op = TOK_EQ;
1927 } else {
1928 o(0x45c4f6); /* test $0x45, %ah */
1929 op = TOK_EQ;
1930 }
1931 vtop--;
1932 vtop->r = VT_CMP;
1933 vtop->c.i = op;
1934 } else {
1935 /* no memory reference possible for long double operations */
1936 load(TREG_ST0, vtop);
1937 swapped = !swapped;
1938
1939 switch(op) {
1940 default:
1941 case '+':
1942 a = 0;
1943 break;
1944 case '-':
1945 a = 4;
1946 if (swapped)
1947 a++;
1948 break;
1949 case '*':
1950 a = 1;
1951 break;
1952 case '/':
1953 a = 6;
1954 if (swapped)
1955 a++;
1956 break;
1957 }
1958 ft = vtop->type.t;
1959 fc = vtop->c.i;
1960 o(0xde); /* fxxxp %st, %st(1) */
1961 o(0xc1 + (a << 3));
1962 vtop--;
1963 }
1964 } else {
1965 if (op >= TOK_ULT && op <= TOK_GT) {
1966 /* if saved lvalue, then we must reload it */
1967 r = vtop->r;
1968 fc = vtop->c.i;
1969 if ((r & VT_VALMASK) == VT_LLOCAL) {
1970 SValue v1;
1971 r = get_reg(RC_INT);
1972 v1.type.t = VT_PTR;
1973 v1.r = VT_LOCAL | VT_LVAL;
1974 v1.c.i = fc;
1975 load(r, &v1);
1976 fc = 0;
1977 }
1978
1979 if (op == TOK_EQ || op == TOK_NE) {
1980 swapped = 0;
1981 } else {
1982 if (op == TOK_LE || op == TOK_LT)
1983 swapped = !swapped;
1984 if (op == TOK_LE || op == TOK_GE) {
1985 op = 0x93; /* setae */
1986 } else {
1987 op = 0x97; /* seta */
1988 }
1989 }
1990
1991 if (swapped) {
1992 gv(RC_FLOAT);
1993 vswap();
1994 }
1995 assert(!(vtop[-1].r & VT_LVAL));
1996
1997 if ((vtop->type.t & VT_BTYPE) == VT_DOUBLE)
1998 o(0x66);
1999 if (op == TOK_EQ || op == TOK_NE)
2000 o(0x2e0f); /* ucomisd */
2001 else
2002 o(0x2f0f); /* comisd */
2003
2004 if (vtop->r & VT_LVAL) {
2005 gen_modrm(vtop[-1].r, r, vtop->sym, fc);
2006 } else {
2007 o(0xc0 + REG_VALUE(vtop[0].r) + REG_VALUE(vtop[-1].r)*8);
2008 }
2009
2010 vtop--;
2011 vtop->r = VT_CMP;
2012 vtop->c.i = op | 0x100;
2013 } else {
2014 assert((vtop->type.t & VT_BTYPE) != VT_LDOUBLE);
2015 switch(op) {
2016 default:
2017 case '+':
2018 a = 0;
2019 break;
2020 case '-':
2021 a = 4;
2022 break;
2023 case '*':
2024 a = 1;
2025 break;
2026 case '/':
2027 a = 6;
2028 break;
2029 }
2030 ft = vtop->type.t;
2031 fc = vtop->c.i;
2032 assert((ft & VT_BTYPE) != VT_LDOUBLE);
2033
2034 r = vtop->r;
2035 /* if saved lvalue, then we must reload it */
2036 if ((vtop->r & VT_VALMASK) == VT_LLOCAL) {
2037 SValue v1;
2038 r = get_reg(RC_INT);
2039 v1.type.t = VT_PTR;
2040 v1.r = VT_LOCAL | VT_LVAL;
2041 v1.c.i = fc;
2042 load(r, &v1);
2043 fc = 0;
2044 }
2045
2046 assert(!(vtop[-1].r & VT_LVAL));
2047 if (swapped) {
2048 assert(vtop->r & VT_LVAL);
2049 gv(RC_FLOAT);
2050 vswap();
2051 }
2052
2053 if ((ft & VT_BTYPE) == VT_DOUBLE) {
2054 o(0xf2);
2055 } else {
2056 o(0xf3);
2057 }
2058 o(0x0f);
2059 o(0x58 + a);
2060
2061 if (vtop->r & VT_LVAL) {
2062 gen_modrm(vtop[-1].r, r, vtop->sym, fc);
2063 } else {
2064 o(0xc0 + REG_VALUE(vtop[0].r) + REG_VALUE(vtop[-1].r)*8);
2065 }
2066
2067 vtop--;
2068 }
2069 }
2070}
2071
2072/* convert integers to fp 't' type. Must handle 'int', 'unsigned int'
2073 and 'long long' cases. */
2074void gen_cvt_itof(int t)
2075{
2076 if ((t & VT_BTYPE) == VT_LDOUBLE) {
2077 save_reg(TREG_ST0);
2078 gv(RC_INT);
2079 if ((vtop->type.t & VT_BTYPE) == VT_LLONG) {
2080 /* signed long long to float/double/long double (unsigned case
2081 is handled generically) */
2082 o(0x50 + (vtop->r & VT_VALMASK)); /* push r */
2083 o(0x242cdf); /* fildll (%rsp) */
2084 o(0x08c48348); /* add $8, %rsp */
2085 } else if ((vtop->type.t & (VT_BTYPE | VT_UNSIGNED)) ==
2086 (VT_INT | VT_UNSIGNED)) {
2087 /* unsigned int to float/double/long double */
2088 o(0x6a); /* push $0 */
2089 g(0x00);
2090 o(0x50 + (vtop->r & VT_VALMASK)); /* push r */
2091 o(0x242cdf); /* fildll (%rsp) */
2092 o(0x10c48348); /* add $16, %rsp */
2093 } else {
2094 /* int to float/double/long double */
2095 o(0x50 + (vtop->r & VT_VALMASK)); /* push r */
2096 o(0x2404db); /* fildl (%rsp) */
2097 o(0x08c48348); /* add $8, %rsp */
2098 }
2099 vtop->r = TREG_ST0;
2100 } else {
2101 int r = get_reg(RC_FLOAT);
2102 gv(RC_INT);
2103 o(0xf2 + ((t & VT_BTYPE) == VT_FLOAT?1:0));
2104 if ((vtop->type.t & (VT_BTYPE | VT_UNSIGNED)) ==
2105 (VT_INT | VT_UNSIGNED) ||
2106 (vtop->type.t & VT_BTYPE) == VT_LLONG) {
2107 o(0x48); /* REX */
2108 }
2109 o(0x2a0f);
2110 o(0xc0 + (vtop->r & VT_VALMASK) + REG_VALUE(r)*8); /* cvtsi2sd */
2111 vtop->r = r;
2112 }
2113}
2114
2115/* convert from one floating point type to another */
2116void gen_cvt_ftof(int t)
2117{
2118 int ft, bt, tbt;
2119
2120 ft = vtop->type.t;
2121 bt = ft & VT_BTYPE;
2122 tbt = t & VT_BTYPE;
2123
2124 if (bt == VT_FLOAT) {
2125 gv(RC_FLOAT);
2126 if (tbt == VT_DOUBLE) {
2127 o(0x140f); /* unpcklps */
2128 o(0xc0 + REG_VALUE(vtop->r)*9);
2129 o(0x5a0f); /* cvtps2pd */
2130 o(0xc0 + REG_VALUE(vtop->r)*9);
2131 } else if (tbt == VT_LDOUBLE) {
2132 save_reg(RC_ST0);
2133 /* movss %xmm0,-0x10(%rsp) */
2134 o(0x110ff3);
2135 o(0x44 + REG_VALUE(vtop->r)*8);
2136 o(0xf024);
2137 o(0xf02444d9); /* flds -0x10(%rsp) */
2138 vtop->r = TREG_ST0;
2139 }
2140 } else if (bt == VT_DOUBLE) {
2141 gv(RC_FLOAT);
2142 if (tbt == VT_FLOAT) {
2143 o(0x140f66); /* unpcklpd */
2144 o(0xc0 + REG_VALUE(vtop->r)*9);
2145 o(0x5a0f66); /* cvtpd2ps */
2146 o(0xc0 + REG_VALUE(vtop->r)*9);
2147 } else if (tbt == VT_LDOUBLE) {
2148 save_reg(RC_ST0);
2149 /* movsd %xmm0,-0x10(%rsp) */
2150 o(0x110ff2);
2151 o(0x44 + REG_VALUE(vtop->r)*8);
2152 o(0xf024);
2153 o(0xf02444dd); /* fldl -0x10(%rsp) */
2154 vtop->r = TREG_ST0;
2155 }
2156 } else {
2157 int r;
2158 gv(RC_ST0);
2159 r = get_reg(RC_FLOAT);
2160 if (tbt == VT_DOUBLE) {
2161 o(0xf0245cdd); /* fstpl -0x10(%rsp) */
2162 /* movsd -0x10(%rsp),%xmm0 */
2163 o(0x100ff2);
2164 o(0x44 + REG_VALUE(r)*8);
2165 o(0xf024);
2166 vtop->r = r;
2167 } else if (tbt == VT_FLOAT) {
2168 o(0xf0245cd9); /* fstps -0x10(%rsp) */
2169 /* movss -0x10(%rsp),%xmm0 */
2170 o(0x100ff3);
2171 o(0x44 + REG_VALUE(r)*8);
2172 o(0xf024);
2173 vtop->r = r;
2174 }
2175 }
2176}
2177
2178/* convert fp to int 't' type */
2179void gen_cvt_ftoi(int t)
2180{
2181 int ft, bt, size, r;
2182 ft = vtop->type.t;
2183 bt = ft & VT_BTYPE;
2184 if (bt == VT_LDOUBLE) {
2185 gen_cvt_ftof(VT_DOUBLE);
2186 bt = VT_DOUBLE;
2187 }
2188
2189 gv(RC_FLOAT);
2190 if (t != VT_INT)
2191 size = 8;
2192 else
2193 size = 4;
2194
2195 r = get_reg(RC_INT);
2196 if (bt == VT_FLOAT) {
2197 o(0xf3);
2198 } else if (bt == VT_DOUBLE) {
2199 o(0xf2);
2200 } else {
2201 assert(0);
2202 }
2203 orex(size == 8, r, 0, 0x2c0f); /* cvttss2si or cvttsd2si */
2204 o(0xc0 + REG_VALUE(vtop->r) + REG_VALUE(r)*8);
2205 vtop->r = r;
2206}
2207
2208/* computed goto support */
2209void ggoto(void)
2210{
2211 gcall_or_jmp(1);
2212 vtop--;
2213}
2214
2215/* Save the stack pointer onto the stack and return the location of its address */
2216ST_FUNC void gen_vla_sp_save(int addr) {
2217 /* mov %rsp,addr(%rbp)*/
2218 gen_modrm64(0x89, TREG_RSP, VT_LOCAL, NULL, addr);
2219}
2220
2221/* Restore the SP from a location on the stack */
2222ST_FUNC void gen_vla_sp_restore(int addr) {
2223 gen_modrm64(0x8b, TREG_RSP, VT_LOCAL, NULL, addr);
2224}
2225
2226#ifdef TCC_TARGET_PE
2227/* Save result of gen_vla_alloc onto the stack */
2228ST_FUNC void gen_vla_result(int addr) {
2229 /* mov %rax,addr(%rbp)*/
2230 gen_modrm64(0x89, TREG_RAX, VT_LOCAL, NULL, addr);
2231}
2232#endif
2233
2234/* Subtract from the stack pointer, and push the resulting value onto the stack */
2235ST_FUNC void gen_vla_alloc(CType *type, int align) {
2236#ifdef TCC_TARGET_PE
2237 /* alloca does more than just adjust %rsp on Windows */
2238 vpush_global_sym(&func_old_type, TOK_alloca);
2239 vswap(); /* Move alloca ref past allocation size */
2240 gfunc_call(1);
2241#else
2242 int r;
2243 r = gv(RC_INT); /* allocation size */
2244 /* sub r,%rsp */
2245 o(0x2b48);
2246 o(0xe0 | REG_VALUE(r));
2247 /* We align to 16 bytes rather than align */
2248 /* and ~15, %rsp */
2249 o(0xf0e48348);
2250 vpop();
2251#endif
2252}
2253
2254
2255/* end of x86-64 code generator */
2256/*************************************************************/
2257#endif /* ! TARGET_DEFS_ONLY */
2258/******************************************************/
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