[270] | 1 | /* mbed Microcontroller Library
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| 2 | * Copyright (c) 2006-2013 ARM Limited
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| 3 | *
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| 4 | * Licensed under the Apache License, Version 2.0 (the "License");
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| 5 | * you may not use this file except in compliance with the License.
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| 6 | * You may obtain a copy of the License at
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| 7 | *
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| 8 | * http://www.apache.org/licenses/LICENSE-2.0
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| 9 | *
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| 10 | * Unless required by applicable law or agreed to in writing, software
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| 11 | * distributed under the License is distributed on an "AS IS" BASIS,
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| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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| 13 | * See the License for the specific language governing permissions and
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| 14 | * limitations under the License.
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| 15 | */
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| 16 | #include <stddef.h>
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| 17 | #include "us_ticker_api.h"
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| 18 | #include "PeripheralNames.h"
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| 19 | #include "ostm_iodefine.h"
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| 20 |
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| 21 | #include "RZ_A1_Init.h"
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| 22 | #include "MBRZA1H.h"
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| 23 |
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| 24 | #define US_TICKER_TIMER_IRQn (OSTMI1TINT_IRQn)
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| 25 | #define CPG_STBCR5_BIT_MSTP50 (0x01u) /* OSTM1 */
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| 26 |
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| 27 | #define US_TICKER_CLOCK_US_DEV (1000000)
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| 28 |
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| 29 | int us_ticker_inited = 0;
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| 30 | static double count_clock = 0;
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| 31 | static uint32_t last_read = 0;
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| 32 | static uint32_t wrap_arround = 0;
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| 33 | static uint64_t ticker_us_last64 = 0;
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| 34 |
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| 35 | void us_ticker_interrupt(void) {
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| 36 | us_ticker_irq_handler();
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| 37 | }
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| 38 |
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| 39 | void us_ticker_init(void) {
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| 40 | if (us_ticker_inited) return;
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| 41 | us_ticker_inited = 1;
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| 42 |
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| 43 | /* set Counter Clock(us) */
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| 44 | if (false == RZ_A1_IsClockMode0()) {
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| 45 | count_clock = ((double)CM1_RENESAS_RZ_A1_P0_CLK / (double)US_TICKER_CLOCK_US_DEV);
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| 46 | } else {
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| 47 | count_clock = ((double)CM0_RENESAS_RZ_A1_P0_CLK / (double)US_TICKER_CLOCK_US_DEV);
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| 48 | }
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| 49 |
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| 50 | /* Power Control for Peripherals */
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| 51 | CPGSTBCR5 &= ~(CPG_STBCR5_BIT_MSTP50); /* enable OSTM1 clock */
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| 52 |
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| 53 | // timer settings
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| 54 | OSTM1TT = 0x01; /* Stop the counter and clears the OSTM1TE bit. */
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| 55 | OSTM1CTL = 0x02; /* Free running timer mode. Interrupt disabled when star counter */
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| 56 |
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| 57 | OSTM1TS = 0x1; /* Start the counter and sets the OSTM0TE bit. */
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| 58 |
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| 59 | // INTC settings
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| 60 | InterruptHandlerRegister(US_TICKER_TIMER_IRQn, (void (*)(uint32_t))us_ticker_interrupt);
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| 61 | GIC_SetPriority(US_TICKER_TIMER_IRQn, 5);
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| 62 | GIC_EnableIRQ(US_TICKER_TIMER_IRQn);
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| 63 | }
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| 64 |
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| 65 | static uint64_t ticker_read_counter64(void) {
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| 66 | uint32_t cnt_val;
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| 67 | uint64_t cnt_val64;
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| 68 |
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| 69 | if (!us_ticker_inited)
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| 70 | us_ticker_init();
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| 71 |
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| 72 | /* read counter */
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| 73 | cnt_val = OSTM1CNT;
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| 74 | if (last_read > cnt_val) {
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| 75 | wrap_arround++;
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| 76 | }
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| 77 | last_read = cnt_val;
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| 78 | cnt_val64 = ((uint64_t)wrap_arround << 32) + cnt_val;
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| 79 |
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| 80 | return cnt_val64;
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| 81 | }
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| 82 |
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| 83 | uint32_t us_ticker_read() {
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| 84 | uint64_t cnt_val64;
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| 85 | uint64_t us_val64;
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| 86 | int check_irq_masked;
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| 87 |
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| 88 | check_irq_masked = __disable_irq();
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| 89 |
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| 90 | cnt_val64 = ticker_read_counter64();
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| 91 | us_val64 = (cnt_val64 / count_clock);
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| 92 | ticker_us_last64 = us_val64;
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| 93 |
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| 94 | if (!check_irq_masked) {
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| 95 | __enable_irq();
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| 96 | }
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| 97 |
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| 98 | /* clock to us */
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| 99 | return (uint32_t)us_val64;
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| 100 | }
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| 101 |
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| 102 | void us_ticker_set_interrupt(timestamp_t timestamp) {
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| 103 | // set match value
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| 104 | uint64_t timestamp64;
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| 105 | uint64_t set_cmp_val64;
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| 106 | volatile uint32_t set_cmp_val;
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| 107 | uint64_t count_val_64;
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| 108 |
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| 109 | /* calc compare mach timestamp */
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| 110 | timestamp64 = (ticker_us_last64 & 0xFFFFFFFF00000000) + timestamp;
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| 111 | if (timestamp < (ticker_us_last64 & 0x00000000FFFFFFFF)) {
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| 112 | /* This event is wrap arround */
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| 113 | timestamp64 += 0x100000000;
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| 114 | }
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| 115 |
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| 116 | /* calc compare mach timestamp */
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| 117 | set_cmp_val64 = timestamp64 * count_clock;
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| 118 | set_cmp_val = (uint32_t)(set_cmp_val64 & 0x00000000FFFFFFFF);
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| 119 | count_val_64 = ticker_read_counter64();
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| 120 | if (set_cmp_val64 <= (count_val_64 + 500)) {
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| 121 | GIC_SetPendingIRQ(US_TICKER_TIMER_IRQn);
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| 122 | GIC_EnableIRQ(US_TICKER_TIMER_IRQn);
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| 123 | return;
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| 124 | }
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| 125 | OSTM1CMP = set_cmp_val;
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| 126 | GIC_EnableIRQ(US_TICKER_TIMER_IRQn);
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| 127 | }
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| 128 |
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| 129 | void us_ticker_disable_interrupt(void) {
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| 130 | GIC_DisableIRQ(US_TICKER_TIMER_IRQn);
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| 131 | }
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| 132 |
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| 133 | void us_ticker_clear_interrupt(void) {
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| 134 | GIC_ClearPendingIRQ(US_TICKER_TIMER_IRQn);
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| 135 | }
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