1 | /* mbed Microcontroller Library
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2 | * Copyright (c) 2006-2013 ARM Limited
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3 | *
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4 | * Licensed under the Apache License, Version 2.0 (the "License");
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5 | * you may not use this file except in compliance with the License.
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6 | * You may obtain a copy of the License at
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7 | *
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8 | * http://www.apache.org/licenses/LICENSE-2.0
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9 | *
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10 | * Unless required by applicable law or agreed to in writing, software
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11 | * distributed under the License is distributed on an "AS IS" BASIS,
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12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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13 | * See the License for the specific language governing permissions and
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14 | * limitations under the License.
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15 | */
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16 | #include "mbed_assert.h"
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17 | #include <math.h>
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18 |
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19 | #include "spi_api.h"
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20 | #include "cmsis.h"
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21 | #include "pinmap.h"
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22 | #include "mbed_error.h"
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23 | #include "RZ_A1_Init.h"
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24 |
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25 | static const PinMap PinMap_SPI_SCLK[] = {
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26 | {P10_12, SPI_0, 4},
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27 | {P4_4 , SPI_1, 2},
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28 | {P11_12, SPI_1, 2},
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29 | {P8_3 , SPI_2, 3},
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30 | {NC , NC , 0}
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31 | };
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32 |
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33 | static const PinMap PinMap_SPI_SSEL[] = {
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34 | {P10_13, SPI_0, 4},
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35 | {P4_5 , SPI_1, 2},
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36 | {P11_13, SPI_1, 2},
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37 | {P8_4 , SPI_2, 3},
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38 | {NC , NC , 0}
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39 | };
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40 |
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41 | static const PinMap PinMap_SPI_MOSI[] = {
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42 | {P10_14, SPI_0, 4},
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43 | {P4_6 , SPI_1, 2},
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44 | {P11_14, SPI_1, 2},
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45 | {P8_5 , SPI_2, 3},
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46 | {NC , NC , 0}
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47 | };
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48 |
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49 | static const PinMap PinMap_SPI_MISO[] = {
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50 | {P10_15, SPI_0, 4},
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51 | {P4_7 , SPI_1, 2},
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52 | {P11_15, SPI_1, 2},
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53 | {P8_6 , SPI_2, 3},
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54 | {NC , NC , 0}
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55 | };
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56 |
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57 | static const struct st_rspi *RSPI[] = RSPI_ADDRESS_LIST;
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58 |
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59 | static inline void spi_disable(spi_t *obj);
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60 | static inline void spi_enable(spi_t *obj);
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61 | static inline int spi_readable(spi_t *obj);
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62 | static inline void spi_write(spi_t *obj, int value);
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63 | static inline int spi_read(spi_t *obj);
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64 |
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65 | void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
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66 | // determine the SPI to use
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67 | volatile uint8_t dummy;
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68 | uint32_t spi_mosi = pinmap_peripheral(mosi, PinMap_SPI_MOSI);
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69 | uint32_t spi_miso = pinmap_peripheral(miso, PinMap_SPI_MISO);
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70 | uint32_t spi_sclk = pinmap_peripheral(sclk, PinMap_SPI_SCLK);
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71 | uint32_t spi_ssel = pinmap_peripheral(ssel, PinMap_SPI_SSEL);
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72 | uint32_t spi_data = pinmap_merge(spi_mosi, spi_miso);
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73 | uint32_t spi_cntl = pinmap_merge(spi_sclk, spi_ssel);
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74 | uint32_t spi = pinmap_merge(spi_data, spi_cntl);
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75 |
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76 | MBED_ASSERT((int)spi != NC);
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77 |
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78 | obj->spi = (struct st_rspi *)RSPI[spi];
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79 |
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80 | // enable power and clocking
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81 | switch (spi) {
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82 | case SPI_0: CPGSTBCR10 &= ~(0x80); break;
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83 | case SPI_1: CPGSTBCR10 &= ~(0x40); break;
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84 | case SPI_2: CPGSTBCR10 &= ~(0x20); break;
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85 | }
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86 | dummy = CPGSTBCR10;
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87 |
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88 | obj->spi->SPCR = 0x00; // CTRL to 0
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89 | obj->spi->SPSCR = 0x00; // no sequential operation
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90 | obj->spi->SSLP = 0x00; // SSL 'L' active
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91 | obj->spi->SPDCR = 0x20; // byte access
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92 | obj->spi->SPCKD = 0x00; // SSL -> enable CLK delay : 1RSPCK
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93 | obj->spi->SSLND = 0x00; // CLK end -> SSL neg delay : 1RSPCK
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94 | obj->spi->SPND = 0x00; // delay between CMD : 1RSPCK + 2P1CLK
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95 | obj->spi->SPPCR = 0x20; // MOSI Idle fixed value equals 0
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96 | obj->spi->SPBFCR = 0xf0; // and set trigger count: read 1, write 1
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97 | obj->spi->SPBFCR = 0x30; // and reset buffer
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98 |
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99 | // pin out the spi pins
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100 | pinmap_pinout(mosi, PinMap_SPI_MOSI);
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101 | pinmap_pinout(miso, PinMap_SPI_MISO);
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102 | pinmap_pinout(sclk, PinMap_SPI_SCLK);
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103 | if ((int)ssel != NC) {
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104 | pinmap_pinout(ssel, PinMap_SPI_SSEL);
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105 | }
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106 | }
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107 |
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108 | void spi_free(spi_t *obj) {}
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109 |
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110 | void spi_format(spi_t *obj, int bits, int mode, int slave) {
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111 | int DSS; // DSS (data select size)
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112 | int polarity = (mode & 0x2) ? 1 : 0;
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113 | int phase = (mode & 0x1) ? 1 : 0;
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114 | uint16_t tmp = 0;
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115 | uint16_t mask = 0xf03;
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116 | uint16_t wk_spcmd0;
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117 | uint8_t splw;
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118 |
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119 | switch (mode) {
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120 | case 0:
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121 | case 1:
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122 | case 2:
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123 | case 3:
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124 | // Do Nothing
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125 | break;
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126 | default:
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127 | error("SPI format error");
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128 | return;
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129 | }
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130 |
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131 | switch (bits) {
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132 | case 8:
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133 | DSS = 0x7;
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134 | splw = 0x20;
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135 | break;
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136 | case 16:
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137 | DSS = 0xf;
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138 | splw = 0x40;
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139 | break;
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140 | case 32:
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141 | DSS = 0x2;
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142 | splw = 0x60;
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143 | break;
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144 | default:
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145 | error("SPI module don't support other than 8/16/32bits");
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146 | return;
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147 | }
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148 | tmp |= phase;
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149 | tmp |= (polarity << 1);
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150 | tmp |= (DSS << 8);
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151 | obj->bits = bits;
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152 |
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153 | spi_disable(obj);
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154 | wk_spcmd0 = obj->spi->SPCMD0;
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155 | wk_spcmd0 &= ~mask;
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156 | wk_spcmd0 |= (mask & tmp);
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157 | obj->spi->SPCMD0 = wk_spcmd0;
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158 | obj->spi->SPDCR = splw;
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159 | if (slave) {
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160 | obj->spi->SPCR &=~(1 << 3); // MSTR to 0
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161 | } else {
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162 | obj->spi->SPCR |= (1 << 3); // MSTR to 1
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163 | }
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164 | spi_enable(obj);
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165 | }
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166 |
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167 | void spi_frequency(spi_t *obj, int hz) {
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168 | uint32_t pclk_base;
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169 | uint32_t div;
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170 | uint32_t brdv = 0;
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171 | uint32_t hz_max;
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172 | uint32_t hz_min;
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173 | uint16_t mask = 0x000c;
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174 | uint16_t wk_spcmd0;
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175 |
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176 | /* set PCLK */
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177 | if (RZ_A1_IsClockMode0() == false) {
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178 | pclk_base = CM1_RENESAS_RZ_A1_P1_CLK;
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179 | } else {
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180 | pclk_base = CM0_RENESAS_RZ_A1_P1_CLK;
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181 | }
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182 |
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183 | hz_min = pclk_base / 2 / 256 / 8;
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184 | hz_max = pclk_base / 2;
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185 | if ((hz < hz_min) || (hz > hz_max)) {
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186 | error("Couldn't setup requested SPI frequency");
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187 | return;
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188 | }
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189 |
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190 | div = (pclk_base / hz / 2);
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191 | while (div > 256) {
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192 | div >>= 1;
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193 | brdv++;
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194 | }
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195 | div -= 1;
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196 | brdv = (brdv << 2);
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197 |
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198 | spi_disable(obj);
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199 | obj->spi->SPBR = div;
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200 | wk_spcmd0 = obj->spi->SPCMD0;
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201 | wk_spcmd0 &= ~mask;
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202 | wk_spcmd0 |= (mask & brdv);
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203 | obj->spi->SPCMD0 = wk_spcmd0;
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204 | spi_enable(obj);
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205 | }
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206 |
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207 | static inline void spi_disable(spi_t *obj) {
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208 | obj->spi->SPCR &= ~(1 << 6); // SPE to 0
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209 | }
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210 |
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211 | static inline void spi_enable(spi_t *obj) {
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212 | obj->spi->SPCR |= (1 << 6); // SPE to 1
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213 | }
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214 |
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215 | static inline int spi_readable(spi_t *obj) {
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216 | return obj->spi->SPSR & (1 << 7); // SPRF
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217 | }
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218 |
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219 | static inline int spi_tend(spi_t *obj) {
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220 | return obj->spi->SPSR & (1 << 6); // TEND
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221 | }
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222 |
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223 | static inline void spi_write(spi_t *obj, int value) {
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224 | if (obj->bits == 8) {
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225 | obj->spi->SPDR.UINT8[0] = (uint8_t)value;
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226 | } else if (obj->bits == 16) {
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227 | obj->spi->SPDR.UINT16[0] = (uint16_t)value;
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228 | } else {
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229 | obj->spi->SPDR.UINT32 = (uint32_t)value;
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230 | }
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231 | }
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232 |
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233 | static inline int spi_read(spi_t *obj) {
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234 | int read_data;
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235 |
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236 | if (obj->bits == 8) {
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237 | read_data = obj->spi->SPDR.UINT8[0];
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238 | } else if (obj->bits == 16) {
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239 | read_data = obj->spi->SPDR.UINT16[0];
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240 | } else {
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241 | read_data = obj->spi->SPDR.UINT32;
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242 | }
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243 |
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244 | return read_data;
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245 | }
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246 |
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247 | int spi_master_write(spi_t *obj, int value) {
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248 | spi_write(obj, value);
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249 | while(!spi_tend(obj));
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250 | return spi_read(obj);
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251 | }
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252 |
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253 | int spi_slave_receive(spi_t *obj) {
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254 | return (spi_readable(obj) && !spi_busy(obj)) ? (1) : (0);
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255 | }
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256 |
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257 | int spi_slave_read(spi_t *obj) {
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258 | return spi_read(obj);
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259 | }
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260 |
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261 | void spi_slave_write(spi_t *obj, int value) {
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262 | spi_write(obj, value);
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263 | }
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264 |
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265 | int spi_busy(spi_t *obj) {
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266 | return 0;
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267 | }
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