[270] | 1 | /* mbed Microcontroller Library
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| 2 | * Copyright (c) 2006-2015 ARM Limited
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| 3 | *
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| 4 | * Licensed under the Apache License, Version 2.0 (the "License");
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| 5 | * you may not use this file except in compliance with the License.
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| 6 | * You may obtain a copy of the License at
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| 7 | *
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| 8 | * http://www.apache.org/licenses/LICENSE-2.0
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| 9 | *
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| 10 | * Unless required by applicable law or agreed to in writing, software
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| 11 | * distributed under the License is distributed on an "AS IS" BASIS,
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| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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| 13 | * See the License for the specific language governing permissions and
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| 14 | * limitations under the License.
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| 15 | */
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| 16 | // math.h required for floating point operations for baud rate calculation
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| 17 | #include "mbed_assert.h"
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| 18 | #include <math.h>
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| 19 | #include <string.h>
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| 20 | #include <stdlib.h>
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| 21 |
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| 22 | #include "serial_api.h"
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| 23 | #include "cmsis.h"
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| 24 | #include "pinmap.h"
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| 25 | #include "gpio_api.h"
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| 26 |
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| 27 | #include "scif_iodefine.h"
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| 28 | #include "cpg_iodefine.h"
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| 29 |
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| 30 | /******************************************************************************
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| 31 | * INITIALIZATION
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| 32 | ******************************************************************************/
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| 33 | #define PCLK (66666666) // Define the peripheral clock P1 frequency.
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| 34 |
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| 35 | #define UART_NUM 8
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| 36 | #define IRQ_NUM 2
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| 37 |
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| 38 | static void uart0_tx_irq(void);
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| 39 | static void uart1_tx_irq(void);
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| 40 | static void uart2_tx_irq(void);
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| 41 | static void uart3_tx_irq(void);
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| 42 | static void uart4_tx_irq(void);
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| 43 | static void uart5_tx_irq(void);
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| 44 | static void uart6_tx_irq(void);
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| 45 | static void uart7_tx_irq(void);
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| 46 | static void uart0_rx_irq(void);
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| 47 | static void uart1_rx_irq(void);
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| 48 | static void uart2_rx_irq(void);
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| 49 | static void uart3_rx_irq(void);
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| 50 | static void uart4_rx_irq(void);
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| 51 | static void uart5_rx_irq(void);
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| 52 | static void uart6_rx_irq(void);
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| 53 | static void uart7_rx_irq(void);
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| 54 |
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| 55 |
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| 56 | static const PinMap PinMap_UART_TX[] = {
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| 57 | {P2_14 , UART0, 6},
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| 58 | {P2_5 , UART1, 6},
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| 59 | {P4_12 , UART1, 7},
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| 60 | {P6_3 , UART2, 7},
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| 61 | {P4_14 , UART2, 7},
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| 62 | {P5_3 , UART3, 5},
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| 63 | {P8_8 , UART3, 7},
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| 64 | {P5_0 , UART4, 5},
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| 65 | {P8_14 , UART4, 7},
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| 66 | {P8_13 , UART5, 5},
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| 67 | {P11_10, UART5, 3},
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| 68 | {P6_6 , UART5, 5},
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| 69 | {P5_6 , UART6, 5},
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| 70 | {P11_1 , UART6, 4},
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| 71 | {P7_4 , UART7, 4},
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| 72 | {NC , NC , 0}
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| 73 | };
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| 74 |
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| 75 | static const PinMap PinMap_UART_RX[] = {
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| 76 | {P2_15 , UART0, 6},
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| 77 | {P2_6 , UART1, 6},
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| 78 | {P4_13 , UART1, 7},
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| 79 | {P6_2 , UART2, 7},
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| 80 | {P4_15 , UART2, 7},
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| 81 | {P5_4 , UART3, 5},
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| 82 | {P8_9 , UART3, 7},
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| 83 | {P5_1 , UART4, 5},
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| 84 | {P8_15 , UART4, 7},
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| 85 | {P8_11 , UART5, 5},
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| 86 | {P11_11, UART5, 3},
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| 87 | {P6_7 , UART5, 5},
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| 88 | {P5_7 , UART6, 5},
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| 89 | {P11_2 , UART6, 4},
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| 90 | {P7_5 , UART7, 4},
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| 91 | {NC , NC , 0}
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| 92 | };
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| 93 |
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| 94 | static const PinMap PinMap_UART_CTS[] = {
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| 95 | {P2_3 , UART1, 6},
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| 96 | {P11_7 , UART5, 3},
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| 97 | {P7_6 , UART7, 4},
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| 98 | {NC , NC , 0}
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| 99 | };
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| 100 | static const PinMap PinMap_UART_RTS[] = {
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| 101 | {P2_7 , UART1, 6},
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| 102 | {P11_8 , UART5, 3},
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| 103 | {P7_7 , UART7, 4},
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| 104 | {NC , NC , 0}
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| 105 | };
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| 106 |
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| 107 |
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| 108 |
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| 109 | static const struct st_scif *SCIF[] = SCIF_ADDRESS_LIST;
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| 110 | static uart_irq_handler irq_handler;
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| 111 |
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| 112 | int stdio_uart_inited = 0;
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| 113 | serial_t stdio_uart;
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| 114 |
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| 115 | struct serial_global_data_s {
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| 116 | uint32_t serial_irq_id;
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| 117 | gpio_t sw_rts, sw_cts;
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| 118 | uint8_t count, rx_irq_set_flow, rx_irq_set_api;
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| 119 | };
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| 120 |
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| 121 | static struct serial_global_data_s uart_data[UART_NUM];
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| 122 |
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| 123 | static const IRQn_Type irq_set_tbl[UART_NUM][IRQ_NUM] = {
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| 124 | {SCIFRXI0_IRQn, SCIFTXI0_IRQn},
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| 125 | {SCIFRXI1_IRQn, SCIFTXI1_IRQn},
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| 126 | {SCIFRXI2_IRQn, SCIFTXI2_IRQn},
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| 127 | {SCIFRXI3_IRQn, SCIFTXI3_IRQn},
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| 128 | {SCIFRXI4_IRQn, SCIFTXI4_IRQn},
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| 129 | {SCIFRXI5_IRQn, SCIFTXI5_IRQn},
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| 130 | {SCIFRXI6_IRQn, SCIFTXI6_IRQn},
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| 131 | {SCIFRXI7_IRQn, SCIFTXI7_IRQn}
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| 132 | };
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| 133 |
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| 134 | static const IRQHandler hander_set_tbl[UART_NUM][IRQ_NUM] = {
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| 135 | {uart0_rx_irq, uart0_tx_irq},
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| 136 | {uart1_rx_irq, uart1_tx_irq},
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| 137 | {uart2_rx_irq, uart2_tx_irq},
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| 138 | {uart3_rx_irq, uart3_tx_irq},
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| 139 | {uart4_rx_irq, uart4_tx_irq},
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| 140 | {uart5_rx_irq, uart5_tx_irq},
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| 141 | {uart6_rx_irq, uart6_tx_irq},
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| 142 | {uart7_rx_irq, uart7_tx_irq}
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| 143 | };
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| 144 |
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| 145 | static __IO uint16_t *SCSCR_MATCH[] = {
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| 146 | &SCSCR_0,
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| 147 | &SCSCR_1,
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| 148 | &SCSCR_2,
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| 149 | &SCSCR_3,
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| 150 | &SCSCR_4,
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| 151 | &SCSCR_5,
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| 152 | &SCSCR_6,
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| 153 | &SCSCR_7,
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| 154 | };
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| 155 |
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| 156 | static __IO uint16_t *SCFSR_MATCH[] = {
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| 157 | &SCFSR_0,
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| 158 | &SCFSR_1,
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| 159 | &SCFSR_2,
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| 160 | &SCFSR_3,
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| 161 | &SCFSR_4,
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| 162 | &SCFSR_5,
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| 163 | &SCFSR_6,
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| 164 | &SCFSR_7,
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| 165 | };
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| 166 |
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| 167 |
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| 168 | void serial_init(serial_t *obj, PinName tx, PinName rx) {
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| 169 | volatile uint8_t dummy ;
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| 170 | int is_stdio_uart = 0;
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| 171 | // determine the UART to use
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| 172 | uint32_t uart_tx = pinmap_peripheral(tx, PinMap_UART_TX);
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| 173 | uint32_t uart_rx = pinmap_peripheral(rx, PinMap_UART_RX);
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| 174 | uint32_t uart = pinmap_merge(uart_tx, uart_rx);
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| 175 |
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| 176 | MBED_ASSERT((int)uart != NC);
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| 177 |
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| 178 | obj->uart = (struct st_scif *)SCIF[uart];
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| 179 | // enable power
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| 180 | switch (uart) {
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| 181 | case UART0:
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| 182 | CPG.STBCR4 &= ~(1 << 7);
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| 183 | break;
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| 184 | case UART1:
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| 185 | CPG.STBCR4 &= ~(1 << 6);
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| 186 | break;
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| 187 | case UART2:
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| 188 | CPG.STBCR4 &= ~(1 << 5);
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| 189 | break;
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| 190 | case UART3:
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| 191 | CPG.STBCR4 &= ~(1 << 4);
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| 192 | break;
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| 193 | case UART4:
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| 194 | CPG.STBCR4 &= ~(1 << 3);
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| 195 | break;
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| 196 | case UART5:
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| 197 | CPG.STBCR4 &= ~(1 << 2);
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| 198 | break;
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| 199 | case UART6:
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| 200 | CPG.STBCR4 &= ~(1 << 1);
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| 201 | break;
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| 202 | case UART7:
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| 203 | CPG.STBCR4 &= ~(1 << 0);
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| 204 | break;
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| 205 | }
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| 206 | dummy = CPG.STBCR4;
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| 207 |
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| 208 | /* ==== SCIF initial setting ==== */
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| 209 | /* ---- Serial control register (SCSCR) setting ---- */
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| 210 | /* B'00 : Internal CLK */
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| 211 | obj->uart->SCSCR = 0x0000u; /* SCIF transmitting and receiving operations stop */
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| 212 |
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| 213 | /* ---- FIFO control register (SCFCR) setting ---- */
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| 214 | /* Transmit FIFO reset & Receive FIFO data register reset */
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| 215 | obj->uart->SCFCR = 0x0006;
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| 216 |
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| 217 | /* ---- Serial status register (SCFSR) setting ---- */
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| 218 | dummy = obj->uart->SCFSR;
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| 219 | obj->uart->SCFSR = (dummy & 0xFF6Cu); /* ER,BRK,DR bit clear */
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| 220 |
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| 221 | /* ---- Line status register (SCLSR) setting ---- */
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| 222 | /* ORER bit clear */
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| 223 | obj->uart->SCLSR = 0;
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| 224 |
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| 225 | /* ---- Serial extension mode register (SCEMR) setting ----
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| 226 | b7 BGDM - Baud rate generator double-speed mode : Normal mode
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| 227 | b0 ABCS - Base clock select in asynchronous mode : Base clock is 16 times the bit rate */
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| 228 | obj->uart->SCEMR = 0x0000u;
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| 229 |
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| 230 | /* ---- Bit rate register (SCBRR) setting ---- */
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| 231 | serial_baud (obj, 9600);
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| 232 | serial_format(obj, 8, ParityNone, 1);
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| 233 |
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| 234 | /* ---- FIFO control register (SCFCR) setting ---- */
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| 235 | obj->uart->SCFCR = 0x0030u;
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| 236 |
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| 237 | /* ---- Serial port register (SCSPTR) setting ----
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| 238 | b1 SPB2IO - Serial port break output : disabled
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| 239 | b0 SPB2DT - Serial port break data : High-level */
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| 240 | obj->uart->SCSPTR = 0x0003u; // SPB2IO = 1, SPB2DT = 1
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| 241 |
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| 242 | /* ---- Line status register (SCLSR) setting ----
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| 243 | b0 ORER - Overrun error detect : clear */
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| 244 |
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| 245 | if (obj->uart->SCLSR & 0x0001) {
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| 246 | obj->uart->SCLSR = 0u; // ORER clear
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| 247 | }
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| 248 |
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| 249 | // pinout the chosen uart
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| 250 | pinmap_pinout(tx, PinMap_UART_TX);
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| 251 | pinmap_pinout(rx, PinMap_UART_RX);
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| 252 |
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| 253 | switch (uart) {
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| 254 | case UART0:
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| 255 | obj->index = 0;
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| 256 | break;
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| 257 | case UART1:
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| 258 | obj->index = 1;
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| 259 | break;
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| 260 | case UART2:
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| 261 | obj->index = 2;
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| 262 | break;
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| 263 | case UART3:
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| 264 | obj->index = 3;
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| 265 | break;
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| 266 | case UART4:
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| 267 | obj->index = 4;
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| 268 | break;
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| 269 | case UART5:
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| 270 | obj->index = 5;
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| 271 | break;
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| 272 | case UART6:
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| 273 | obj->index = 6;
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| 274 | break;
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| 275 | case UART7:
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| 276 | obj->index = 7;
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| 277 | break;
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| 278 | }
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| 279 | uart_data[obj->index].sw_rts.pin = NC;
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| 280 | uart_data[obj->index].sw_cts.pin = NC;
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| 281 |
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| 282 | /* ---- Serial control register (SCSCR) setting ---- */
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| 283 | /* Setting the TE and RE bits enables the TxD and RxD pins to be used. */
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| 284 | obj->uart->SCSCR = 0x00F0;
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| 285 |
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| 286 | is_stdio_uart = (uart == STDIO_UART) ? (1) : (0);
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| 287 |
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| 288 | if (is_stdio_uart) {
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| 289 | stdio_uart_inited = 1;
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| 290 | memcpy(&stdio_uart, obj, sizeof(serial_t));
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| 291 | }
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| 292 | }
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| 293 |
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| 294 | void serial_free(serial_t *obj) {
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| 295 | uart_data[obj->index].serial_irq_id = 0;
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| 296 | }
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| 297 |
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| 298 | // serial_baud
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| 299 | // set the baud rate, taking in to account the current SystemFrequency
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| 300 | void serial_baud(serial_t *obj, int baudrate) {
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| 301 | uint16_t DL;
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| 302 |
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| 303 | obj->uart->SCSMR &= ~0x0003;
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| 304 |
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| 305 | if (baudrate > 32552) {
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| 306 | obj->uart->SCEMR = 0x0081; // BGDM = 1, ABCS = 1
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| 307 | DL = PCLK / (8 * baudrate);
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| 308 | if (DL > 0) {
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| 309 | DL--;
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| 310 | }
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| 311 | obj->uart->SCBRR = (uint8_t)DL;
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| 312 | } else if (baudrate > 16276) {
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| 313 | obj->uart->SCEMR = 0x0080; // BGDM = 1
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| 314 | obj->uart->SCBRR = PCLK / (16 * baudrate) - 1;
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| 315 | } else if (baudrate > 8138) {
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| 316 | obj->uart->SCEMR = 0x0000;
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| 317 | obj->uart->SCBRR = PCLK / (32 * baudrate) - 1;
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| 318 | } else if (baudrate > 4169) {
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| 319 | obj->uart->SCSMR |= 0x0001;
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| 320 | obj->uart->SCEMR = 0x0080; // BGDM = 1
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| 321 | obj->uart->SCBRR = PCLK / (64 * baudrate) - 1;
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| 322 | } else if (baudrate > 2034) {
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| 323 | obj->uart->SCSMR |= 0x0001;
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| 324 | obj->uart->SCEMR = 0x0000;
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| 325 | obj->uart->SCBRR = PCLK / (128 * baudrate) - 1;
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| 326 | } else if (baudrate > 1017) {
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| 327 | obj->uart->SCSMR |= 0x0002;
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| 328 | obj->uart->SCEMR = 0x0080; // BGDM = 1
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| 329 | obj->uart->SCBRR = PCLK / (256 * baudrate) - 1;
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| 330 | } else if (baudrate > 508) {
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| 331 | obj->uart->SCSMR |= 0x0002;
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| 332 | obj->uart->SCEMR = 0x0000;
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| 333 | obj->uart->SCBRR = PCLK / (512 * baudrate) - 1;
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| 334 | } else if (baudrate > 254) {
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| 335 | obj->uart->SCSMR |= 0x0003;
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| 336 | obj->uart->SCEMR = 0x0080; // BGDM = 1
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| 337 | obj->uart->SCBRR = PCLK / (1024 * baudrate) - 1;
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| 338 | } else if (baudrate > 127) {
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| 339 | obj->uart->SCSMR |= 0x0003;
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| 340 | obj->uart->SCEMR = 0x0000;
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| 341 | obj->uart->SCBRR = PCLK / (2048 * baudrate) - 1;
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| 342 | } else {
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| 343 | obj->uart->SCSMR |= 0x0003;
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| 344 | obj->uart->SCEMR = 0x0000;
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| 345 | obj->uart->SCBRR = 0xFFu;
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| 346 | }
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| 347 | }
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| 348 |
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| 349 | void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
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| 350 | int parity_enable;
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| 351 | int parity_select;
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| 352 |
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| 353 | MBED_ASSERT((stop_bits == 1) || (stop_bits == 2)); // 0: 1 stop bits, 1: 2 stop bits
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| 354 | MBED_ASSERT((data_bits > 4) && (data_bits < 9)); // 5: 5 data bits ... 3: 8 data bits
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| 355 | MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || (parity == ParityEven) ||
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| 356 | (parity == ParityForced1) || (parity == ParityForced0));
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| 357 |
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| 358 | stop_bits = (stop_bits == 1)? 0:
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| 359 | (stop_bits == 2)? 1:
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| 360 | 0; // must not to be
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| 361 |
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| 362 | data_bits = (data_bits == 8)? 0:
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| 363 | (data_bits == 7)? 1:
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| 364 | 0; // must not to be
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| 365 |
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| 366 | switch (parity) {
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| 367 | case ParityNone:
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| 368 | parity_enable = 0;
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| 369 | parity_select = 0;
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| 370 | break;
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| 371 | case ParityOdd:
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| 372 | parity_enable = 1;
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| 373 | parity_select = 1;
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| 374 | break;
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| 375 | case ParityEven:
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| 376 | parity_enable = 1;
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| 377 | parity_select = 0;
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| 378 | break;
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| 379 | case ParityForced1:
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| 380 | case ParityForced0:
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| 381 | default:
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| 382 | parity_enable = 0;
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| 383 | parity_select = 0;
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| 384 | break;
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| 385 | }
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| 386 |
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| 387 | obj->uart->SCSMR = data_bits << 6
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| 388 | | parity_enable << 5
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| 389 | | parity_select << 4
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| 390 | | stop_bits << 3;
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| 391 | }
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| 392 |
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| 393 | /******************************************************************************
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| 394 | * INTERRUPTS HANDLING
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| 395 | ******************************************************************************/
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| 396 |
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| 397 | static void uart_tx_irq(IRQn_Type irq_num, uint32_t index) {
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| 398 | __IO uint16_t *dmy_rd_scscr;
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| 399 | __IO uint16_t *dmy_rd_scfsr;
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| 400 |
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| 401 | dmy_rd_scscr = SCSCR_MATCH[index];
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| 402 | *dmy_rd_scscr &= 0x007B; // Clear TIE and Write to bit15~8,2 is always 0
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| 403 | dmy_rd_scfsr = SCFSR_MATCH[index];
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| 404 | *dmy_rd_scfsr = (*dmy_rd_scfsr & ~0x0020); // Clear TDFE
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| 405 |
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| 406 | irq_handler(uart_data[index].serial_irq_id, TxIrq);
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| 407 | }
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| 408 |
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| 409 | static void uart_rx_irq(IRQn_Type irq_num, uint32_t index) {
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| 410 | __IO uint16_t *dmy_rd_scscr;
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| 411 | __IO uint16_t *dmy_rd_scfsr;
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| 412 |
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| 413 | dmy_rd_scscr = SCSCR_MATCH[index];
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| 414 | *dmy_rd_scscr &= 0x00B3; // Clear RIE,REIE and Write to bit15~8,2 is always 0
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| 415 | dmy_rd_scfsr = SCFSR_MATCH[index];
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| 416 | *dmy_rd_scfsr = (*dmy_rd_scfsr & ~0x0003); // Clear RDF,DR
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| 417 |
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| 418 | irq_handler(uart_data[index].serial_irq_id, RxIrq);
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| 419 | }
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| 420 |
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| 421 | /* TX handler */
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| 422 | static void uart0_tx_irq(void) {
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| 423 | uart_tx_irq(SCIFTXI0_IRQn, 0);
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| 424 | }
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| 425 | static void uart1_tx_irq(void) {
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| 426 | uart_tx_irq(SCIFTXI1_IRQn, 1);
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| 427 | }
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| 428 | static void uart2_tx_irq(void) {
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| 429 | uart_tx_irq(SCIFTXI2_IRQn, 2);
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| 430 | }
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| 431 | static void uart3_tx_irq(void) {
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| 432 | uart_tx_irq(SCIFTXI3_IRQn, 3);
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| 433 | }
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| 434 | static void uart4_tx_irq(void) {
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| 435 | uart_tx_irq(SCIFTXI4_IRQn, 4);
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| 436 | }
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| 437 | static void uart5_tx_irq(void) {
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| 438 | uart_tx_irq(SCIFTXI5_IRQn, 5);
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| 439 | }
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| 440 | static void uart6_tx_irq(void) {
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| 441 | uart_tx_irq(SCIFTXI6_IRQn, 6);
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| 442 | }
|
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| 443 | static void uart7_tx_irq(void) {
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| 444 | uart_tx_irq(SCIFTXI7_IRQn, 7);
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| 445 | }
|
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| 446 | /* RX handler */
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| 447 | static void uart0_rx_irq(void) {
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| 448 | uart_rx_irq(SCIFRXI0_IRQn, 0);
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| 449 | }
|
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| 450 | static void uart1_rx_irq(void) {
|
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| 451 | uart_rx_irq(SCIFRXI1_IRQn, 1);
|
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| 452 | }
|
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| 453 | static void uart2_rx_irq(void) {
|
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| 454 | uart_rx_irq(SCIFRXI2_IRQn, 2);
|
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| 455 | }
|
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| 456 | static void uart3_rx_irq(void) {
|
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| 457 | uart_rx_irq(SCIFRXI3_IRQn, 3);
|
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| 458 | }
|
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| 459 | static void uart4_rx_irq(void) {
|
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| 460 | uart_rx_irq(SCIFRXI4_IRQn, 4);
|
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| 461 | }
|
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| 462 | static void uart5_rx_irq(void) {
|
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| 463 | uart_rx_irq(SCIFRXI5_IRQn, 5);
|
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| 464 | }
|
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| 465 | static void uart6_rx_irq(void) {
|
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| 466 | uart_rx_irq(SCIFRXI6_IRQn, 6);
|
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| 467 | }
|
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| 468 | static void uart7_rx_irq(void) {
|
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| 469 | uart_rx_irq(SCIFRXI7_IRQn, 7);
|
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| 470 | }
|
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| 471 |
|
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| 472 | void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) {
|
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| 473 | irq_handler = handler;
|
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| 474 | uart_data[obj->index].serial_irq_id = id;
|
---|
| 475 | }
|
---|
| 476 |
|
---|
| 477 | static void serial_irq_set_internal(serial_t *obj, SerialIrq irq, uint32_t enable) {
|
---|
| 478 | IRQn_Type IRQn;
|
---|
| 479 | IRQHandler handler;
|
---|
| 480 |
|
---|
| 481 | IRQn = irq_set_tbl[obj->index][irq];
|
---|
| 482 | handler = hander_set_tbl[obj->index][irq];
|
---|
| 483 |
|
---|
| 484 | if ((obj->index >= 0) && (obj->index <= 7)) {
|
---|
| 485 | if (enable) {
|
---|
| 486 | InterruptHandlerRegister(IRQn, (void (*)(uint32_t))handler);
|
---|
| 487 | GIC_SetPriority(IRQn, 5);
|
---|
| 488 | GIC_EnableIRQ(IRQn);
|
---|
| 489 | } else {
|
---|
| 490 | GIC_DisableIRQ(IRQn);
|
---|
| 491 | }
|
---|
| 492 | }
|
---|
| 493 | }
|
---|
| 494 |
|
---|
| 495 | void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) {
|
---|
| 496 | if (RxIrq == irq) {
|
---|
| 497 | uart_data[obj->index].rx_irq_set_api = enable;
|
---|
| 498 | }
|
---|
| 499 | serial_irq_set_internal(obj, irq, enable);
|
---|
| 500 | }
|
---|
| 501 |
|
---|
| 502 | static void serial_flow_irq_set(serial_t *obj, uint32_t enable) {
|
---|
| 503 | uart_data[obj->index].rx_irq_set_flow = enable;
|
---|
| 504 | serial_irq_set_internal(obj, RxIrq, enable);
|
---|
| 505 | }
|
---|
| 506 |
|
---|
| 507 | /******************************************************************************
|
---|
| 508 | * READ/WRITE
|
---|
| 509 | ******************************************************************************/
|
---|
| 510 | int serial_getc(serial_t *obj) {
|
---|
| 511 | uint16_t err_read;
|
---|
| 512 | int data;
|
---|
| 513 | int was_masked;
|
---|
| 514 |
|
---|
| 515 | was_masked = __disable_irq();
|
---|
| 516 | if (obj->uart->SCFSR & 0x93) {
|
---|
| 517 | err_read = obj->uart->SCFSR;
|
---|
| 518 | obj->uart->SCFSR = (err_read & ~0x93);
|
---|
| 519 | }
|
---|
| 520 | obj->uart->SCSCR |= 0x0040; // Set RIE
|
---|
| 521 | if (!was_masked) {
|
---|
| 522 | __enable_irq();
|
---|
| 523 | }
|
---|
| 524 |
|
---|
| 525 | if (obj->uart->SCLSR & 0x0001) {
|
---|
| 526 | obj->uart->SCLSR = 0u; // ORER clear
|
---|
| 527 | }
|
---|
| 528 |
|
---|
| 529 | while (!serial_readable(obj));
|
---|
| 530 | data = obj->uart->SCFRDR & 0xff;
|
---|
| 531 |
|
---|
| 532 | was_masked = __disable_irq();
|
---|
| 533 | err_read = obj->uart->SCFSR;
|
---|
| 534 | obj->uart->SCFSR = (err_read & 0xfffD); // Clear RDF
|
---|
| 535 | if (!was_masked) {
|
---|
| 536 | __enable_irq();
|
---|
| 537 | }
|
---|
| 538 |
|
---|
| 539 | if (err_read & 0x80) {
|
---|
| 540 | data = -1; //err
|
---|
| 541 | }
|
---|
| 542 | return data;
|
---|
| 543 | }
|
---|
| 544 |
|
---|
| 545 | void serial_putc(serial_t *obj, int c) {
|
---|
| 546 | uint16_t dummy_read;
|
---|
| 547 | int was_masked;
|
---|
| 548 |
|
---|
| 549 | was_masked = __disable_irq();
|
---|
| 550 | obj->uart->SCSCR |= 0x0080; // Set TIE
|
---|
| 551 | if (!was_masked) {
|
---|
| 552 | __enable_irq();
|
---|
| 553 | }
|
---|
| 554 | while (!serial_writable(obj));
|
---|
| 555 | obj->uart->SCFTDR = c;
|
---|
| 556 | was_masked = __disable_irq();
|
---|
| 557 | dummy_read = obj->uart->SCFSR;
|
---|
| 558 | obj->uart->SCFSR = (dummy_read & 0xff9f); // Clear TEND/TDFE
|
---|
| 559 | if (!was_masked) {
|
---|
| 560 | __enable_irq();
|
---|
| 561 | }
|
---|
| 562 | uart_data[obj->index].count++;
|
---|
| 563 | }
|
---|
| 564 |
|
---|
| 565 | int serial_readable(serial_t *obj) {
|
---|
| 566 | return ((obj->uart->SCFSR & 0x02) != 0); // RDF
|
---|
| 567 | }
|
---|
| 568 |
|
---|
| 569 | int serial_writable(serial_t *obj) {
|
---|
| 570 | return ((obj->uart->SCFSR & 0x20) != 0); // TDFE
|
---|
| 571 | }
|
---|
| 572 |
|
---|
| 573 | void serial_clear(serial_t *obj) {
|
---|
| 574 | int was_masked;
|
---|
| 575 | was_masked = __disable_irq();
|
---|
| 576 |
|
---|
| 577 | obj->uart->SCFCR |= 0x06; // TFRST = 1, RFRST = 1
|
---|
| 578 | obj->uart->SCFCR &= ~0x06; // TFRST = 0, RFRST = 0
|
---|
| 579 | obj->uart->SCFSR &= ~0x0093u; // ER, BRK, RDF, DR = 0
|
---|
| 580 |
|
---|
| 581 | if (!was_masked) {
|
---|
| 582 | __enable_irq();
|
---|
| 583 | }
|
---|
| 584 | }
|
---|
| 585 |
|
---|
| 586 | void serial_pinout_tx(PinName tx) {
|
---|
| 587 | pinmap_pinout(tx, PinMap_UART_TX);
|
---|
| 588 | }
|
---|
| 589 |
|
---|
| 590 | void serial_break_set(serial_t *obj) {
|
---|
| 591 | int was_masked;
|
---|
| 592 | was_masked = __disable_irq();
|
---|
| 593 | // TxD Output(L)
|
---|
| 594 | obj->uart->SCSPTR &= ~0x0001u; // SPB2DT = 0
|
---|
| 595 | obj->uart->SCSCR &= ~0x0020u; // TE = 0 (Output disable)
|
---|
| 596 | if (!was_masked) {
|
---|
| 597 | __enable_irq();
|
---|
| 598 | }
|
---|
| 599 | }
|
---|
| 600 |
|
---|
| 601 | void serial_break_clear(serial_t *obj) {
|
---|
| 602 | int was_masked;
|
---|
| 603 | was_masked = __disable_irq();
|
---|
| 604 | obj->uart->SCSCR |= 0x0020u; // TE = 1 (Output enable)
|
---|
| 605 | obj->uart->SCSPTR |= 0x0001u; // SPB2DT = 1
|
---|
| 606 | if (!was_masked) {
|
---|
| 607 | __enable_irq();
|
---|
| 608 | }
|
---|
| 609 | }
|
---|
| 610 |
|
---|
| 611 | void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) {
|
---|
| 612 | // determine the UART to use
|
---|
| 613 | int was_masked;
|
---|
| 614 |
|
---|
| 615 | serial_flow_irq_set(obj, 0);
|
---|
| 616 |
|
---|
| 617 | if (type == FlowControlRTSCTS) {
|
---|
| 618 | was_masked = __disable_irq();
|
---|
| 619 | obj->uart->SCFCR = 0x0008u; // CTS/RTS enable
|
---|
| 620 | if (!was_masked) {
|
---|
| 621 | __enable_irq();
|
---|
| 622 | }
|
---|
| 623 | pinmap_pinout(rxflow, PinMap_UART_RTS);
|
---|
| 624 | pinmap_pinout(txflow, PinMap_UART_CTS);
|
---|
| 625 | } else {
|
---|
| 626 | was_masked = __disable_irq();
|
---|
| 627 | obj->uart->SCFCR = 0x0000u; // CTS/RTS diable
|
---|
| 628 | if (!was_masked) {
|
---|
| 629 | __enable_irq();
|
---|
| 630 | }
|
---|
| 631 | }
|
---|
| 632 | }
|
---|
| 633 |
|
---|
| 634 |
|
---|
| 635 |
|
---|
| 636 |
|
---|