source: EcnlProtoTool/trunk/asp3_dcre/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/i2c_api.c@ 270

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1/* mbed Microcontroller Library
2 * Copyright (c) 2006-2013 ARM Limited
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16#include "mbed_assert.h"
17#include "i2c_api.h"
18#include "cmsis.h"
19#include "pinmap.h"
20#include "r_typedefs.h"
21
22#include "riic_iodefine.h"
23#include "RZ_A1_Init.h"
24#include "MBRZA1H.h"
25
26volatile struct st_riic *RIIC[] = RIIC_ADDRESS_LIST;
27
28#define REG(N) \
29 RIIC[obj->i2c]->RIICn##N
30
31/* RIICnCR1 */
32#define CR1_RST (1 << 6)
33#define CR1_ICE (1 << 7)
34
35/* RIICnCR2 */
36#define CR2_ST (1 << 1)
37#define CR2_RS (1 << 2)
38#define CR2_SP (1 << 3)
39#define CR2_TRS (1 << 5)
40#define CR2_BBSY (1 << 7)
41
42/* RIICnMR3 */
43#define MR3_ACKBT (1 << 3)
44#define MR3_ACKWP (1 << 4)
45#define MR3_WAIT (1 << 6)
46
47/* RIICnSER */
48#define SER_SAR0E (1 << 0)
49
50/* RIICnSR1 */
51#define SR1_AAS0 (1 << 0)
52
53/* RIICnSR2 */
54#define SR2_START (1 << 2)
55#define SR2_STOP (1 << 3)
56#define SR2_NACKF (1 << 4)
57#define SR2_RDRF (1 << 5)
58#define SR2_TEND (1 << 6)
59#define SR2_TDRE (1 << 7)
60
61#define WAIT_TIMEOUT (3600000) /* Loop counter : Time-out is about 1s. By 3600000 loops, measured value is 969ms. */
62
63static const PinMap PinMap_I2C_SDA[] = {
64 {P1_1 , I2C_0, 1},
65 {P1_3 , I2C_1, 1},
66 {P1_7 , I2C_3, 1},
67 {NC , NC , 0}
68};
69
70static const PinMap PinMap_I2C_SCL[] = {
71 {P1_0 , I2C_0, 1},
72 {P1_2 , I2C_1, 1},
73 {P1_6 , I2C_3, 1},
74 {NC , NC, 0}
75};
76
77
78static inline int i2c_status(i2c_t *obj) {
79 return REG(SR2.UINT8[0]);
80}
81
82static void i2c_reg_reset(i2c_t *obj) {
83 /* full reset */
84 REG(CR1.UINT8[0]) &= ~CR1_ICE; // CR1.ICE off
85 REG(CR1.UINT8[0]) |= CR1_RST; // CR1.IICRST on
86 REG(CR1.UINT8[0]) |= CR1_ICE; // CR1.ICE on
87
88 REG(MR1.UINT8[0]) = 0x08; // P_phi /x 9bit (including Ack)
89 REG(SER.UINT8[0]) = 0x00; // no slave addr enabled
90
91 /* set frequency */
92 REG(MR1.UINT8[0]) |= obj->pclk_bit;
93 REG(BRL.UINT8[0]) = obj->width_low;
94 REG(BRH.UINT8[0]) = obj->width_hi;
95
96 REG(MR2.UINT8[0]) = 0x07;
97 REG(MR3.UINT8[0]) = 0x00;
98
99 REG(FER.UINT8[0]) = 0x72; // SCLE, NFE enabled, TMOT
100 REG(IER.UINT8[0]) = 0x00; // no interrupt
101
102 REG(CR1.UINT32) &= ~CR1_RST; // CR1.IICRST negate reset
103}
104
105static inline int i2c_wait_RDRF(i2c_t *obj) {
106 int timeout = 0;
107
108 /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */
109 while ((i2c_status(obj) & SR2_RDRF) == 0) {
110 timeout ++;
111 if (timeout >= WAIT_TIMEOUT) {
112 return -1;
113 }
114 }
115
116 return 0;
117}
118
119static int i2c_wait_TDRE(i2c_t *obj) {
120 int timeout = 0;
121
122 /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */
123 while ((i2c_status(obj) & SR2_TDRE) == 0) {
124 timeout ++;
125 if (timeout >= WAIT_TIMEOUT) {
126 return -1;
127 }
128 }
129
130 return 0;
131}
132
133static int i2c_wait_TEND(i2c_t *obj) {
134 int timeout = 0;
135
136 /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */
137 while ((i2c_status(obj) & SR2_TEND) == 0) {
138 timeout ++;
139 if (timeout >= WAIT_TIMEOUT) {
140 return -1;
141 }
142 }
143
144 return 0;
145}
146
147
148static int i2c_wait_START(i2c_t *obj) {
149 int timeout = 0;
150
151 /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */
152 while ((i2c_status(obj) & SR2_START) == 0) {
153 timeout ++;
154 if (timeout >= WAIT_TIMEOUT) {
155 return -1;
156 }
157 }
158
159 return 0;
160}
161
162static int i2c_wait_STOP(i2c_t *obj) {
163 int timeout = 0;
164
165 /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */
166 while ((i2c_status(obj) & SR2_STOP) == 0) {
167 timeout ++;
168 if (timeout >= WAIT_TIMEOUT) {
169 return -1;
170 }
171 }
172
173 return 0;
174}
175
176static int i2c_set_STOP(i2c_t *obj) {
177 /* SR2.STOP = 0 */
178 REG(SR2.UINT32) &= ~SR2_STOP;
179 /* Stop condition */
180 REG(CR2.UINT32) |= CR2_SP;
181
182 return 0;
183}
184
185static void i2c_set_SR2_NACKF_STOP(i2c_t *obj) {
186 /* SR2.NACKF = 0 */
187 REG(SR2.UINT32) &= ~SR2_NACKF;
188 /* SR2.STOP = 0 */
189 REG(SR2.UINT32) &= ~SR2_STOP;
190}
191
192static void i2c_set_MR3_NACK(i2c_t *obj) {
193 /* send a NOT ACK */
194 REG(MR3.UINT32) |= MR3_ACKWP;
195 REG(MR3.UINT32) |= MR3_ACKBT;
196 REG(MR3.UINT32) &= ~MR3_ACKWP;
197}
198
199static void i2c_set_MR3_ACK(i2c_t *obj) {
200 /* send a ACK */
201 REG(MR3.UINT32) |= MR3_ACKWP;
202 REG(MR3.UINT32) &= ~MR3_ACKBT;
203 REG(MR3.UINT32) &= ~MR3_ACKWP;
204}
205
206static inline void i2c_power_enable(i2c_t *obj) {
207 volatile uint8_t dummy;
208 switch ((int)obj->i2c) {
209 case I2C_0:
210 CPGSTBCR9 &= ~(0x80);
211 break;
212 case I2C_1:
213 CPGSTBCR9 &= ~(0x40);
214 break;
215 case I2C_2:
216 CPGSTBCR9 &= ~(0x20);
217 break;
218 case I2C_3:
219 CPGSTBCR9 &= ~(0x10);
220 break;
221 }
222 dummy = CPGSTBCR9;
223}
224
225void i2c_init(i2c_t *obj, PinName sda, PinName scl) {
226 /* determine the I2C to use */
227 I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
228 I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
229 obj->i2c = pinmap_merge(i2c_sda, i2c_scl);
230 MBED_ASSERT((int)obj->i2c != NC);
231
232 /* enable power */
233 i2c_power_enable(obj);
234
235 /* set default frequency at 100k */
236 i2c_frequency(obj, 100000);
237
238 pinmap_pinout(sda, PinMap_I2C_SDA);
239 pinmap_pinout(scl, PinMap_I2C_SCL);
240
241 obj->last_stop_flag = 1;
242}
243
244inline int i2c_start(i2c_t *obj) {
245 int timeout = 0;
246
247 while ((REG(CR2.UINT32) & CR2_BBSY) != 0) {
248 timeout ++;
249 if (timeout >= obj->bbsy_wait_cnt) {
250 break;
251 }
252 }
253 /* Start Condition */
254 REG(CR2.UINT8[0]) |= CR2_ST;
255
256 return 0;
257}
258
259static inline int i2c_restart(i2c_t *obj) {
260 /* SR2.START = 0 */
261 REG(SR2.UINT32) &= ~SR2_START;
262 /* ReStart condition */
263 REG(CR2.UINT32) |= CR2_RS;
264
265 return 0;
266}
267
268inline int i2c_stop(i2c_t *obj) {
269 (void)i2c_set_STOP(obj);
270 (void)i2c_wait_STOP(obj);
271 i2c_set_SR2_NACKF_STOP(obj);
272
273 return 0;
274}
275
276static void i2c_set_err_noslave(i2c_t *obj) {
277 (void)i2c_set_STOP(obj);
278 (void)i2c_wait_STOP(obj);
279 i2c_set_SR2_NACKF_STOP(obj);
280 obj->last_stop_flag = 1;
281}
282
283static inline int i2c_do_write(i2c_t *obj, int value) {
284 int timeout = 0;
285
286 /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */
287 while ((i2c_status(obj) & SR2_TDRE) == 0) {
288 timeout ++;
289 if (timeout >= WAIT_TIMEOUT) {
290 return -1;
291 }
292 }
293 /* write the data */
294 REG(DRT.UINT32) = value;
295
296 return 0;
297}
298
299static inline int i2c_read_address_write(i2c_t *obj, int value) {
300 int status;
301
302 status = i2c_wait_TDRE(obj);
303 if (status == 0) {
304 /* write the data */
305 REG(DRT.UINT32) = value;
306 }
307
308 return status;
309
310}
311
312static inline int i2c_do_read(i2c_t *obj, int last) {
313 if (last == 2) {
314 /* this time is befor last byte read */
315 /* Set MR3 WAIT bit is 1 */;
316 REG(MR3.UINT32) |= MR3_WAIT;
317 } else if (last == 1) {
318 i2c_set_MR3_NACK(obj);
319 } else {
320 i2c_set_MR3_ACK(obj);
321 }
322
323 /* return the data */
324 return (REG(DRR.UINT32) & 0xFF);
325}
326
327void i2c_frequency(i2c_t *obj, int hz) {
328 float64_t pclk_val;
329 float64_t wait_utime;
330 volatile float64_t bps;
331 volatile float64_t L_time; /* H Width period */
332 volatile float64_t H_time; /* L Width period */
333 uint32_t tmp_L_width;
334 uint32_t tmp_H_width;
335 uint32_t remainder;
336 uint32_t wk_cks = 0;
337
338 /* set PCLK */
339 if (false == RZ_A1_IsClockMode0()) {
340 pclk_val = (float64_t)CM1_RENESAS_RZ_A1_P0_CLK;
341 } else {
342 pclk_val = (float64_t)CM0_RENESAS_RZ_A1_P0_CLK;
343 }
344
345 /* Min 10kHz, Max 400kHz */
346 if (hz < 10000) {
347 bps = 10000;
348 } else if (hz > 400000) {
349 bps = 400000;
350 } else {
351 bps = (float64_t)hz;
352 }
353
354 /* Calculation L width time */
355 L_time = (1 / (2 * bps)); /* Harf period of frequency */
356 H_time = L_time;
357
358 /* Check I2C mode of Speed */
359 if (bps > 100000) {
360 /* Fast-mode */
361 L_time -= 102E-9; /* Falling time of SCL clock. */
362 H_time -= 138E-9; /* Rising time of SCL clock. */
363 /* Check L wideth */
364 if (L_time < 1.3E-6) {
365 /* Wnen L width less than 1.3us */
366 /* Subtract Rise up and down time for SCL from H/L width */
367 L_time = 1.3E-6;
368 H_time = (1 / bps) - L_time - 138E-9 - 102E-9;
369 }
370 }
371
372 tmp_L_width = (uint32_t)(L_time * pclk_val * 10);
373 tmp_L_width >>= 1;
374 wk_cks++;
375 while (tmp_L_width >= 341) {
376 tmp_L_width >>= 1;
377 wk_cks++;
378 }
379 remainder = tmp_L_width % 10;
380 tmp_L_width = ((tmp_L_width + 9) / 10) - 3; /* carry */
381
382 tmp_H_width = (uint32_t)(H_time * pclk_val * 10);
383 tmp_H_width >>= wk_cks;
384 if (remainder == 0) {
385 tmp_H_width = ((tmp_H_width + 9) / 10) - 3; /* carry */
386 } else {
387 remainder += tmp_H_width % 10;
388 tmp_H_width = (tmp_H_width / 10) - 3;
389 if (remainder > 10) {
390 tmp_H_width += 1; /* fine adjustment */
391 }
392 }
393 /* timeout of BBSY bit is minimum low width by frequency */
394 /* so timeout calculates "(low width) * 2" by frequency */
395 wait_utime = (L_time * 2) * 1000000;
396 /* 1 wait of BBSY bit is about 0.3us. if it's below 0.3us, wait count is set as 1. */
397 if (wait_utime <= 0.3) {
398 obj->bbsy_wait_cnt = 1;
399 } else {
400 obj->bbsy_wait_cnt = (int)(wait_utime / 0.3);
401 }
402
403
404 /* I2C Rate */
405 obj->pclk_bit = (uint8_t)(0x10 * wk_cks); /* P_phi / xx */
406 obj->width_low = (uint8_t)(tmp_L_width | 0x000000E0);
407 obj->width_hi = (uint8_t)(tmp_H_width | 0x000000E0);
408
409 /* full reset */
410 i2c_reg_reset(obj);
411}
412
413int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
414 int count = 0;
415 int status;
416 int value;
417 volatile uint32_t work_reg = 0;
418
419 if(length <= 0) {
420 return 0;
421 }
422 i2c_set_MR3_ACK(obj);
423 /* There is a STOP condition for last processing */
424 if (obj->last_stop_flag != 0) {
425 status = i2c_start(obj);
426 if (status != 0) {
427 i2c_set_err_noslave(obj);
428 return I2C_ERROR_BUS_BUSY;
429 }
430 }
431 obj->last_stop_flag = stop;
432 /* Send Slave address */
433 status = i2c_read_address_write(obj, (address | 0x01));
434 if (status != 0) {
435 i2c_set_err_noslave(obj);
436 return I2C_ERROR_NO_SLAVE;
437 }
438 /* wait RDRF */
439 status = i2c_wait_RDRF(obj);
440 /* check ACK/NACK */
441 if ((status != 0) || ((REG(SR2.UINT32) & SR2_NACKF) != 0)) {
442 /* Slave sends NACK */
443 (void)i2c_set_STOP(obj);
444 /* dummy read */
445 value = REG(DRR.UINT32);
446 (void)i2c_wait_STOP(obj);
447 i2c_set_SR2_NACKF_STOP(obj);
448 obj->last_stop_flag = 1;
449 return I2C_ERROR_NO_SLAVE;
450 }
451 /* Read in all except last byte */
452 if (length > 2) {
453 /* dummy read */
454 value = REG(DRR.UINT32);
455 for (count = 0; count < (length - 1); count++) {
456 /* wait for it to arrive */
457 status = i2c_wait_RDRF(obj);
458 if (status != 0) {
459 i2c_set_err_noslave(obj);
460 return I2C_ERROR_NO_SLAVE;
461 }
462 /* Recieve the data */
463 if (count == (length - 2)) {
464 value = i2c_do_read(obj, 1);
465 } else if ((length >= 3) && (count == (length - 3))) {
466 value = i2c_do_read(obj, 2);
467 } else {
468 value = i2c_do_read(obj, 0);
469 }
470 data[count] = (char)value;
471 }
472 } else if (length == 2) {
473 /* Set MR3 WATI bit is 1 */
474 REG(MR3.UINT32) |= MR3_WAIT;
475 /* dummy read */
476 value = REG(DRR.UINT32);
477 /* wait for it to arrive */
478 status = i2c_wait_RDRF(obj);
479 if (status != 0) {
480 i2c_set_err_noslave(obj);
481 return I2C_ERROR_NO_SLAVE;
482 }
483 i2c_set_MR3_NACK(obj);
484 data[count] = (char)REG(DRR.UINT32);
485 count++;
486 } else {
487 /* length == 1 */
488 /* Set MR3 WATI bit is 1 */;
489 REG(MR3.UINT32) |= MR3_WAIT;
490 i2c_set_MR3_NACK(obj);
491 /* dummy read */
492 value = REG(DRR.UINT32);
493 }
494 /* wait for it to arrive */
495 status = i2c_wait_RDRF(obj);
496 if (status != 0) {
497 i2c_set_err_noslave(obj);
498 return I2C_ERROR_NO_SLAVE;
499 }
500
501 /* If not repeated start, send stop. */
502 if (stop) {
503 (void)i2c_set_STOP(obj);
504 /* RIICnDRR read */
505 value = (REG(DRR.UINT32) & 0xFF);
506 data[count] = (char)value;
507 /* RIICnMR3.WAIT = 0 */
508 REG(MR3.UINT32) &= ~MR3_WAIT;
509 (void)i2c_wait_STOP(obj);
510 i2c_set_SR2_NACKF_STOP(obj);
511 } else {
512 (void)i2c_restart(obj);
513 /* RIICnDRR read */
514 value = (REG(DRR.UINT32) & 0xFF);
515 data[count] = (char)value;
516 /* RIICnMR3.WAIT = 0 */
517 REG(MR3.UINT32) &= ~MR3_WAIT;
518 (void)i2c_wait_START(obj);
519 /* SR2.START = 0 */
520 REG(SR2.UINT32) &= ~SR2_START;
521 }
522
523 return length;
524}
525
526int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) {
527 int cnt;
528 int status;
529
530 if(length <= 0) {
531 return 0;
532 }
533
534 /* There is a STOP condition for last processing */
535 if (obj->last_stop_flag != 0) {
536 status = i2c_start(obj);
537 if (status != 0) {
538 i2c_set_err_noslave(obj);
539 return I2C_ERROR_BUS_BUSY;
540 }
541 }
542 obj->last_stop_flag = stop;
543 /* Send Slave address */
544 status = i2c_do_write(obj, address);
545 if (status != 0) {
546 i2c_set_err_noslave(obj);
547 return I2C_ERROR_NO_SLAVE;
548 }
549 /* Wait send end */
550 status = i2c_wait_TEND(obj);
551 if ((status != 0) || ((REG(SR2.UINT32) & SR2_NACKF) != 0)) {
552 /* Slave sends NACK */
553 i2c_set_err_noslave(obj);
554 return I2C_ERROR_NO_SLAVE;
555 }
556 /* Send Write data */
557 for (cnt=0; cnt<length; cnt++) {
558 status = i2c_do_write(obj, data[cnt]);
559 if(status != 0) {
560 i2c_set_err_noslave(obj);
561 return cnt;
562 } else {
563 /* Wait send end */
564 status = i2c_wait_TEND(obj);
565 if ((status != 0) || ((REG(SR2.UINT32) & SR2_NACKF) != 0)) {
566 /* Slave sends NACK */
567 i2c_set_err_noslave(obj);
568 return I2C_ERROR_NO_SLAVE;
569 }
570 }
571 }
572 /* If not repeated start, send stop. */
573 if (stop) {
574 (void)i2c_set_STOP(obj);
575 (void)i2c_wait_STOP(obj);
576 i2c_set_SR2_NACKF_STOP(obj);
577 } else {
578 (void)i2c_restart(obj);
579 (void)i2c_wait_START(obj);
580 /* SR2.START = 0 */
581 REG(SR2.UINT32) &= ~SR2_START;
582
583 }
584
585 return length;
586}
587
588void i2c_reset(i2c_t *obj) {
589 (void)i2c_set_STOP(obj);
590 (void)i2c_wait_STOP(obj);
591 i2c_set_SR2_NACKF_STOP(obj);
592}
593
594int i2c_byte_read(i2c_t *obj, int last) {
595 int status;
596 int data;
597
598 data = i2c_do_read(obj, last);
599 /* wait for it to arrive */
600 status = i2c_wait_RDRF(obj);
601 if (status != 0) {
602 i2c_set_SR2_NACKF_STOP(obj);
603 return I2C_ERROR_NO_SLAVE;
604 }
605
606 return data;
607}
608
609int i2c_byte_write(i2c_t *obj, int data) {
610 int ack = 0;
611 int status;
612 int timeout = 0;
613
614 status = i2c_do_write(obj, (data & 0xFF));
615 if (status != 0) {
616 i2c_set_SR2_NACKF_STOP(obj);
617 } else {
618 while (((i2c_status(obj) & SR2_RDRF) == 0) && ((i2c_status(obj) & SR2_TEND) == 0)) {
619 timeout++;
620 if (timeout >= WAIT_TIMEOUT) {
621 return ack;
622 }
623 }
624 /* check ACK/NACK */
625 if ((REG(SR2.UINT32) & SR2_NACKF) != 0) {
626 /* NACK */
627 i2c_set_SR2_NACKF_STOP(obj);
628 } else {
629 ack = 1;
630 }
631 }
632
633 return ack;
634}
635
636void i2c_slave_mode(i2c_t *obj, int enable_slave) {
637 if (enable_slave != 0) {
638 REG(SER.UINT32) |= SER_SAR0E; // only slave addr 0 is enabled
639 } else {
640 REG(SER.UINT32) &= ~SER_SAR0E; // no slave addr enabled
641 }
642}
643
644int i2c_slave_receive(i2c_t *obj) {
645 int status;
646 int retval;
647
648 status = (REG(SR1.UINT8[0]) & SR1_AAS0);
649 status |= (REG(CR2.UINT8[0]) & CR2_TRS) >> 4;
650
651 switch(status) {
652 case 0x01:
653 /* the master is writing to this slave */
654 retval = 3;
655 break;
656 case 0x02:
657 /* the master is writing to all slave */
658 retval = 2;
659 break;
660 case 0x03:
661 /* the master has requested a read from this slave */
662 retval = 1;
663 break;
664 default :
665 /* no data */
666 retval = 0;
667 break;
668 }
669
670 return retval;
671}
672
673int i2c_slave_read(i2c_t *obj, char *data, int length) {
674 int timeout = 0;
675 int count;
676 int break_flg = 0;
677
678 if(length <= 0) {
679 return 0;
680 }
681 for (count = 0; ((count < (length + 1)) && (break_flg == 0)); count++) {
682 /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */
683 while (((i2c_status(obj) & SR2_STOP) != 0) || ((i2c_status(obj) & SR2_RDRF) == 0)) {
684 if ((i2c_status(obj) & SR2_STOP) != 0) {
685 break_flg = 1;
686 break;
687 }
688 timeout ++;
689 if (timeout >= WAIT_TIMEOUT) {
690 return -1;
691 }
692 }
693 if (break_flg == 0) {
694 if (count == 0) {
695 /* dummy read */
696 (void)REG(DRR.UINT32);
697 } else {
698 data[count - 1] = (char)(REG(DRR.UINT32) & 0xFF);
699 }
700 }
701 }
702 if (break_flg == 0) {
703 (void)i2c_wait_STOP(obj);
704 } else {
705 if ((i2c_status(obj) & SR2_RDRF) != 0) {
706 if (count <= 1) {
707 /* fail safe */
708 /* dummy read */
709 (void)REG(DRR.UINT32);
710 } else {
711 data[count - 2] = (char)(REG(DRR.UINT32) & 0xFF);
712 }
713 }
714 }
715 /* SR2.STOP = 0 */
716 REG(SR2.UINT32) &= ~SR2_STOP;
717
718 return (count - 1);
719}
720
721int i2c_slave_write(i2c_t *obj, const char *data, int length) {
722 int count = 0;
723 int status = 0;
724
725 if(length <= 0) {
726 return 0;
727 }
728
729 while ((count < length) && (status == 0)) {
730 status = i2c_do_write(obj, data[count]);
731 if(status == 0) {
732 /* Wait send end */
733 status = i2c_wait_TEND(obj);
734 if ((status != 0) || ((count < (length - 1)) && ((REG(SR2.UINT32) & SR2_NACKF) != 0))) {
735 /* NACK */
736 break;
737 }
738 }
739 count++;
740 }
741 /* dummy read */
742 (void)REG(DRR.UINT32);
743 (void)i2c_wait_STOP(obj);
744 i2c_set_SR2_NACKF_STOP(obj);
745
746 return count;
747}
748
749void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) {
750 REG(SAR0.UINT32) = (address & 0xfffffffe);
751}
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