1 | /* mbed Microcontroller Library
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2 | * Copyright (c) 2006-2013 ARM Limited
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3 | *
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4 | * Licensed under the Apache License, Version 2.0 (the "License");
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5 | * you may not use this file except in compliance with the License.
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6 | * You may obtain a copy of the License at
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7 | *
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8 | * http://www.apache.org/licenses/LICENSE-2.0
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9 | *
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10 | * Unless required by applicable law or agreed to in writing, software
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11 | * distributed under the License is distributed on an "AS IS" BASIS,
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12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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13 | * See the License for the specific language governing permissions and
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14 | * limitations under the License.
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15 | */
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16 | #include "mbed_assert.h"
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17 | #include "i2c_api.h"
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18 | #include "cmsis.h"
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19 | #include "pinmap.h"
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20 | #include "r_typedefs.h"
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21 |
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22 | #include "riic_iodefine.h"
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23 | #include "RZ_A1_Init.h"
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24 | #include "MBRZA1H.h"
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25 |
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26 | volatile struct st_riic *RIIC[] = RIIC_ADDRESS_LIST;
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27 |
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28 | #define REG(N) \
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29 | RIIC[obj->i2c]->RIICn##N
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30 |
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31 | /* RIICnCR1 */
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32 | #define CR1_RST (1 << 6)
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33 | #define CR1_ICE (1 << 7)
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34 |
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35 | /* RIICnCR2 */
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36 | #define CR2_ST (1 << 1)
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37 | #define CR2_RS (1 << 2)
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38 | #define CR2_SP (1 << 3)
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39 | #define CR2_TRS (1 << 5)
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40 | #define CR2_BBSY (1 << 7)
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41 |
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42 | /* RIICnMR3 */
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43 | #define MR3_ACKBT (1 << 3)
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44 | #define MR3_ACKWP (1 << 4)
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45 | #define MR3_WAIT (1 << 6)
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46 |
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47 | /* RIICnSER */
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48 | #define SER_SAR0E (1 << 0)
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49 |
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50 | /* RIICnSR1 */
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51 | #define SR1_AAS0 (1 << 0)
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52 |
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53 | /* RIICnSR2 */
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54 | #define SR2_START (1 << 2)
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55 | #define SR2_STOP (1 << 3)
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56 | #define SR2_NACKF (1 << 4)
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57 | #define SR2_RDRF (1 << 5)
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58 | #define SR2_TEND (1 << 6)
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59 | #define SR2_TDRE (1 << 7)
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60 |
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61 | #define WAIT_TIMEOUT (3600000) /* Loop counter : Time-out is about 1s. By 3600000 loops, measured value is 969ms. */
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62 |
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63 | static const PinMap PinMap_I2C_SDA[] = {
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64 | {P1_1 , I2C_0, 1},
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65 | {P1_3 , I2C_1, 1},
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66 | {P1_7 , I2C_3, 1},
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67 | {NC , NC , 0}
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68 | };
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69 |
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70 | static const PinMap PinMap_I2C_SCL[] = {
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71 | {P1_0 , I2C_0, 1},
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72 | {P1_2 , I2C_1, 1},
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73 | {P1_6 , I2C_3, 1},
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74 | {NC , NC, 0}
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75 | };
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76 |
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77 |
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78 | static inline int i2c_status(i2c_t *obj) {
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79 | return REG(SR2.UINT8[0]);
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80 | }
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81 |
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82 | static void i2c_reg_reset(i2c_t *obj) {
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83 | /* full reset */
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84 | REG(CR1.UINT8[0]) &= ~CR1_ICE; // CR1.ICE off
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85 | REG(CR1.UINT8[0]) |= CR1_RST; // CR1.IICRST on
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86 | REG(CR1.UINT8[0]) |= CR1_ICE; // CR1.ICE on
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87 |
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88 | REG(MR1.UINT8[0]) = 0x08; // P_phi /x 9bit (including Ack)
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89 | REG(SER.UINT8[0]) = 0x00; // no slave addr enabled
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90 |
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91 | /* set frequency */
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92 | REG(MR1.UINT8[0]) |= obj->pclk_bit;
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93 | REG(BRL.UINT8[0]) = obj->width_low;
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94 | REG(BRH.UINT8[0]) = obj->width_hi;
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95 |
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96 | REG(MR2.UINT8[0]) = 0x07;
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97 | REG(MR3.UINT8[0]) = 0x00;
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98 |
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99 | REG(FER.UINT8[0]) = 0x72; // SCLE, NFE enabled, TMOT
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100 | REG(IER.UINT8[0]) = 0x00; // no interrupt
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101 |
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102 | REG(CR1.UINT32) &= ~CR1_RST; // CR1.IICRST negate reset
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103 | }
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104 |
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105 | static inline int i2c_wait_RDRF(i2c_t *obj) {
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106 | int timeout = 0;
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107 |
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108 | /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */
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109 | while ((i2c_status(obj) & SR2_RDRF) == 0) {
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110 | timeout ++;
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111 | if (timeout >= WAIT_TIMEOUT) {
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112 | return -1;
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113 | }
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114 | }
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115 |
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116 | return 0;
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117 | }
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118 |
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119 | static int i2c_wait_TDRE(i2c_t *obj) {
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120 | int timeout = 0;
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121 |
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122 | /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */
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123 | while ((i2c_status(obj) & SR2_TDRE) == 0) {
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124 | timeout ++;
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125 | if (timeout >= WAIT_TIMEOUT) {
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126 | return -1;
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127 | }
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128 | }
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129 |
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130 | return 0;
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131 | }
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132 |
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133 | static int i2c_wait_TEND(i2c_t *obj) {
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134 | int timeout = 0;
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135 |
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136 | /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */
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137 | while ((i2c_status(obj) & SR2_TEND) == 0) {
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138 | timeout ++;
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139 | if (timeout >= WAIT_TIMEOUT) {
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140 | return -1;
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141 | }
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142 | }
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143 |
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144 | return 0;
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145 | }
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146 |
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147 |
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148 | static int i2c_wait_START(i2c_t *obj) {
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149 | int timeout = 0;
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150 |
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151 | /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */
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152 | while ((i2c_status(obj) & SR2_START) == 0) {
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153 | timeout ++;
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154 | if (timeout >= WAIT_TIMEOUT) {
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155 | return -1;
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156 | }
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157 | }
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158 |
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159 | return 0;
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160 | }
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161 |
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162 | static int i2c_wait_STOP(i2c_t *obj) {
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163 | int timeout = 0;
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164 |
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165 | /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */
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166 | while ((i2c_status(obj) & SR2_STOP) == 0) {
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167 | timeout ++;
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168 | if (timeout >= WAIT_TIMEOUT) {
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169 | return -1;
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170 | }
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171 | }
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172 |
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173 | return 0;
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174 | }
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175 |
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176 | static int i2c_set_STOP(i2c_t *obj) {
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177 | /* SR2.STOP = 0 */
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178 | REG(SR2.UINT32) &= ~SR2_STOP;
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179 | /* Stop condition */
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180 | REG(CR2.UINT32) |= CR2_SP;
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181 |
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182 | return 0;
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183 | }
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184 |
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185 | static void i2c_set_SR2_NACKF_STOP(i2c_t *obj) {
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186 | /* SR2.NACKF = 0 */
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187 | REG(SR2.UINT32) &= ~SR2_NACKF;
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188 | /* SR2.STOP = 0 */
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189 | REG(SR2.UINT32) &= ~SR2_STOP;
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190 | }
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191 |
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192 | static void i2c_set_MR3_NACK(i2c_t *obj) {
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193 | /* send a NOT ACK */
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194 | REG(MR3.UINT32) |= MR3_ACKWP;
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195 | REG(MR3.UINT32) |= MR3_ACKBT;
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196 | REG(MR3.UINT32) &= ~MR3_ACKWP;
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197 | }
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198 |
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199 | static void i2c_set_MR3_ACK(i2c_t *obj) {
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200 | /* send a ACK */
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201 | REG(MR3.UINT32) |= MR3_ACKWP;
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202 | REG(MR3.UINT32) &= ~MR3_ACKBT;
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203 | REG(MR3.UINT32) &= ~MR3_ACKWP;
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204 | }
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205 |
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206 | static inline void i2c_power_enable(i2c_t *obj) {
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207 | volatile uint8_t dummy;
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208 | switch ((int)obj->i2c) {
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209 | case I2C_0:
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210 | CPGSTBCR9 &= ~(0x80);
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211 | break;
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212 | case I2C_1:
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213 | CPGSTBCR9 &= ~(0x40);
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214 | break;
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215 | case I2C_2:
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216 | CPGSTBCR9 &= ~(0x20);
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217 | break;
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218 | case I2C_3:
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219 | CPGSTBCR9 &= ~(0x10);
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220 | break;
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221 | }
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222 | dummy = CPGSTBCR9;
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223 | }
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224 |
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225 | void i2c_init(i2c_t *obj, PinName sda, PinName scl) {
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226 | /* determine the I2C to use */
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227 | I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
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228 | I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
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229 | obj->i2c = pinmap_merge(i2c_sda, i2c_scl);
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230 | MBED_ASSERT((int)obj->i2c != NC);
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231 |
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232 | /* enable power */
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233 | i2c_power_enable(obj);
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234 |
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235 | /* set default frequency at 100k */
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236 | i2c_frequency(obj, 100000);
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237 |
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238 | pinmap_pinout(sda, PinMap_I2C_SDA);
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239 | pinmap_pinout(scl, PinMap_I2C_SCL);
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240 |
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241 | obj->last_stop_flag = 1;
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242 | }
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243 |
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244 | inline int i2c_start(i2c_t *obj) {
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245 | int timeout = 0;
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246 |
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247 | while ((REG(CR2.UINT32) & CR2_BBSY) != 0) {
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248 | timeout ++;
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249 | if (timeout >= obj->bbsy_wait_cnt) {
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250 | break;
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251 | }
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252 | }
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253 | /* Start Condition */
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254 | REG(CR2.UINT8[0]) |= CR2_ST;
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255 |
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256 | return 0;
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257 | }
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258 |
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259 | static inline int i2c_restart(i2c_t *obj) {
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260 | /* SR2.START = 0 */
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261 | REG(SR2.UINT32) &= ~SR2_START;
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262 | /* ReStart condition */
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263 | REG(CR2.UINT32) |= CR2_RS;
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264 |
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265 | return 0;
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266 | }
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267 |
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268 | inline int i2c_stop(i2c_t *obj) {
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269 | (void)i2c_set_STOP(obj);
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270 | (void)i2c_wait_STOP(obj);
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271 | i2c_set_SR2_NACKF_STOP(obj);
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272 |
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273 | return 0;
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274 | }
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275 |
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276 | static void i2c_set_err_noslave(i2c_t *obj) {
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277 | (void)i2c_set_STOP(obj);
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278 | (void)i2c_wait_STOP(obj);
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279 | i2c_set_SR2_NACKF_STOP(obj);
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280 | obj->last_stop_flag = 1;
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281 | }
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282 |
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283 | static inline int i2c_do_write(i2c_t *obj, int value) {
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284 | int timeout = 0;
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285 |
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286 | /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */
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287 | while ((i2c_status(obj) & SR2_TDRE) == 0) {
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288 | timeout ++;
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289 | if (timeout >= WAIT_TIMEOUT) {
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290 | return -1;
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291 | }
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292 | }
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293 | /* write the data */
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294 | REG(DRT.UINT32) = value;
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295 |
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296 | return 0;
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297 | }
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298 |
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299 | static inline int i2c_read_address_write(i2c_t *obj, int value) {
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300 | int status;
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301 |
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302 | status = i2c_wait_TDRE(obj);
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303 | if (status == 0) {
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304 | /* write the data */
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305 | REG(DRT.UINT32) = value;
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306 | }
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307 |
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308 | return status;
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309 |
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310 | }
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311 |
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312 | static inline int i2c_do_read(i2c_t *obj, int last) {
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313 | if (last == 2) {
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314 | /* this time is befor last byte read */
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315 | /* Set MR3 WAIT bit is 1 */;
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316 | REG(MR3.UINT32) |= MR3_WAIT;
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317 | } else if (last == 1) {
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318 | i2c_set_MR3_NACK(obj);
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319 | } else {
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320 | i2c_set_MR3_ACK(obj);
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321 | }
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322 |
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323 | /* return the data */
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324 | return (REG(DRR.UINT32) & 0xFF);
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325 | }
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326 |
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327 | void i2c_frequency(i2c_t *obj, int hz) {
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328 | float64_t pclk_val;
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329 | float64_t wait_utime;
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330 | volatile float64_t bps;
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331 | volatile float64_t L_time; /* H Width period */
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332 | volatile float64_t H_time; /* L Width period */
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333 | uint32_t tmp_L_width;
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334 | uint32_t tmp_H_width;
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335 | uint32_t remainder;
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336 | uint32_t wk_cks = 0;
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337 |
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338 | /* set PCLK */
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339 | if (false == RZ_A1_IsClockMode0()) {
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340 | pclk_val = (float64_t)CM1_RENESAS_RZ_A1_P0_CLK;
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341 | } else {
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342 | pclk_val = (float64_t)CM0_RENESAS_RZ_A1_P0_CLK;
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343 | }
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344 |
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345 | /* Min 10kHz, Max 400kHz */
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346 | if (hz < 10000) {
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347 | bps = 10000;
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348 | } else if (hz > 400000) {
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349 | bps = 400000;
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350 | } else {
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351 | bps = (float64_t)hz;
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352 | }
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353 |
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354 | /* Calculation L width time */
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355 | L_time = (1 / (2 * bps)); /* Harf period of frequency */
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356 | H_time = L_time;
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357 |
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358 | /* Check I2C mode of Speed */
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359 | if (bps > 100000) {
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360 | /* Fast-mode */
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361 | L_time -= 102E-9; /* Falling time of SCL clock. */
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362 | H_time -= 138E-9; /* Rising time of SCL clock. */
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363 | /* Check L wideth */
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364 | if (L_time < 1.3E-6) {
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365 | /* Wnen L width less than 1.3us */
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366 | /* Subtract Rise up and down time for SCL from H/L width */
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367 | L_time = 1.3E-6;
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368 | H_time = (1 / bps) - L_time - 138E-9 - 102E-9;
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369 | }
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370 | }
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371 |
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372 | tmp_L_width = (uint32_t)(L_time * pclk_val * 10);
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373 | tmp_L_width >>= 1;
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374 | wk_cks++;
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375 | while (tmp_L_width >= 341) {
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376 | tmp_L_width >>= 1;
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377 | wk_cks++;
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378 | }
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379 | remainder = tmp_L_width % 10;
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380 | tmp_L_width = ((tmp_L_width + 9) / 10) - 3; /* carry */
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381 |
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382 | tmp_H_width = (uint32_t)(H_time * pclk_val * 10);
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383 | tmp_H_width >>= wk_cks;
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384 | if (remainder == 0) {
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385 | tmp_H_width = ((tmp_H_width + 9) / 10) - 3; /* carry */
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386 | } else {
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387 | remainder += tmp_H_width % 10;
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388 | tmp_H_width = (tmp_H_width / 10) - 3;
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389 | if (remainder > 10) {
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390 | tmp_H_width += 1; /* fine adjustment */
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391 | }
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392 | }
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393 | /* timeout of BBSY bit is minimum low width by frequency */
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394 | /* so timeout calculates "(low width) * 2" by frequency */
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395 | wait_utime = (L_time * 2) * 1000000;
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396 | /* 1 wait of BBSY bit is about 0.3us. if it's below 0.3us, wait count is set as 1. */
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397 | if (wait_utime <= 0.3) {
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398 | obj->bbsy_wait_cnt = 1;
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399 | } else {
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400 | obj->bbsy_wait_cnt = (int)(wait_utime / 0.3);
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401 | }
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402 |
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403 |
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404 | /* I2C Rate */
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405 | obj->pclk_bit = (uint8_t)(0x10 * wk_cks); /* P_phi / xx */
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406 | obj->width_low = (uint8_t)(tmp_L_width | 0x000000E0);
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407 | obj->width_hi = (uint8_t)(tmp_H_width | 0x000000E0);
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408 |
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409 | /* full reset */
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410 | i2c_reg_reset(obj);
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411 | }
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412 |
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413 | int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
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414 | int count = 0;
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415 | int status;
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416 | int value;
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417 | volatile uint32_t work_reg = 0;
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418 |
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419 | if(length <= 0) {
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420 | return 0;
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421 | }
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422 | i2c_set_MR3_ACK(obj);
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423 | /* There is a STOP condition for last processing */
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424 | if (obj->last_stop_flag != 0) {
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425 | status = i2c_start(obj);
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426 | if (status != 0) {
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427 | i2c_set_err_noslave(obj);
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428 | return I2C_ERROR_BUS_BUSY;
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429 | }
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430 | }
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431 | obj->last_stop_flag = stop;
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432 | /* Send Slave address */
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433 | status = i2c_read_address_write(obj, (address | 0x01));
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434 | if (status != 0) {
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435 | i2c_set_err_noslave(obj);
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436 | return I2C_ERROR_NO_SLAVE;
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437 | }
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438 | /* wait RDRF */
|
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439 | status = i2c_wait_RDRF(obj);
|
---|
440 | /* check ACK/NACK */
|
---|
441 | if ((status != 0) || ((REG(SR2.UINT32) & SR2_NACKF) != 0)) {
|
---|
442 | /* Slave sends NACK */
|
---|
443 | (void)i2c_set_STOP(obj);
|
---|
444 | /* dummy read */
|
---|
445 | value = REG(DRR.UINT32);
|
---|
446 | (void)i2c_wait_STOP(obj);
|
---|
447 | i2c_set_SR2_NACKF_STOP(obj);
|
---|
448 | obj->last_stop_flag = 1;
|
---|
449 | return I2C_ERROR_NO_SLAVE;
|
---|
450 | }
|
---|
451 | /* Read in all except last byte */
|
---|
452 | if (length > 2) {
|
---|
453 | /* dummy read */
|
---|
454 | value = REG(DRR.UINT32);
|
---|
455 | for (count = 0; count < (length - 1); count++) {
|
---|
456 | /* wait for it to arrive */
|
---|
457 | status = i2c_wait_RDRF(obj);
|
---|
458 | if (status != 0) {
|
---|
459 | i2c_set_err_noslave(obj);
|
---|
460 | return I2C_ERROR_NO_SLAVE;
|
---|
461 | }
|
---|
462 | /* Recieve the data */
|
---|
463 | if (count == (length - 2)) {
|
---|
464 | value = i2c_do_read(obj, 1);
|
---|
465 | } else if ((length >= 3) && (count == (length - 3))) {
|
---|
466 | value = i2c_do_read(obj, 2);
|
---|
467 | } else {
|
---|
468 | value = i2c_do_read(obj, 0);
|
---|
469 | }
|
---|
470 | data[count] = (char)value;
|
---|
471 | }
|
---|
472 | } else if (length == 2) {
|
---|
473 | /* Set MR3 WATI bit is 1 */
|
---|
474 | REG(MR3.UINT32) |= MR3_WAIT;
|
---|
475 | /* dummy read */
|
---|
476 | value = REG(DRR.UINT32);
|
---|
477 | /* wait for it to arrive */
|
---|
478 | status = i2c_wait_RDRF(obj);
|
---|
479 | if (status != 0) {
|
---|
480 | i2c_set_err_noslave(obj);
|
---|
481 | return I2C_ERROR_NO_SLAVE;
|
---|
482 | }
|
---|
483 | i2c_set_MR3_NACK(obj);
|
---|
484 | data[count] = (char)REG(DRR.UINT32);
|
---|
485 | count++;
|
---|
486 | } else {
|
---|
487 | /* length == 1 */
|
---|
488 | /* Set MR3 WATI bit is 1 */;
|
---|
489 | REG(MR3.UINT32) |= MR3_WAIT;
|
---|
490 | i2c_set_MR3_NACK(obj);
|
---|
491 | /* dummy read */
|
---|
492 | value = REG(DRR.UINT32);
|
---|
493 | }
|
---|
494 | /* wait for it to arrive */
|
---|
495 | status = i2c_wait_RDRF(obj);
|
---|
496 | if (status != 0) {
|
---|
497 | i2c_set_err_noslave(obj);
|
---|
498 | return I2C_ERROR_NO_SLAVE;
|
---|
499 | }
|
---|
500 |
|
---|
501 | /* If not repeated start, send stop. */
|
---|
502 | if (stop) {
|
---|
503 | (void)i2c_set_STOP(obj);
|
---|
504 | /* RIICnDRR read */
|
---|
505 | value = (REG(DRR.UINT32) & 0xFF);
|
---|
506 | data[count] = (char)value;
|
---|
507 | /* RIICnMR3.WAIT = 0 */
|
---|
508 | REG(MR3.UINT32) &= ~MR3_WAIT;
|
---|
509 | (void)i2c_wait_STOP(obj);
|
---|
510 | i2c_set_SR2_NACKF_STOP(obj);
|
---|
511 | } else {
|
---|
512 | (void)i2c_restart(obj);
|
---|
513 | /* RIICnDRR read */
|
---|
514 | value = (REG(DRR.UINT32) & 0xFF);
|
---|
515 | data[count] = (char)value;
|
---|
516 | /* RIICnMR3.WAIT = 0 */
|
---|
517 | REG(MR3.UINT32) &= ~MR3_WAIT;
|
---|
518 | (void)i2c_wait_START(obj);
|
---|
519 | /* SR2.START = 0 */
|
---|
520 | REG(SR2.UINT32) &= ~SR2_START;
|
---|
521 | }
|
---|
522 |
|
---|
523 | return length;
|
---|
524 | }
|
---|
525 |
|
---|
526 | int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) {
|
---|
527 | int cnt;
|
---|
528 | int status;
|
---|
529 |
|
---|
530 | if(length <= 0) {
|
---|
531 | return 0;
|
---|
532 | }
|
---|
533 |
|
---|
534 | /* There is a STOP condition for last processing */
|
---|
535 | if (obj->last_stop_flag != 0) {
|
---|
536 | status = i2c_start(obj);
|
---|
537 | if (status != 0) {
|
---|
538 | i2c_set_err_noslave(obj);
|
---|
539 | return I2C_ERROR_BUS_BUSY;
|
---|
540 | }
|
---|
541 | }
|
---|
542 | obj->last_stop_flag = stop;
|
---|
543 | /* Send Slave address */
|
---|
544 | status = i2c_do_write(obj, address);
|
---|
545 | if (status != 0) {
|
---|
546 | i2c_set_err_noslave(obj);
|
---|
547 | return I2C_ERROR_NO_SLAVE;
|
---|
548 | }
|
---|
549 | /* Wait send end */
|
---|
550 | status = i2c_wait_TEND(obj);
|
---|
551 | if ((status != 0) || ((REG(SR2.UINT32) & SR2_NACKF) != 0)) {
|
---|
552 | /* Slave sends NACK */
|
---|
553 | i2c_set_err_noslave(obj);
|
---|
554 | return I2C_ERROR_NO_SLAVE;
|
---|
555 | }
|
---|
556 | /* Send Write data */
|
---|
557 | for (cnt=0; cnt<length; cnt++) {
|
---|
558 | status = i2c_do_write(obj, data[cnt]);
|
---|
559 | if(status != 0) {
|
---|
560 | i2c_set_err_noslave(obj);
|
---|
561 | return cnt;
|
---|
562 | } else {
|
---|
563 | /* Wait send end */
|
---|
564 | status = i2c_wait_TEND(obj);
|
---|
565 | if ((status != 0) || ((REG(SR2.UINT32) & SR2_NACKF) != 0)) {
|
---|
566 | /* Slave sends NACK */
|
---|
567 | i2c_set_err_noslave(obj);
|
---|
568 | return I2C_ERROR_NO_SLAVE;
|
---|
569 | }
|
---|
570 | }
|
---|
571 | }
|
---|
572 | /* If not repeated start, send stop. */
|
---|
573 | if (stop) {
|
---|
574 | (void)i2c_set_STOP(obj);
|
---|
575 | (void)i2c_wait_STOP(obj);
|
---|
576 | i2c_set_SR2_NACKF_STOP(obj);
|
---|
577 | } else {
|
---|
578 | (void)i2c_restart(obj);
|
---|
579 | (void)i2c_wait_START(obj);
|
---|
580 | /* SR2.START = 0 */
|
---|
581 | REG(SR2.UINT32) &= ~SR2_START;
|
---|
582 |
|
---|
583 | }
|
---|
584 |
|
---|
585 | return length;
|
---|
586 | }
|
---|
587 |
|
---|
588 | void i2c_reset(i2c_t *obj) {
|
---|
589 | (void)i2c_set_STOP(obj);
|
---|
590 | (void)i2c_wait_STOP(obj);
|
---|
591 | i2c_set_SR2_NACKF_STOP(obj);
|
---|
592 | }
|
---|
593 |
|
---|
594 | int i2c_byte_read(i2c_t *obj, int last) {
|
---|
595 | int status;
|
---|
596 | int data;
|
---|
597 |
|
---|
598 | data = i2c_do_read(obj, last);
|
---|
599 | /* wait for it to arrive */
|
---|
600 | status = i2c_wait_RDRF(obj);
|
---|
601 | if (status != 0) {
|
---|
602 | i2c_set_SR2_NACKF_STOP(obj);
|
---|
603 | return I2C_ERROR_NO_SLAVE;
|
---|
604 | }
|
---|
605 |
|
---|
606 | return data;
|
---|
607 | }
|
---|
608 |
|
---|
609 | int i2c_byte_write(i2c_t *obj, int data) {
|
---|
610 | int ack = 0;
|
---|
611 | int status;
|
---|
612 | int timeout = 0;
|
---|
613 |
|
---|
614 | status = i2c_do_write(obj, (data & 0xFF));
|
---|
615 | if (status != 0) {
|
---|
616 | i2c_set_SR2_NACKF_STOP(obj);
|
---|
617 | } else {
|
---|
618 | while (((i2c_status(obj) & SR2_RDRF) == 0) && ((i2c_status(obj) & SR2_TEND) == 0)) {
|
---|
619 | timeout++;
|
---|
620 | if (timeout >= WAIT_TIMEOUT) {
|
---|
621 | return ack;
|
---|
622 | }
|
---|
623 | }
|
---|
624 | /* check ACK/NACK */
|
---|
625 | if ((REG(SR2.UINT32) & SR2_NACKF) != 0) {
|
---|
626 | /* NACK */
|
---|
627 | i2c_set_SR2_NACKF_STOP(obj);
|
---|
628 | } else {
|
---|
629 | ack = 1;
|
---|
630 | }
|
---|
631 | }
|
---|
632 |
|
---|
633 | return ack;
|
---|
634 | }
|
---|
635 |
|
---|
636 | void i2c_slave_mode(i2c_t *obj, int enable_slave) {
|
---|
637 | if (enable_slave != 0) {
|
---|
638 | REG(SER.UINT32) |= SER_SAR0E; // only slave addr 0 is enabled
|
---|
639 | } else {
|
---|
640 | REG(SER.UINT32) &= ~SER_SAR0E; // no slave addr enabled
|
---|
641 | }
|
---|
642 | }
|
---|
643 |
|
---|
644 | int i2c_slave_receive(i2c_t *obj) {
|
---|
645 | int status;
|
---|
646 | int retval;
|
---|
647 |
|
---|
648 | status = (REG(SR1.UINT8[0]) & SR1_AAS0);
|
---|
649 | status |= (REG(CR2.UINT8[0]) & CR2_TRS) >> 4;
|
---|
650 |
|
---|
651 | switch(status) {
|
---|
652 | case 0x01:
|
---|
653 | /* the master is writing to this slave */
|
---|
654 | retval = 3;
|
---|
655 | break;
|
---|
656 | case 0x02:
|
---|
657 | /* the master is writing to all slave */
|
---|
658 | retval = 2;
|
---|
659 | break;
|
---|
660 | case 0x03:
|
---|
661 | /* the master has requested a read from this slave */
|
---|
662 | retval = 1;
|
---|
663 | break;
|
---|
664 | default :
|
---|
665 | /* no data */
|
---|
666 | retval = 0;
|
---|
667 | break;
|
---|
668 | }
|
---|
669 |
|
---|
670 | return retval;
|
---|
671 | }
|
---|
672 |
|
---|
673 | int i2c_slave_read(i2c_t *obj, char *data, int length) {
|
---|
674 | int timeout = 0;
|
---|
675 | int count;
|
---|
676 | int break_flg = 0;
|
---|
677 |
|
---|
678 | if(length <= 0) {
|
---|
679 | return 0;
|
---|
680 | }
|
---|
681 | for (count = 0; ((count < (length + 1)) && (break_flg == 0)); count++) {
|
---|
682 | /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */
|
---|
683 | while (((i2c_status(obj) & SR2_STOP) != 0) || ((i2c_status(obj) & SR2_RDRF) == 0)) {
|
---|
684 | if ((i2c_status(obj) & SR2_STOP) != 0) {
|
---|
685 | break_flg = 1;
|
---|
686 | break;
|
---|
687 | }
|
---|
688 | timeout ++;
|
---|
689 | if (timeout >= WAIT_TIMEOUT) {
|
---|
690 | return -1;
|
---|
691 | }
|
---|
692 | }
|
---|
693 | if (break_flg == 0) {
|
---|
694 | if (count == 0) {
|
---|
695 | /* dummy read */
|
---|
696 | (void)REG(DRR.UINT32);
|
---|
697 | } else {
|
---|
698 | data[count - 1] = (char)(REG(DRR.UINT32) & 0xFF);
|
---|
699 | }
|
---|
700 | }
|
---|
701 | }
|
---|
702 | if (break_flg == 0) {
|
---|
703 | (void)i2c_wait_STOP(obj);
|
---|
704 | } else {
|
---|
705 | if ((i2c_status(obj) & SR2_RDRF) != 0) {
|
---|
706 | if (count <= 1) {
|
---|
707 | /* fail safe */
|
---|
708 | /* dummy read */
|
---|
709 | (void)REG(DRR.UINT32);
|
---|
710 | } else {
|
---|
711 | data[count - 2] = (char)(REG(DRR.UINT32) & 0xFF);
|
---|
712 | }
|
---|
713 | }
|
---|
714 | }
|
---|
715 | /* SR2.STOP = 0 */
|
---|
716 | REG(SR2.UINT32) &= ~SR2_STOP;
|
---|
717 |
|
---|
718 | return (count - 1);
|
---|
719 | }
|
---|
720 |
|
---|
721 | int i2c_slave_write(i2c_t *obj, const char *data, int length) {
|
---|
722 | int count = 0;
|
---|
723 | int status = 0;
|
---|
724 |
|
---|
725 | if(length <= 0) {
|
---|
726 | return 0;
|
---|
727 | }
|
---|
728 |
|
---|
729 | while ((count < length) && (status == 0)) {
|
---|
730 | status = i2c_do_write(obj, data[count]);
|
---|
731 | if(status == 0) {
|
---|
732 | /* Wait send end */
|
---|
733 | status = i2c_wait_TEND(obj);
|
---|
734 | if ((status != 0) || ((count < (length - 1)) && ((REG(SR2.UINT32) & SR2_NACKF) != 0))) {
|
---|
735 | /* NACK */
|
---|
736 | break;
|
---|
737 | }
|
---|
738 | }
|
---|
739 | count++;
|
---|
740 | }
|
---|
741 | /* dummy read */
|
---|
742 | (void)REG(DRR.UINT32);
|
---|
743 | (void)i2c_wait_STOP(obj);
|
---|
744 | i2c_set_SR2_NACKF_STOP(obj);
|
---|
745 |
|
---|
746 | return count;
|
---|
747 | }
|
---|
748 |
|
---|
749 | void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) {
|
---|
750 | REG(SAR0.UINT32) = (address & 0xfffffffe);
|
---|
751 | }
|
---|