source: EcnlProtoTool/trunk/asp3_dcre/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/ethernet_api.c@ 321

Last change on this file since 321 was 321, checked in by coas-nagasima, 7 years ago

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1/* mbed Microcontroller Library
2 * Copyright (c) 2006-2013 ARM Limited
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16#include <string.h>
17#include "ethernet_api.h"
18#include "cmsis.h"
19#include "mbed_interface.h"
20#include "toolchain.h"
21#include "mbed_error.h"
22#include "ether_iodefine.h"
23#include "ethernetext_api.h"
24
25/* Descriptor info */
26#define SIZE_OF_BUFFER (1600) /* Must be an integral multiple of 32 */
27#define MAX_SEND_SIZE (1514)
28/* Ethernet Descriptor Value Define */
29#define TD0_TFP_TOP_BOTTOM (0x30000000)
30#define TD0_TACT (0x80000000)
31#define TD0_TDLE (0x40000000)
32#define RD0_RACT (0x80000000)
33#define RD0_RDLE (0x40000000)
34#define RD0_RFE (0x08000000)
35#define RD0_RCSE (0x04000000)
36#define RD0_RFS (0x03FF0000)
37#define RD0_RCS (0x0000FFFF)
38#define RD0_RFS_RFOF (0x02000000)
39#define RD0_RFS_RUAF (0x00400000)
40#define RD0_RFS_RRF (0x00100000)
41#define RD0_RFS_RTLF (0x00080000)
42#define RD0_RFS_RTSF (0x00040000)
43#define RD0_RFS_PRE (0x00020000)
44#define RD0_RFS_CERF (0x00010000)
45#define RD0_RFS_ERROR (RD0_RFS_RFOF | RD0_RFS_RUAF | RD0_RFS_RRF | RD0_RFS_RTLF | \
46 RD0_RFS_RTSF | RD0_RFS_PRE | RD0_RFS_CERF)
47#define RD1_RDL_MSK (0x0000FFFF)
48/* PHY Register */
49#define BASIC_MODE_CONTROL_REG (0)
50#define BASIC_MODE_STATUS_REG (1)
51#define PHY_IDENTIFIER1_REG (2)
52#define PHY_IDENTIFIER2_REG (3)
53#define PHY_SP_CTL_STS_REG (31)
54/* MII management interface access */
55#define PHY_ADDR (0) /* Confirm the pin connection of the PHY-LSI */
56#define PHY_ST (1)
57#define PHY_WRITE (1)
58#define PHY_READ (2)
59#define MDC_WAIT (6) /* 400ns/4 */
60#define BASIC_STS_MSK_LINK (0x0004) /* Link Status */
61#define BASIC_STS_MSK_AUTO_CMP (0x0010) /* Auto-Negotiate Complete */
62#define M_PHY_ID (0xFFFFFFF0)
63#define PHY_ID_LAN8710A (0x0007C0F0)
64/* ETHERPIR0 */
65#define PIR0_MDI (0x00000008)
66#define PIR0_MDO (0x00000004)
67#define PIR0_MMD (0x00000002)
68#define PIR0_MDC (0x00000001)
69#define PIR0_MDC_HIGH (0x00000001)
70#define PIR0_MDC_LOW (0x00000000)
71/* ETHEREDRRR0 */
72#define EDRRR0_RR (0x00000001)
73/* ETHEREDTRR0 */
74#define EDTRR0_TR (0x00000003)
75/* software wait */
76#define LOOP_100us (6700) /* Loop counter for software wait 6666=100us/((1/400MHz)*6cyc) */
77
78#define EDMAC_EESIPR_INI_RECV (0x0205001F) /* 0x02000000 : Detect reception suspended */
79 /* 0x00040000 : Detect frame reception */
80 /* 0x00010000 : Receive FIFO overflow */
81 /* 0x00000010 : Residual bit frame reception */
82 /* 0x00000008 : Long frame reception */
83 /* 0x00000004 : Short frame reception */
84 /* 0x00000002 : PHY-LSI reception error */
85 /* 0x00000001 : Receive frame CRC error */
86#define EDMAC_EESIPR_INI_EtherC (0x00400000) /* 0x00400000 : E-MAC status register */
87
88/* Send descriptor */
89typedef struct tag_edmac_send_desc {
90 uint32_t td0;
91 uint32_t td1;
92 uint8_t *td2;
93 uint32_t padding4;
94} edmac_send_desc_t;
95
96/* Receive descriptor */
97typedef struct tag_edmac_recv_desc {
98 uint32_t rd0;
99 uint32_t rd1;
100 uint8_t *rd2;
101 uint32_t padding4;
102} edmac_recv_desc_t;
103
104/* memory */
105/* The whole transmit/receive descriptors (must be allocated in 16-byte boundaries) */
106/* Transmit/receive buffers (must be allocated in 16-byte boundaries) */
107static uint8_t ehernet_nc_memory[(sizeof(edmac_send_desc_t) * NUM_OF_TX_DESCRIPTOR) +
108 (sizeof(edmac_recv_desc_t) * NUM_OF_RX_DESCRIPTOR) +
109 (NUM_OF_TX_DESCRIPTOR * SIZE_OF_BUFFER) +
110 (NUM_OF_RX_DESCRIPTOR * SIZE_OF_BUFFER)]
111 __attribute((section("NC_BSS"),aligned(16))); //16 bytes aligned!
112static int32_t rx_read_offset; /* read offset */
113static int32_t tx_wite_offset; /* write offset */
114static uint32_t send_top_index;
115static uint32_t recv_top_index;
116static int32_t Interrupt_priority;
117static edmac_send_desc_t *p_eth_desc_dsend = NULL;
118static edmac_recv_desc_t *p_eth_desc_drecv = NULL;
119static edmac_recv_desc_t *p_recv_end_desc = NULL;
120static ethernetext_cb_fnc *p_recv_cb_fnc = NULL;
121static char mac_addr[6] = {0x00, 0x02, 0xF7, 0xF0, 0x00, 0x00}; /* MAC Address */
122static uint32_t phy_id = 0;
123static uint32_t start_stop = 1; /* 0:stop 1:start */
124
125/* function */
126static void lan_reg_reset(void);
127static void lan_desc_create(void);
128static void lan_reg_set(int32_t link);
129static uint16_t phy_reg_read(uint16_t reg_addr);
130static void phy_reg_write(uint16_t reg_addr, uint16_t data);
131static void mii_preamble(void);
132static void mii_cmd(uint16_t reg_addr, uint32_t option);
133static void mii_reg_read(uint16_t *data);
134static void mii_reg_write(uint16_t data);
135static void mii_z(void);
136static void mii_write_1(void);
137static void mii_write_0(void);
138static void set_ether_pir(uint32_t set_data);
139static void wait_100us(int32_t wait_cnt);
140
141
142int ethernetext_init(ethernet_cfg_t *p_ethcfg) {
143 int32_t i;
144 uint16_t val;
145
146 CPGSTBCR7 &= ~(CPG_STBCR7_BIT_MSTP74); /* enable ETHER clock */
147
148 /* P4_2(PHY Reset) */
149 GPIOP4 &= ~0x0004; /* Outputs low level */
150 GPIOPMC4 &= ~0x0004; /* Port mode */
151 GPIOPM4 &= ~0x0004; /* Output mode */
152
153 /* GPIO P1 P1_14(ET_COL) */
154 GPIOPMC1 |= 0x4000;
155 GPIOPFCAE1 &= ~0x4000;
156 GPIOPFCE1 |= 0x4000;
157 GPIOPFC1 |= 0x4000;
158
159 /* P3_0(ET_TXCLK), P3_3(ET_MDIO), P3_4(ET_RXCLK), P3_5(ET_RXER), P3_6(ET_RXDV) */
160 GPIOPMC3 |= 0x0079;
161 GPIOPFCAE3 &= ~0x0079;
162 GPIOPFCE3 &= ~0x0079;
163 GPIOPFC3 |= 0x0079;
164 GPIOPIPC3 |= 0x0079;
165
166 /* P5_9(ET_MDC) */
167 GPIOPMC5 |= 0x0200;
168 GPIOPFCAE5 &= ~0x0200;
169 GPIOPFCE5 &= ~0x0200;
170 GPIOPFC5 |= 0x0200;
171 GPIOPIPC5 |= 0x0200;
172
173 /* P10_1(ET_TXER), P10_2(ET_TXEN), P10_3(ET_CRS), P10_4(ET_TXD0), P10_5(ET_TXD1) */
174 /* P10_6(ET_TXD2), P10_7(ET_TXD3), P10_8(ET_RXD0), P10_9(ET_RXD1), P10_10(ET_RXD2), P10_11(ET_RXD3) */
175 GPIOPMC10 |= 0x0FFE;
176 GPIOPFCAE10 &= ~0x0FFE;
177 GPIOPFCE10 |= 0x0FFE;
178 GPIOPFC10 |= 0x0FFE;
179 GPIOPIPC10 |= 0x0FFE;
180
181 /* Resets the E-MAC,E-DMAC */
182 lan_reg_reset();
183
184 /* PHY Reset */
185 GPIOP4 &= ~0x0004; /* P4_2 Outputs low level */
186 wait_100us(250); /* 25msec */
187 GPIOP4 |= 0x0004; /* P4_2 Outputs high level */
188 wait_100us(100); /* 10msec */
189
190 /* Resets the PHY-LSI */
191 phy_reg_write(BASIC_MODE_CONTROL_REG, 0x8000);
192 for (i = 10000; i > 0; i--) {
193 val = phy_reg_read(BASIC_MODE_CONTROL_REG);
194 if (((uint32_t)val & 0x8000uL) == 0) {
195 break; /* Reset complete */
196 }
197 }
198
199 phy_id = ((uint32_t)phy_reg_read(PHY_IDENTIFIER1_REG) << 16)
200 | (uint32_t)phy_reg_read(PHY_IDENTIFIER2_REG);
201
202 Interrupt_priority = p_ethcfg->int_priority;
203 p_recv_cb_fnc = p_ethcfg->recv_cb;
204 start_stop = 1;
205
206 if (p_ethcfg->ether_mac != NULL) {
207 (void)memcpy(mac_addr, p_ethcfg->ether_mac, sizeof(mac_addr));
208 } else {
209 ethernet_address(mac_addr); /* Get MAC Address */
210 }
211
212 return 0;
213}
214
215void ethernetext_start_stop(int32_t mode) {
216 if (mode == 1) {
217 /* start */
218 ETHEREDTRR0 |= EDTRR0_TR;
219 ETHEREDRRR0 |= EDRRR0_RR;
220 start_stop = 1;
221 } else {
222 /* stop */
223 ETHEREDTRR0 &= ~EDTRR0_TR;
224 ETHEREDRRR0 &= ~EDRRR0_RR;
225 start_stop = 0;
226 }
227}
228
229int ethernetext_chk_link_mode(void) {
230 int32_t link;
231 uint16_t data;
232
233 if ((phy_id & M_PHY_ID) == PHY_ID_LAN8710A) {
234 data = phy_reg_read(PHY_SP_CTL_STS_REG);
235 switch (((uint32_t)data >> 2) & 0x00000007) {
236 case 0x0001:
237 link = HALF_10M;
238 break;
239 case 0x0005:
240 link = FULL_10M;
241 break;
242 case 0x0002:
243 link = HALF_TX;
244 break;
245 case 0x0006:
246 link = FULL_TX;
247 break;
248 default:
249 link = NEGO_FAIL;
250 break;
251 }
252 } else {
253 link = NEGO_FAIL;
254 }
255
256 return link;
257}
258
259void ethernetext_set_link_mode(int32_t link) {
260 lan_reg_reset(); /* Resets the E-MAC,E-DMAC */
261 lan_desc_create(); /* Initialize of buffer memory */
262 lan_reg_set(link); /* E-DMAC, E-MAC initialization */
263}
264
265int ethernet_init() {
266 ethernet_cfg_t ethcfg;
267
268 ethcfg.int_priority = 5;
269 ethcfg.recv_cb = NULL;
270 ethcfg.ether_mac = NULL;
271 ethernetext_init(&ethcfg);
272 ethernet_set_link(-1, 0); /* Auto-Negotiation */
273
274 return 0;
275}
276
277void ethernet_free() {
278 ETHERARSTR |= 0x00000001; /* ETHER software reset */
279 CPGSTBCR7 |= CPG_STBCR7_BIT_MSTP74; /* disable ETHER clock */
280}
281
282int ethernet_write(const char *data, int slen) {
283 edmac_send_desc_t *p_send_desc;
284 int32_t copy_size;
285
286 if ((p_eth_desc_dsend == NULL) || (data == NULL) || (slen < 0)
287 || (tx_wite_offset < 0) || (tx_wite_offset >= MAX_SEND_SIZE)) {
288 copy_size = 0;
289 } else {
290 p_send_desc = &p_eth_desc_dsend[send_top_index]; /* Current descriptor */
291 if ((p_send_desc->td0 & TD0_TACT) != 0) {
292 copy_size = 0;
293 } else {
294 copy_size = MAX_SEND_SIZE - tx_wite_offset;
295 if (copy_size > slen) {
296 copy_size = slen;
297 }
298 (void)memcpy(&p_send_desc->td2[tx_wite_offset], data, copy_size);
299 tx_wite_offset += copy_size;
300 }
301 }
302
303 return copy_size;
304}
305
306int ethernet_send() {
307 edmac_send_desc_t *p_send_desc;
308 int32_t ret;
309
310 if ((p_eth_desc_dsend == NULL) || (tx_wite_offset <= 0)) {
311 ret = 0;
312 } else {
313 /* Transfer 1 frame */
314 p_send_desc = &p_eth_desc_dsend[send_top_index]; /* Current descriptor */
315
316 /* Sets the frame length */
317 p_send_desc->td1 = ((uint32_t)tx_wite_offset << 16);
318 tx_wite_offset = 0;
319
320 /* Sets the transmit descriptor to transmit again */
321 p_send_desc->td0 &= (TD0_TACT | TD0_TDLE | TD0_TFP_TOP_BOTTOM);
322 p_send_desc->td0 |= TD0_TACT;
323 if ((start_stop == 1) && ((ETHEREDTRR0 & EDTRR0_TR) != EDTRR0_TR)) {
324 ETHEREDTRR0 |= EDTRR0_TR;
325 }
326
327 /* Update the current descriptor */
328 send_top_index++;
329 if (send_top_index >= NUM_OF_TX_DESCRIPTOR) {
330 send_top_index = 0;
331 }
332 ret = 1;
333 }
334
335 return ret;
336}
337
338int ethernet_receive() {
339 edmac_recv_desc_t *p_recv_desc;
340 int32_t receive_size = 0;
341
342 if (p_eth_desc_drecv != NULL) {
343 if (p_recv_end_desc != NULL) {
344 /* Sets the receive descriptor to receive again */
345 p_recv_end_desc->rd0 &= (RD0_RACT | RD0_RDLE);
346 p_recv_end_desc->rd0 |= RD0_RACT;
347 if ((start_stop == 1) && ((ETHEREDRRR0 & EDRRR0_RR) == 0)) {
348 ETHEREDRRR0 |= EDRRR0_RR;
349 }
350 p_recv_end_desc = NULL;
351 }
352
353 p_recv_desc = &p_eth_desc_drecv[recv_top_index]; /* Current descriptor */
354 if ((p_recv_desc->rd0 & RD0_RACT) == 0) {
355 /* Receives 1 frame */
356 if (((p_recv_desc->rd0 & RD0_RFE) != 0) && ((p_recv_desc->rd0 & RD0_RFS_ERROR) != 0)) {
357 /* Receive frame error */
358 /* Sets the receive descriptor to receive again */
359 p_recv_desc->rd0 &= (RD0_RACT | RD0_RDLE);
360 p_recv_desc->rd0 |= RD0_RACT;
361 if ((start_stop == 1) && ((ETHEREDRRR0 & EDRRR0_RR) == 0)) {
362 ETHEREDRRR0 |= EDRRR0_RR;
363 }
364 } else {
365 /* Copies the received frame */
366 rx_read_offset = 0;
367 p_recv_end_desc = p_recv_desc;
368 receive_size = (p_recv_desc->rd1 & RD1_RDL_MSK); /* number of bytes received */
369 }
370
371 /* Update the current descriptor */
372 recv_top_index++;
373 if (recv_top_index >= NUM_OF_TX_DESCRIPTOR) {
374 recv_top_index = 0;
375 }
376 }
377 }
378
379 return receive_size;
380}
381
382int ethernet_read(char *data, int dlen) {
383 edmac_recv_desc_t *p_recv_desc = p_recv_end_desc; /* Read top descriptor */
384 int32_t copy_size;
385
386 if ((data == NULL) || (dlen < 0) || (p_recv_desc == NULL)) {
387 copy_size = 0;
388 } else {
389 copy_size = (p_recv_desc->rd1 & RD1_RDL_MSK) - rx_read_offset;
390 if (copy_size > dlen) {
391 copy_size = dlen;
392 }
393 (void)memcpy(data, &p_recv_desc->rd2[rx_read_offset], (size_t)copy_size);
394 rx_read_offset += copy_size;
395 }
396
397 return copy_size;
398}
399
400void ethernet_address(char *mac) {
401 if (mac != NULL) {
402 mbed_mac_address(mac); /* Get MAC Address */
403 }
404}
405
406int ethernet_link(void) {
407 int32_t ret;
408 uint16_t data;
409
410 data = phy_reg_read(BASIC_MODE_STATUS_REG);
411 if (((uint32_t)data & BASIC_STS_MSK_LINK) != 0) {
412 ret = 1;
413 } else {
414 ret = 0;
415 }
416
417 return ret;
418}
419
420void ethernet_set_link(int speed, int duplex) {
421 uint16_t data;
422 int32_t i;
423 int32_t link;
424
425 if ((speed < 0) || (speed > 1)) {
426 data = 0x1000; /* Auto-Negotiation Enable */
427 phy_reg_write(BASIC_MODE_CONTROL_REG, data);
428 data = phy_reg_read(BASIC_MODE_STATUS_REG);
429 for (i = 0; i < 1000; i++) {
430 if (((uint32_t)data & BASIC_STS_MSK_AUTO_CMP) != 0) {
431 break;
432 }
433 wait_100us(10);
434 }
435 } else {
436 data = (uint16_t)(((uint32_t)speed << 13) | ((uint32_t)duplex << 8));
437 phy_reg_write(BASIC_MODE_CONTROL_REG, data);
438 wait_100us(1);
439 }
440
441 link = ethernetext_chk_link_mode();
442 ethernetext_set_link_mode(link);
443}
444
445void INT_Ether(void) {
446 uint32_t stat_edmac;
447 uint32_t stat_etherc;
448
449 /* Clear the interrupt request flag */
450 stat_edmac = (ETHEREESR0 & ETHEREESIPR0); /* Targets are restricted to allowed interrupts */
451 ETHEREESR0 = stat_edmac;
452 /* Reception-related */
453 if (stat_edmac & EDMAC_EESIPR_INI_RECV) {
454 if (p_recv_cb_fnc != NULL) {
455 p_recv_cb_fnc();
456 }
457 }
458 /* E-MAC-related */
459 if (stat_edmac & EDMAC_EESIPR_INI_EtherC) {
460 /* Clear the interrupt request flag */
461 stat_etherc = (ETHERECSR0 & ETHERECSIPR0); /* Targets are restricted to allowed interrupts */
462 ETHERECSR0 = stat_etherc;
463 }
464}
465
466static void lan_reg_reset(void) {
467 volatile int32_t j = 400; /* Wait for B dia 256 cycles ((I dia/B dia)*256)/6cyc = 8*256/6 = 342 */
468
469 ETHERARSTR |= 0x00000001; /* ETHER software reset */
470 while (j--) {
471 /* Do Nothing */
472 }
473
474 ETHEREDSR0 |= 0x00000003; /* E-DMAC software reset */
475 ETHEREDMR0 |= 0x00000003; /* Set SWRR and SWRT simultaneously */
476
477 /* Check clear software reset */
478 while ((ETHEREDMR0 & 0x00000003) != 0) {
479 /* Do Nothing */
480 }
481}
482
483static void lan_desc_create(void) {
484 int32_t i;
485 uint8_t *p_memory_top;
486
487 (void)memset((void *)ehernet_nc_memory, 0, sizeof(ehernet_nc_memory));
488 p_memory_top = ehernet_nc_memory;
489
490 /* Descriptor area configuration */
491 p_eth_desc_dsend = (edmac_send_desc_t *)p_memory_top;
492 p_memory_top += (sizeof(edmac_send_desc_t) * NUM_OF_TX_DESCRIPTOR);
493 p_eth_desc_drecv = (edmac_recv_desc_t *)p_memory_top;
494 p_memory_top += (sizeof(edmac_recv_desc_t) * NUM_OF_RX_DESCRIPTOR);
495
496 /* Transmit descriptor */
497 for (i = 0; i < NUM_OF_TX_DESCRIPTOR; i++) {
498 p_eth_desc_dsend[i].td2 = p_memory_top; /* TD2 TBA */
499 p_memory_top += SIZE_OF_BUFFER;
500 p_eth_desc_dsend[i].td1 = 0; /* TD1 TDL */
501 p_eth_desc_dsend[i].td0 = TD0_TFP_TOP_BOTTOM; /* TD0:1frame/1buf1buf, transmission disabled */
502 }
503 p_eth_desc_dsend[i - 1].td0 |= TD0_TDLE; /* Set the last descriptor */
504
505 /* Receive descriptor */
506 for (i = 0; i < NUM_OF_RX_DESCRIPTOR; i++) {
507 p_eth_desc_drecv[i].rd2 = p_memory_top; /* RD2 RBA */
508 p_memory_top += SIZE_OF_BUFFER;
509 p_eth_desc_drecv[i].rd1 = ((uint32_t)SIZE_OF_BUFFER << 16); /* RD1 RBL */
510 p_eth_desc_drecv[i].rd0 = RD0_RACT; /* RD0:reception enabled */
511 }
512 p_eth_desc_drecv[i - 1].rd0 |= RD0_RDLE; /* Set the last descriptor */
513
514 /* Initialize descriptor management information */
515 send_top_index = 0;
516 recv_top_index = 0;
517 rx_read_offset = 0;
518 tx_wite_offset = 0;
519 p_recv_end_desc = NULL;
520}
521
522static void lan_reg_set(int32_t link) {
523 /* MAC address setting */
524 ETHERMAHR0 = ((uint32_t)mac_addr[0] << 24)
525 | ((uint32_t)mac_addr[1] << 16)
526 | ((uint32_t)mac_addr[2] << 8)
527 | (uint32_t)mac_addr[3];
528 ETHERMALR0 = ((uint32_t)mac_addr[4] << 8)
529 | (uint32_t)mac_addr[5];
530
531 /* E-DMAC */
532 ETHERTDLAR0 = (uint32_t)&p_eth_desc_dsend[0];
533 ETHERRDLAR0 = (uint32_t)&p_eth_desc_drecv[0];
534 ETHERTDFAR0 = (uint32_t)&p_eth_desc_dsend[0];
535 ETHERRDFAR0 = (uint32_t)&p_eth_desc_drecv[0];
536 ETHERTDFXR0 = (uint32_t)&p_eth_desc_dsend[NUM_OF_TX_DESCRIPTOR - 1];
537 ETHERRDFXR0 = (uint32_t)&p_eth_desc_drecv[NUM_OF_RX_DESCRIPTOR - 1];
538 ETHERTDFFR0 |= 0x00000001; /* TDLF Transmit Descriptor Queue Last Flag : Last descriptor (1) */
539 ETHERRDFFR0 |= 0x00000001; /* RDLF Receive Descriptor Queue Last Flag : Last descriptor (1) */
540 ETHEREDMR0 |= 0x00000040; /* Little endian */
541 ETHERTRSCER0 &= ~0x0003009F; /* All clear */
542 ETHERTFTR0 &= ~0x000007FF; /* TFT[10:0] Transmit FIFO Threshold : Store and forward modes (H'000) */
543 ETHERFDR0 |= 0x00000707; /* Transmit FIFO Size:2048 bytes, Receive FIFO Size:2048 bytes */
544 ETHERRMCR0 |= 0x00000001; /* RNC Receive Enable Control : Continuous reception enabled (1) */
545 ETHERFCFTR0 &= ~0x001F00FF;
546 ETHERFCFTR0 |= 0x00070007;
547 ETHERRPADIR0 &= ~0x001FFFFF; /* Padding Size:No padding insertion, Padding Slot:Inserts at first byte */
548
549 /* E-MAC */
550 ETHERECMR0 &= ~0x04BF2063; /* All clear */
551 ETHERRFLR0 &= ~0x0003FFFF; /* RFL[17:0] Receive Frame Length : 1518 bytes (H'00000) */
552 ETHERAPR0 &= ~0x0000FFFF; /* AP[15:0] Automatic PAUSE : Flow control is disabled (H'0000) */
553 ETHERMPR0 &= ~0x0000FFFF; /* MP[15:0] Manual PAUSE : Flow control is disabled (H'0000) */
554 ETHERTPAUSER0 &= ~0x0000FFFF; /* Upper Limit for Automatic PAUSE Frame : Retransmit count is unlimited */
555 ETHERCSMR &= ~0xC000003F; /* The result of checksum is not written back to the receive descriptor */
556 if ((link == FULL_TX) || (link == FULL_10M) || (link == NEGO_FAIL)) {
557 ETHERECMR0 |= 0x00000002; /* Set to full-duplex mode */
558 } else {
559 ETHERECMR0 &= ~0x00000002; /* Set to half-duplex mode */
560 }
561
562 /* Interrupt-related */
563 if (p_recv_cb_fnc != NULL) {
564 ETHEREESR0 |= 0xFF7F009F; /* Clear all status (by writing 1) */
565 ETHEREESIPR0 |= 0x00040000; /* FR Frame Reception (1) */
566 ETHERECSR0 |= 0x00000011; /* Clear all status (clear by writing 1) */
567 ETHERECSIPR0 &= ~0x00000011; /* PFROIP Disable, ICDIP Disable */
568 /*InterruptHandlerRegister(ETHERI_IRQn, INT_Ether); /* Ethernet interrupt handler registration */
569 GIC_SetPriority(ETHERI_IRQn, Interrupt_priority); /* Ethernet interrupt priority */
570 GIC_EnableIRQ(ETHERI_IRQn); /* Enables the E-DMAC interrupt */
571 }
572
573 ETHERECMR0 |= 0x00000060; /* RE Enable, TE Enable */
574
575 /* Enable transmission/reception */
576 if ((start_stop == 1) && ((ETHEREDRRR0 & 0x00000001) == 0)) {
577 ETHEREDRRR0 |= 0x00000001; /* RR */
578 }
579}
580
581static uint16_t phy_reg_read(uint16_t reg_addr) {
582 uint16_t data;
583
584 mii_preamble();
585 mii_cmd(reg_addr, PHY_READ);
586 mii_z();
587 mii_reg_read(&data);
588 mii_z();
589
590 return data;
591}
592
593static void phy_reg_write(uint16_t reg_addr, uint16_t data) {
594 mii_preamble();
595 mii_cmd(reg_addr, PHY_WRITE);
596 mii_write_1();
597 mii_write_0();
598 mii_reg_write(data);
599 mii_z();
600}
601
602static void mii_preamble(void) {
603 int32_t i = 32;
604
605 for (i = 32; i > 0; i--) {
606 /* 1 is output via the MII (Media Independent Interface) block. */
607 mii_write_1();
608 }
609}
610
611static void mii_cmd(uint16_t reg_addr, uint32_t option) {
612 int32_t i;
613 uint16_t data = 0;
614
615 data |= (PHY_ST << 14); /* ST code */
616 data |= (option << 12); /* OP code */
617 data |= (PHY_ADDR << 7); /* PHY Address */
618 data |= (uint16_t)(reg_addr << 2); /* Reg Address */
619 for (i = 14; i > 0; i--) {
620 if ((data & 0x8000) == 0) {
621 mii_write_0();
622 } else {
623 mii_write_1();
624 }
625 data <<= 1;
626 }
627}
628
629static void mii_reg_read(uint16_t *data) {
630 int32_t i;
631 uint16_t reg_data = 0;
632
633 /* Data are read in one bit at a time */
634 for (i = 16; i > 0; i--) {
635 set_ether_pir(PIR0_MDC_LOW);
636 set_ether_pir(PIR0_MDC_HIGH);
637 reg_data <<= 1;
638 reg_data |= (uint16_t)((ETHERPIR0 & PIR0_MDI) >> 3); /* MDI read */
639 set_ether_pir(PIR0_MDC_HIGH);
640 set_ether_pir(PIR0_MDC_LOW);
641 }
642 *data = reg_data;
643}
644
645static void mii_reg_write(uint16_t data) {
646 int32_t i;
647
648 /* Data are written one bit at a time */
649 for (i = 16; i > 0; i--) {
650 if ((data & 0x8000) == 0) {
651 mii_write_0();
652 } else {
653 mii_write_1();
654 }
655 data <<= 1;
656 }
657}
658
659static void mii_z(void) {
660 set_ether_pir(PIR0_MDC_LOW);
661 set_ether_pir(PIR0_MDC_HIGH);
662 set_ether_pir(PIR0_MDC_HIGH);
663 set_ether_pir(PIR0_MDC_LOW);
664}
665
666static void mii_write_1(void) {
667 set_ether_pir(PIR0_MDO | PIR0_MMD);
668 set_ether_pir(PIR0_MDO | PIR0_MMD | PIR0_MDC);
669 set_ether_pir(PIR0_MDO | PIR0_MMD | PIR0_MDC);
670 set_ether_pir(PIR0_MDO | PIR0_MMD);
671}
672
673static void mii_write_0(void) {
674 set_ether_pir(PIR0_MMD);
675 set_ether_pir(PIR0_MMD | PIR0_MDC);
676 set_ether_pir(PIR0_MMD | PIR0_MDC);
677 set_ether_pir(PIR0_MMD);
678}
679
680static void set_ether_pir(uint32_t set_data) {
681 int32_t i;
682
683 for (i = MDC_WAIT; i > 0; i--) {
684 ETHERPIR0 = set_data;
685 }
686}
687
688static void wait_100us(int32_t wait_cnt) {
689 volatile int32_t j = LOOP_100us * wait_cnt;
690
691 while (--j) {
692 /* Do Nothing */
693 }
694}
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