[270] | 1 | /* mbed Microcontroller Library
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| 2 | * Copyright (c) 2006-2013 ARM Limited
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| 3 | *
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| 4 | * Licensed under the Apache License, Version 2.0 (the "License");
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| 5 | * you may not use this file except in compliance with the License.
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| 6 | * You may obtain a copy of the License at
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| 7 | *
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| 8 | * http://www.apache.org/licenses/LICENSE-2.0
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| 9 | *
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| 10 | * Unless required by applicable law or agreed to in writing, software
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| 11 | * distributed under the License is distributed on an "AS IS" BASIS,
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| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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| 13 | * See the License for the specific language governing permissions and
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| 14 | * limitations under the License.
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| 15 | */
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| 16 | #include <string.h>
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| 17 | #include "mbed_assert.h"
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| 18 | #include "can_api.h"
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| 19 | #include "RZ_A1_Init.h"
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| 20 | #include "cmsis.h"
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| 21 | #include "pinmap.h"
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| 22 | #include "rscan0_iodefine.h"
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| 23 | #include "r_typedefs.h"
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| 24 | #include "MBRZA1H.h"
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| 25 |
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| 26 | #define CAN_NUM 5
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| 27 | #define CAN_SND_RCV 2
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| 28 | #define IRQ_NUM 8
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| 29 |
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| 30 | static void can_rec_irq(uint32_t ch);
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| 31 | static void can_trx_irq(uint32_t ch);
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| 32 | static void can_err_irq(uint32_t ch, CanIrqType type);
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| 33 | static void can0_rec_irq(void);
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| 34 | static void can1_rec_irq(void);
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| 35 | static void can2_rec_irq(void);
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| 36 | static void can3_rec_irq(void);
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| 37 | static void can4_rec_irq(void);
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| 38 | static void can0_trx_irq(void);
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| 39 | static void can1_trx_irq(void);
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| 40 | static void can2_trx_irq(void);
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| 41 | static void can3_trx_irq(void);
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| 42 | static void can4_trx_irq(void);
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| 43 | static void can0_err_warning_irq(void);
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| 44 | static void can1_err_warning_irq(void);
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| 45 | static void can2_err_warning_irq(void);
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| 46 | static void can3_err_warning_irq(void);
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| 47 | static void can4_err_warning_irq(void);
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| 48 | static void can0_overrun_irq(void);
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| 49 | static void can1_overrun_irq(void);
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| 50 | static void can2_overrun_irq(void);
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| 51 | static void can3_overrun_irq(void);
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| 52 | static void can4_overrun_irq(void);
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| 53 | static void can0_passive_irq(void);
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| 54 | static void can1_passive_irq(void);
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| 55 | static void can2_passive_irq(void);
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| 56 | static void can3_passive_irq(void);
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| 57 | static void can4_passive_irq(void);
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| 58 | static void can0_arb_lost_irq(void);
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| 59 | static void can1_arb_lost_irq(void);
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| 60 | static void can2_arb_lost_irq(void);
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| 61 | static void can3_arb_lost_irq(void);
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| 62 | static void can4_arb_lost_irq(void);
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| 63 | static void can0_bus_err_irq(void);
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| 64 | static void can1_bus_err_irq(void);
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| 65 | static void can2_bus_err_irq(void);
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| 66 | static void can3_bus_err_irq(void);
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| 67 | static void can4_bus_err_irq(void);
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| 68 | static void can_reset_reg(can_t *obj);
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| 69 | static void can_reset_recv_rule(can_t *obj);
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| 70 | static void can_reset_buffer(can_t *obj);
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| 71 | static void can_reconfigure_channel(void);
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| 72 | static void can_set_frequency(can_t *obj, int f);
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| 73 | static void can_set_global_mode(int mode);
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| 74 | static void can_set_channel_mode(uint32_t ch, int mode);
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| 75 |
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| 76 | typedef enum {
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| 77 | CAN_SEND = 0,
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| 78 | CAN_RECV
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| 79 | } CANfunc;
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| 80 |
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| 81 | typedef enum {
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| 82 | GL_OPE = 0,
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| 83 | GL_RESET,
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| 84 | GL_TEST
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| 85 | } Globalmode;
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| 86 |
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| 87 | typedef enum {
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| 88 | CH_COMM = 0,
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| 89 | CH_RESET,
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| 90 | CH_HOLD
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| 91 | } Channelmode;
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| 92 |
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| 93 | typedef struct {
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| 94 | IRQn_Type int_num; /* Interrupt number */
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| 95 | IRQHandler handler; /* Interrupt handler */
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| 96 | } can_info_int_t;
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| 97 |
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| 98 | static can_irq_handler irq_handler;
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| 99 | static uint32_t can_irq_id[CAN_NUM];
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| 100 | static int can_initialized[CAN_NUM] = {0};
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| 101 |
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| 102 | static const PinMap PinMap_CAN_RD[] = {
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| 103 | {P7_8 , CAN_0, 4},
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| 104 | {P9_1 , CAN_0, 3},
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| 105 | {P1_4 , CAN_1, 3},
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| 106 | {P5_9 , CAN_1, 5},
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| 107 | {P7_11 , CAN_1, 4},
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| 108 | {P11_12, CAN_1, 1},
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| 109 | {P4_9 , CAN_2, 6},
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| 110 | {P6_4 , CAN_2, 3},
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| 111 | {P7_2 , CAN_2, 5},
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| 112 | {P2_12 , CAN_3, 5},
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| 113 | {P4_2 , CAN_3, 4},
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| 114 | {P1_5 , CAN_4, 3},
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| 115 | {P2_14 , CAN_4, 5},
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| 116 | {NC , NC , 0}
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| 117 | };
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| 118 |
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| 119 | static const PinMap PinMap_CAN_TD[] = {
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| 120 | {P7_9 , CAN_0, 4},
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| 121 | {P9_0 , CAN_0, 3},
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| 122 | {P5_10 , CAN_1, 5},
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| 123 | {P7_10 , CAN_1, 4},
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| 124 | {P11_13, CAN_1, 1},
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| 125 | {P4_8 , CAN_2, 6},
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| 126 | {P6_5 , CAN_2, 3},
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| 127 | {P7_3 , CAN_2, 5},
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| 128 | {P2_13 , CAN_3, 5},
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| 129 | {P4_3 , CAN_3, 4},
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| 130 | {P4_11 , CAN_4, 6},
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| 131 | {P8_10 , CAN_4, 5},
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| 132 | {NC , NC , 0}
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| 133 | };
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| 134 |
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| 135 | static __IO uint32_t *CTR_MATCH[] = {
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| 136 | &RSCAN0C0CTR,
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| 137 | &RSCAN0C1CTR,
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| 138 | &RSCAN0C2CTR,
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| 139 | &RSCAN0C3CTR,
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| 140 | &RSCAN0C4CTR,
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| 141 | };
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| 142 |
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| 143 | static __IO uint32_t *CFG_MATCH[] = {
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| 144 | &RSCAN0C0CFG,
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| 145 | &RSCAN0C1CFG,
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| 146 | &RSCAN0C2CFG,
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| 147 | &RSCAN0C3CFG,
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| 148 | &RSCAN0C4CFG,
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| 149 | };
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| 150 |
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| 151 | static __IO uint32_t *RFCC_MATCH[] = {
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| 152 | &RSCAN0RFCC0,
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| 153 | &RSCAN0RFCC1,
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| 154 | &RSCAN0RFCC2,
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| 155 | &RSCAN0RFCC3,
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| 156 | &RSCAN0RFCC4,
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| 157 | &RSCAN0RFCC5,
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| 158 | &RSCAN0RFCC6,
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| 159 | &RSCAN0RFCC7
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| 160 | };
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| 161 |
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| 162 | static __IO uint32_t *TXQCC_MATCH[] = {
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| 163 | &RSCAN0TXQCC0,
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| 164 | &RSCAN0TXQCC1,
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| 165 | &RSCAN0TXQCC2,
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| 166 | &RSCAN0TXQCC3,
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| 167 | &RSCAN0TXQCC4,
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| 168 | };
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| 169 |
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| 170 | static __IO uint32_t *THLCC_MATCH[] = {
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| 171 | &RSCAN0THLCC0,
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| 172 | &RSCAN0THLCC1,
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| 173 | &RSCAN0THLCC2,
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| 174 | &RSCAN0THLCC3,
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| 175 | &RSCAN0THLCC4,
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| 176 | };
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| 177 |
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| 178 | static __IO uint32_t *STS_MATCH[] = {
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| 179 | &RSCAN0C0STS,
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| 180 | &RSCAN0C1STS,
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| 181 | &RSCAN0C2STS,
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| 182 | &RSCAN0C3STS,
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| 183 | &RSCAN0C4STS,
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| 184 | };
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| 185 |
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| 186 | static __IO uint32_t *ERFL_MATCH[] = {
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| 187 | &RSCAN0C0ERFL,
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| 188 | &RSCAN0C1ERFL,
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| 189 | &RSCAN0C2ERFL,
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| 190 | &RSCAN0C3ERFL,
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| 191 | &RSCAN0C4ERFL,
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| 192 | };
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| 193 |
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| 194 | static __IO uint32_t *CFCC_TBL[CAN_NUM][CAN_SND_RCV] = {
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| 195 | { &RSCAN0CFCC0 , &RSCAN0CFCC1 },
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| 196 | { &RSCAN0CFCC3 , &RSCAN0CFCC4 },
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| 197 | { &RSCAN0CFCC6 , &RSCAN0CFCC7 },
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| 198 | { &RSCAN0CFCC9 , &RSCAN0CFCC10 },
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| 199 | { &RSCAN0CFCC12, &RSCAN0CFCC13 }
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| 200 | };
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| 201 |
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| 202 | static __IO uint32_t *CFSTS_TBL[CAN_NUM][CAN_SND_RCV] = {
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| 203 | { &RSCAN0CFSTS0 , &RSCAN0CFSTS1 },
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| 204 | { &RSCAN0CFSTS3 , &RSCAN0CFSTS4 },
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| 205 | { &RSCAN0CFSTS6 , &RSCAN0CFSTS7 },
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| 206 | { &RSCAN0CFSTS9 , &RSCAN0CFSTS10 },
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| 207 | { &RSCAN0CFSTS12, &RSCAN0CFSTS13 }
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| 208 | };
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| 209 |
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| 210 | static __IO uint32_t *CFPCTR_TBL[CAN_NUM][CAN_SND_RCV] = {
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| 211 | { &RSCAN0CFPCTR0 , &RSCAN0CFPCTR1 },
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| 212 | { &RSCAN0CFPCTR3 , &RSCAN0CFPCTR4 },
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| 213 | { &RSCAN0CFPCTR6 , &RSCAN0CFPCTR7 },
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| 214 | { &RSCAN0CFPCTR9 , &RSCAN0CFPCTR10 },
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| 215 | { &RSCAN0CFPCTR12, &RSCAN0CFPCTR13 }
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| 216 | };
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| 217 |
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| 218 | static __IO uint32_t *CFID_TBL[CAN_NUM][CAN_SND_RCV] = {
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| 219 | { &RSCAN0CFID0 , &RSCAN0CFID1 },
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| 220 | { &RSCAN0CFID3 , &RSCAN0CFID4 },
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| 221 | { &RSCAN0CFID6 , &RSCAN0CFID7 },
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| 222 | { &RSCAN0CFID9 , &RSCAN0CFID10 },
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| 223 | { &RSCAN0CFID12, &RSCAN0CFID13 }
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| 224 | };
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| 225 |
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| 226 | static __IO uint32_t *CFPTR_TBL[CAN_NUM][CAN_SND_RCV] = {
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| 227 | { &RSCAN0CFPTR0 , &RSCAN0CFPTR1 },
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| 228 | { &RSCAN0CFPTR3 , &RSCAN0CFPTR4 },
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| 229 | { &RSCAN0CFPTR6 , &RSCAN0CFPTR7 },
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| 230 | { &RSCAN0CFPTR9 , &RSCAN0CFPTR10 },
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| 231 | { &RSCAN0CFPTR12, &RSCAN0CFPTR13 }
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| 232 | };
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| 233 |
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| 234 | static __IO uint32_t *CFDF0_TBL[CAN_NUM][CAN_SND_RCV] = {
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| 235 | { &RSCAN0CFDF00 , &RSCAN0CFDF01 },
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| 236 | { &RSCAN0CFDF03 , &RSCAN0CFDF04 },
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| 237 | { &RSCAN0CFDF06 , &RSCAN0CFDF07 },
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| 238 | { &RSCAN0CFDF09 , &RSCAN0CFDF010 },
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| 239 | { &RSCAN0CFDF012, &RSCAN0CFDF013 }
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| 240 | };
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| 241 |
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| 242 | static __IO uint32_t *CFDF1_TBL[CAN_NUM][CAN_SND_RCV] = {
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| 243 | { &RSCAN0CFDF10 , &RSCAN0CFDF11 },
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| 244 | { &RSCAN0CFDF13 , &RSCAN0CFDF14 },
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| 245 | { &RSCAN0CFDF16 , &RSCAN0CFDF17 },
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| 246 | { &RSCAN0CFDF19 , &RSCAN0CFDF110 },
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| 247 | { &RSCAN0CFDF112, &RSCAN0CFDF113 }
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| 248 | };
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| 249 |
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| 250 | static const can_info_int_t can_int_info[CAN_NUM][IRQ_NUM] =
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| 251 | {
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| 252 | { /* ch0 */
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| 253 | { INTRCAN0REC_IRQn, can0_rec_irq }, /* RxIrq */
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| 254 | { INTRCAN0TRX_IRQn, can0_trx_irq }, /* TxIrq */
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| 255 | { INTRCAN0ERR_IRQn, can0_err_warning_irq }, /* EwIrq */
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| 256 | { INTRCAN0ERR_IRQn, can0_overrun_irq }, /* DoIrq */
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| 257 | { INTRCAN0ERR_IRQn, NULL }, /* WuIrq(not supported) */
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| 258 | { INTRCAN0ERR_IRQn, can0_passive_irq }, /* EpIrq */
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| 259 | { INTRCAN0ERR_IRQn, can0_arb_lost_irq }, /* AlIrq */
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| 260 | { INTRCAN0ERR_IRQn, can0_bus_err_irq } /* BeIrq */
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| 261 | },
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| 262 | { /* ch1 */
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| 263 | { INTRCAN1REC_IRQn, can1_rec_irq }, /* RxIrq */
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| 264 | { INTRCAN1TRX_IRQn, can1_trx_irq }, /* TxIrq */
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| 265 | { INTRCAN1ERR_IRQn, can1_err_warning_irq }, /* EwIrq */
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| 266 | { INTRCAN1ERR_IRQn, can1_overrun_irq }, /* DoIrq */
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| 267 | { INTRCAN1ERR_IRQn, NULL }, /* WuIrq(not supported) */
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| 268 | { INTRCAN1ERR_IRQn, can1_passive_irq }, /* EpIrq */
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| 269 | { INTRCAN1ERR_IRQn, can1_arb_lost_irq }, /* AlIrq */
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| 270 | { INTRCAN1ERR_IRQn, can1_bus_err_irq } /* BeIrq */
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| 271 | },
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| 272 | { /* ch2 */
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| 273 | { INTRCAN2REC_IRQn, can2_rec_irq }, /* RxIrq */
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| 274 | { INTRCAN2TRX_IRQn, can2_trx_irq }, /* TxIrq */
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| 275 | { INTRCAN2ERR_IRQn, can2_err_warning_irq }, /* EwIrq */
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| 276 | { INTRCAN2ERR_IRQn, can2_overrun_irq }, /* DoIrq */
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| 277 | { INTRCAN2ERR_IRQn, NULL }, /* WuIrq(not supported) */
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| 278 | { INTRCAN2ERR_IRQn, can2_passive_irq }, /* EpIrq */
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| 279 | { INTRCAN2ERR_IRQn, can2_arb_lost_irq }, /* AlIrq */
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| 280 | { INTRCAN2ERR_IRQn, can2_bus_err_irq } /* BeIrq */
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| 281 | },
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| 282 | { /* ch3 */
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| 283 | { INTRCAN3REC_IRQn, can3_rec_irq }, /* RxIrq */
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| 284 | { INTRCAN3TRX_IRQn, can3_trx_irq }, /* TxIrq */
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| 285 | { INTRCAN3ERR_IRQn, can3_err_warning_irq }, /* EwIrq */
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| 286 | { INTRCAN3ERR_IRQn, can3_overrun_irq }, /* DoIrq */
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| 287 | { INTRCAN3ERR_IRQn, NULL }, /* WuIrq(not supported) */
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| 288 | { INTRCAN3ERR_IRQn, can3_passive_irq }, /* EpIrq */
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| 289 | { INTRCAN3ERR_IRQn, can3_arb_lost_irq }, /* AlIrq */
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| 290 | { INTRCAN3ERR_IRQn, can3_bus_err_irq } /* BeIrq */
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| 291 | },
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| 292 | { /* ch4 */
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| 293 | { INTRCAN4REC_IRQn, can4_rec_irq }, /* RxIrq */
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| 294 | { INTRCAN4TRX_IRQn, can4_trx_irq }, /* TxIrq */
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| 295 | { INTRCAN4ERR_IRQn, can4_err_warning_irq }, /* EwIrq */
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| 296 | { INTRCAN4ERR_IRQn, can4_overrun_irq }, /* DoIrq */
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| 297 | { INTRCAN4ERR_IRQn, NULL }, /* WuIrq(not supported) */
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| 298 | { INTRCAN4ERR_IRQn, can4_passive_irq }, /* EpIrq */
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| 299 | { INTRCAN4ERR_IRQn, can4_arb_lost_irq }, /* AlIrq */
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| 300 | { INTRCAN4ERR_IRQn, can4_bus_err_irq } /* BeIrq */
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| 301 | }
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| 302 | };
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| 303 |
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| 304 | static __IO uint32_t *dmy_gaflid = &RSCAN0GAFLID0;
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| 305 | static __IO uint32_t *dmy_gaflm = &RSCAN0GAFLM0;
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| 306 | static __IO uint32_t *dmy_gaflp0 = &RSCAN0GAFLP00;
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| 307 | static __IO uint32_t *dmy_gaflp1 = &RSCAN0GAFLP10;
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| 308 |
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| 309 | void can_irq_init(can_t *obj, can_irq_handler handler, uint32_t id) {
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| 310 | irq_handler = handler;
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| 311 | can_irq_id[obj->ch] = id;
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| 312 | }
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| 313 |
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| 314 | void can_irq_free(can_t *obj) {
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| 315 | can_irq_id[obj->ch] = 0;
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| 316 | }
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| 317 |
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| 318 | void can_irq_set(can_t *obj, CanIrqType type, uint32_t enable) {
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| 319 | __IO uint32_t *dmy_ctr;
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| 320 |
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| 321 | /* Wake-up Irq is not supported */
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| 322 | if (type != IRQ_WAKEUP) {
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| 323 | if (enable) {
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| 324 | dmy_ctr = CTR_MATCH[obj->ch];
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| 325 | if (type == IRQ_ERROR) {
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| 326 | /* EWIE interrupts is enable */
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| 327 | *dmy_ctr |= 0x00000200;
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| 328 | } else if (type == IRQ_OVERRUN) {
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| 329 | /* OLIE interrupts is enable */
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| 330 | *dmy_ctr |= 0x00002000;
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| 331 | } else if (type == IRQ_PASSIVE) {
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| 332 | /* EPIE interrupts is enable */
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| 333 | *dmy_ctr |= 0x00000400;
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| 334 | } else if (type == IRQ_ARB) {
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| 335 | /* ALIE interrupts is enable */
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| 336 | *dmy_ctr |= 0x00008000;
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| 337 | } else if (type == IRQ_BUS) {
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| 338 | /* BEIE interrupts is enable */
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| 339 | *dmy_ctr |= 0x00000100;
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| 340 | }
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| 341 | InterruptHandlerRegister(can_int_info[obj->ch][type].int_num, can_int_info[obj->ch][type].handler);
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| 342 | GIC_SetPriority(can_int_info[obj->ch][type].int_num, 5);
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| 343 | GIC_EnableIRQ(can_int_info[obj->ch][type].int_num);
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| 344 | } else {
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| 345 | GIC_DisableIRQ(can_int_info[obj->ch][type].int_num);
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| 346 | }
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| 347 | }
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| 348 | }
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| 349 |
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| 350 | static void can_rec_irq(uint32_t ch) {
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| 351 | __IO uint32_t *dmy_cfsts;
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| 352 |
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| 353 | dmy_cfsts = CFSTS_TBL[ch][CAN_RECV];
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| 354 | *dmy_cfsts &= 0xFFFFFFF7; // Clear CFRXIF
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| 355 |
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| 356 | irq_handler(can_irq_id[ch], IRQ_RX);
|
---|
| 357 | }
|
---|
| 358 |
|
---|
| 359 | static void can_trx_irq(uint32_t ch) {
|
---|
| 360 | __IO uint32_t *dmy_cfsts;
|
---|
| 361 |
|
---|
| 362 | dmy_cfsts = CFSTS_TBL[ch][CAN_SEND];
|
---|
| 363 | *dmy_cfsts &= 0xFFFFFFEF; // Clear CFTXIF
|
---|
| 364 |
|
---|
| 365 | irq_handler(can_irq_id[ch], IRQ_TX);
|
---|
| 366 | }
|
---|
| 367 |
|
---|
| 368 | static void can_err_irq(uint32_t ch, CanIrqType type) {
|
---|
| 369 | __IO uint32_t *dmy_erfl;
|
---|
| 370 | int val = 1;
|
---|
| 371 |
|
---|
| 372 | dmy_erfl = ERFL_MATCH[ch];
|
---|
| 373 | switch (type) {
|
---|
| 374 | case IRQ_ERROR:
|
---|
| 375 | *dmy_erfl &= 0xFFFFFFFD; // Clear EWF
|
---|
| 376 | break;
|
---|
| 377 | case IRQ_OVERRUN:
|
---|
| 378 | *dmy_erfl &= 0xFFFFFFDF; // Clear OVLF
|
---|
| 379 | break;
|
---|
| 380 | case IRQ_PASSIVE:
|
---|
| 381 | *dmy_erfl &= 0xFFFFFFFB; // Clear EPF
|
---|
| 382 | break;
|
---|
| 383 | case IRQ_ARB:
|
---|
| 384 | *dmy_erfl &= 0xFFFFFF7F; // Clear ALF
|
---|
| 385 | break;
|
---|
| 386 | case IRQ_BUS:
|
---|
| 387 | *dmy_erfl &= 0xFFFF00FF; // Clear ADERR, B0ERR, B1ERR, CERR, AERR, FERR, SERR
|
---|
| 388 | *dmy_erfl &= 0xFFFFFFFE; // Clear BEF
|
---|
| 389 | break;
|
---|
| 390 | case IRQ_WAKEUP:
|
---|
| 391 | /* not supported */
|
---|
| 392 | /* fall through */
|
---|
| 393 | default:
|
---|
| 394 | val = 0;
|
---|
| 395 | break;
|
---|
| 396 | }
|
---|
| 397 | if (val == 1) {
|
---|
| 398 | irq_handler(can_irq_id[ch], type);
|
---|
| 399 | }
|
---|
| 400 | }
|
---|
| 401 |
|
---|
| 402 | static void can0_rec_irq(void) {
|
---|
| 403 | can_rec_irq(CAN_0);
|
---|
| 404 | }
|
---|
| 405 |
|
---|
| 406 | static void can1_rec_irq(void) {
|
---|
| 407 | can_rec_irq(CAN_1);
|
---|
| 408 | }
|
---|
| 409 |
|
---|
| 410 | static void can2_rec_irq(void) {
|
---|
| 411 | can_rec_irq(CAN_2);
|
---|
| 412 | }
|
---|
| 413 |
|
---|
| 414 | static void can3_rec_irq(void) {
|
---|
| 415 | can_rec_irq(CAN_3);
|
---|
| 416 | }
|
---|
| 417 |
|
---|
| 418 | static void can4_rec_irq(void) {
|
---|
| 419 | can_rec_irq(CAN_4);
|
---|
| 420 | }
|
---|
| 421 |
|
---|
| 422 | static void can0_trx_irq(void) {
|
---|
| 423 | can_trx_irq(CAN_0);
|
---|
| 424 | }
|
---|
| 425 |
|
---|
| 426 | static void can1_trx_irq(void) {
|
---|
| 427 | can_trx_irq(CAN_1);
|
---|
| 428 | }
|
---|
| 429 |
|
---|
| 430 | static void can2_trx_irq(void) {
|
---|
| 431 | can_trx_irq(CAN_2);
|
---|
| 432 | }
|
---|
| 433 |
|
---|
| 434 | static void can3_trx_irq(void) {
|
---|
| 435 | can_trx_irq(CAN_3);
|
---|
| 436 | }
|
---|
| 437 |
|
---|
| 438 | static void can4_trx_irq(void) {
|
---|
| 439 | can_trx_irq(CAN_4);
|
---|
| 440 | }
|
---|
| 441 |
|
---|
| 442 | static void can0_err_warning_irq(void) {
|
---|
| 443 | can_err_irq(CAN_0, IRQ_ERROR);
|
---|
| 444 | }
|
---|
| 445 |
|
---|
| 446 | static void can1_err_warning_irq(void) {
|
---|
| 447 | can_err_irq(CAN_1, IRQ_ERROR);
|
---|
| 448 | }
|
---|
| 449 |
|
---|
| 450 | static void can2_err_warning_irq(void) {
|
---|
| 451 | can_err_irq(CAN_2, IRQ_ERROR);
|
---|
| 452 | }
|
---|
| 453 |
|
---|
| 454 | static void can3_err_warning_irq(void) {
|
---|
| 455 | can_err_irq(CAN_3, IRQ_ERROR);
|
---|
| 456 | }
|
---|
| 457 |
|
---|
| 458 | static void can4_err_warning_irq(void) {
|
---|
| 459 | can_err_irq(CAN_4, IRQ_ERROR);
|
---|
| 460 | }
|
---|
| 461 |
|
---|
| 462 | static void can0_overrun_irq(void) {
|
---|
| 463 | can_err_irq(CAN_0, IRQ_OVERRUN);
|
---|
| 464 | }
|
---|
| 465 |
|
---|
| 466 | static void can1_overrun_irq(void) {
|
---|
| 467 | can_err_irq(CAN_1, IRQ_OVERRUN);
|
---|
| 468 | }
|
---|
| 469 |
|
---|
| 470 | static void can2_overrun_irq(void) {
|
---|
| 471 | can_err_irq(CAN_2, IRQ_OVERRUN);
|
---|
| 472 | }
|
---|
| 473 |
|
---|
| 474 | static void can3_overrun_irq(void) {
|
---|
| 475 | can_err_irq(CAN_3, IRQ_OVERRUN);
|
---|
| 476 | }
|
---|
| 477 |
|
---|
| 478 | static void can4_overrun_irq(void) {
|
---|
| 479 | can_err_irq(CAN_4, IRQ_OVERRUN);
|
---|
| 480 | }
|
---|
| 481 |
|
---|
| 482 | static void can0_passive_irq(void) {
|
---|
| 483 | can_err_irq(CAN_0, IRQ_PASSIVE);
|
---|
| 484 | }
|
---|
| 485 |
|
---|
| 486 | static void can1_passive_irq(void) {
|
---|
| 487 | can_err_irq(CAN_1, IRQ_PASSIVE);
|
---|
| 488 | }
|
---|
| 489 |
|
---|
| 490 | static void can2_passive_irq(void) {
|
---|
| 491 | can_err_irq(CAN_2, IRQ_PASSIVE);
|
---|
| 492 | }
|
---|
| 493 |
|
---|
| 494 | static void can3_passive_irq(void) {
|
---|
| 495 | can_err_irq(CAN_3, IRQ_PASSIVE);
|
---|
| 496 | }
|
---|
| 497 |
|
---|
| 498 | static void can4_passive_irq(void) {
|
---|
| 499 | can_err_irq(CAN_4, IRQ_PASSIVE);
|
---|
| 500 | }
|
---|
| 501 |
|
---|
| 502 | static void can0_arb_lost_irq(void) {
|
---|
| 503 | can_err_irq(CAN_0, IRQ_ARB);
|
---|
| 504 | }
|
---|
| 505 |
|
---|
| 506 | static void can1_arb_lost_irq(void) {
|
---|
| 507 | can_err_irq(CAN_1, IRQ_ARB);
|
---|
| 508 | }
|
---|
| 509 |
|
---|
| 510 | static void can2_arb_lost_irq(void) {
|
---|
| 511 | can_err_irq(CAN_2, IRQ_ARB);
|
---|
| 512 | }
|
---|
| 513 |
|
---|
| 514 | static void can3_arb_lost_irq(void) {
|
---|
| 515 | can_err_irq(CAN_3, IRQ_ARB);
|
---|
| 516 | }
|
---|
| 517 |
|
---|
| 518 | static void can4_arb_lost_irq(void) {
|
---|
| 519 | can_err_irq(CAN_4, IRQ_ARB);
|
---|
| 520 | }
|
---|
| 521 |
|
---|
| 522 | static void can0_bus_err_irq(void) {
|
---|
| 523 | can_err_irq(CAN_0, IRQ_BUS);
|
---|
| 524 | }
|
---|
| 525 |
|
---|
| 526 | static void can1_bus_err_irq(void) {
|
---|
| 527 | can_err_irq(CAN_1, IRQ_BUS);
|
---|
| 528 | }
|
---|
| 529 |
|
---|
| 530 | static void can2_bus_err_irq(void) {
|
---|
| 531 | can_err_irq(CAN_2, IRQ_BUS);
|
---|
| 532 | }
|
---|
| 533 |
|
---|
| 534 | static void can3_bus_err_irq(void) {
|
---|
| 535 | can_err_irq(CAN_3, IRQ_BUS);
|
---|
| 536 | }
|
---|
| 537 |
|
---|
| 538 | static void can4_bus_err_irq(void) {
|
---|
| 539 | can_err_irq(CAN_4, IRQ_BUS);
|
---|
| 540 | }
|
---|
| 541 |
|
---|
| 542 | void can_init(can_t *obj, PinName rd, PinName td) {
|
---|
| 543 | __IO uint32_t *dmy_ctr;
|
---|
| 544 |
|
---|
| 545 | /* determine the CAN to use */
|
---|
| 546 | uint32_t can_rx = pinmap_peripheral(rd, PinMap_CAN_RD);
|
---|
| 547 | uint32_t can_tx = pinmap_peripheral(td, PinMap_CAN_TD);
|
---|
| 548 | obj->ch = pinmap_merge(can_tx, can_rx);
|
---|
| 549 | MBED_ASSERT((int)obj->ch != NC);
|
---|
| 550 |
|
---|
| 551 | /* enable CAN clock */
|
---|
| 552 | CPGSTBCR3 &= ~(CPG_STBCR3_BIT_MSTP32);
|
---|
| 553 | /* Has CAN RAM initialisation completed ? */
|
---|
| 554 | while ((RSCAN0GSTS & 0x08) == 0x08) {
|
---|
| 555 | __NOP();
|
---|
| 556 | }
|
---|
| 557 | /* clear Global Stop mode bit */
|
---|
| 558 | RSCAN0GCTR &= 0xFFFFFFFB;
|
---|
| 559 | /* clear Channel Stop mode bit */
|
---|
| 560 | dmy_ctr = CTR_MATCH[obj->ch];
|
---|
| 561 | *dmy_ctr &= 0xFFFFFFFB;
|
---|
| 562 | /* Enter global reset mode */
|
---|
| 563 | can_set_global_mode(GL_RESET);
|
---|
| 564 | /* Enter channel reset mode */
|
---|
| 565 | can_set_channel_mode(obj->ch, CH_RESET);
|
---|
| 566 | /* reset register */
|
---|
| 567 | can_reset_reg(obj);
|
---|
| 568 |
|
---|
| 569 | can_initialized[obj->ch] = 1;
|
---|
| 570 | /* reconfigure channel which is already initialized */
|
---|
| 571 | can_reconfigure_channel();
|
---|
| 572 |
|
---|
| 573 | /* pin out the can pins */
|
---|
| 574 | pinmap_pinout(rd, PinMap_CAN_RD);
|
---|
| 575 | pinmap_pinout(td, PinMap_CAN_TD);
|
---|
| 576 | }
|
---|
| 577 |
|
---|
| 578 | void can_free(can_t *obj) {
|
---|
| 579 | /* disable CAN clock */
|
---|
| 580 | CPGSTBCR3 |= CPG_STBCR3_BIT_MSTP32;
|
---|
| 581 | }
|
---|
| 582 |
|
---|
| 583 | int can_frequency(can_t *obj, int f) {
|
---|
| 584 | int retval = 0;
|
---|
| 585 |
|
---|
| 586 | if (f <= 1000000) {
|
---|
| 587 | /* less than 1Mhz */
|
---|
| 588 | /* set Channel Reset mode */
|
---|
| 589 | can_set_channel_mode(obj->ch, CH_RESET);
|
---|
| 590 | can_set_frequency(obj, f);
|
---|
| 591 | /* set Channel Communication mode */
|
---|
| 592 | can_set_channel_mode(obj->ch, CH_COMM);
|
---|
| 593 | retval = 1;
|
---|
| 594 | }
|
---|
| 595 |
|
---|
| 596 | return retval;
|
---|
| 597 | }
|
---|
| 598 |
|
---|
| 599 | void can_reset(can_t *obj) {
|
---|
| 600 | /* Enter global reset mode */
|
---|
| 601 | can_set_global_mode(GL_RESET);
|
---|
| 602 | /* Enter channel reset mode */
|
---|
| 603 | can_set_channel_mode(obj->ch, CH_RESET);
|
---|
| 604 | /* reset register */
|
---|
| 605 | can_reset_reg(obj);
|
---|
| 606 | /* reconfigure channel which is already initialized */
|
---|
| 607 | can_reconfigure_channel();
|
---|
| 608 | }
|
---|
| 609 |
|
---|
| 610 | int can_write(can_t *obj, CAN_Message msg, int cc) {
|
---|
| 611 | __IO uint32_t *dmy_sts;
|
---|
| 612 | __IO uint32_t *dmy_cfsts;
|
---|
| 613 | __IO uint32_t *dmy_cfid;
|
---|
| 614 | __IO uint32_t *dmy_cfptr;
|
---|
| 615 | __IO uint32_t *dmy_cfdf0;
|
---|
| 616 | __IO uint32_t *dmy_cfdf1;
|
---|
| 617 | __IO uint32_t *dmy_cfpctr;
|
---|
| 618 | int retval = 0;
|
---|
| 619 |
|
---|
| 620 | /* Wait to become channel communication mode */
|
---|
| 621 | dmy_sts = STS_MATCH[obj->ch];
|
---|
| 622 | while ((*dmy_sts & 0x07) != 0) {
|
---|
| 623 | __NOP();
|
---|
| 624 | }
|
---|
| 625 |
|
---|
| 626 | if (((msg.format == CANStandard) && (msg.id <= 0x07FF)) || ((msg.format == CANExtended) && (msg.id <= 0x03FFFF))) {
|
---|
| 627 | /* send/receive FIFO buffer isn't full */
|
---|
| 628 | dmy_cfsts = CFSTS_TBL[obj->ch][CAN_SEND];
|
---|
| 629 | if ((*dmy_cfsts & 0x02) != 0x02) {
|
---|
| 630 | /* set format, frame type and send/receive FIFO buffer ID(b10-0 or b28-11) */
|
---|
| 631 | dmy_cfid = CFID_TBL[obj->ch][CAN_SEND];
|
---|
| 632 | *dmy_cfid = ((msg.format << 31) | (msg.type << 30));
|
---|
| 633 | if (msg.format == CANStandard) {
|
---|
| 634 | *dmy_cfid |= (msg.id & 0x07FF);
|
---|
| 635 | } else {
|
---|
| 636 | *dmy_cfid |= ((msg.id & 0x03FFFF) << 11);
|
---|
| 637 | }
|
---|
| 638 | /* set length */
|
---|
| 639 | dmy_cfptr = CFPTR_TBL[obj->ch][CAN_SEND];
|
---|
| 640 | *dmy_cfptr = msg.len << 28;
|
---|
| 641 | /* set data */
|
---|
| 642 | dmy_cfdf0 = CFDF0_TBL[obj->ch][CAN_SEND];
|
---|
| 643 | memcpy((void *)dmy_cfdf0, &msg.data[0], 4);
|
---|
| 644 | dmy_cfdf1 = CFDF1_TBL[obj->ch][CAN_SEND];
|
---|
| 645 | memcpy((void *)dmy_cfdf1, &msg.data[4], 4);
|
---|
| 646 | /* send request */
|
---|
| 647 | dmy_cfpctr = CFPCTR_TBL[obj->ch][CAN_SEND];
|
---|
| 648 | *dmy_cfpctr = 0xFF;
|
---|
| 649 | retval = 1;
|
---|
| 650 | }
|
---|
| 651 | }
|
---|
| 652 |
|
---|
| 653 | return retval;
|
---|
| 654 | }
|
---|
| 655 |
|
---|
| 656 | int can_read(can_t *obj, CAN_Message *msg, int handle) {
|
---|
| 657 | __IO uint32_t *dmy_sts;
|
---|
| 658 | __IO uint32_t *dmy_cfsts;
|
---|
| 659 | __IO uint32_t *dmy_cfid;
|
---|
| 660 | __IO uint32_t *dmy_cfptr;
|
---|
| 661 | __IO uint32_t *dmy_cfdf0;
|
---|
| 662 | __IO uint32_t *dmy_cfdf1;
|
---|
| 663 | __IO uint32_t *dmy_cfpctr;
|
---|
| 664 | int retval = 0;
|
---|
| 665 |
|
---|
| 666 | /* Wait to become channel communication mode */
|
---|
| 667 | dmy_sts = STS_MATCH[obj->ch];
|
---|
| 668 | while ((*dmy_sts & 0x07) != 0) {
|
---|
| 669 | __NOP();
|
---|
| 670 | }
|
---|
| 671 |
|
---|
| 672 | /* send/receive FIFO buffer isn't empty */
|
---|
| 673 | dmy_cfsts = CFSTS_TBL[obj->ch][CAN_RECV];
|
---|
| 674 | while ((*dmy_cfsts & 0x01) != 0x01) {
|
---|
| 675 | /* get format, frame type and send/receive FIFO buffer ID(b10-0 or b28-11) */
|
---|
| 676 | dmy_cfid = CFID_TBL[obj->ch][CAN_RECV];
|
---|
| 677 | msg->format = (CANFormat)(*dmy_cfid >> 31);
|
---|
| 678 | msg->type = (CANType)(*dmy_cfid >> 30);
|
---|
| 679 | if (msg->format == CANStandard) {
|
---|
| 680 | msg->id = (*dmy_cfid & 0x07FF);
|
---|
| 681 | } else {
|
---|
| 682 | msg->id = ((*dmy_cfid >> 11) & 0x03FFFF);
|
---|
| 683 | }
|
---|
| 684 | /* get length */
|
---|
| 685 | dmy_cfptr = CFPTR_TBL[obj->ch][CAN_RECV];
|
---|
| 686 | msg->len = (unsigned char)(*dmy_cfptr >> 28);
|
---|
| 687 | /* get data */
|
---|
| 688 | dmy_cfdf0 = CFDF0_TBL[obj->ch][CAN_RECV];
|
---|
| 689 | memcpy(&msg->data[0], (void *)dmy_cfdf0, 4);
|
---|
| 690 | dmy_cfdf1 = CFDF1_TBL[obj->ch][CAN_RECV];
|
---|
| 691 | memcpy(&msg->data[4], (void *)dmy_cfdf1, 4);
|
---|
| 692 | /* receive(next data) request */
|
---|
| 693 | dmy_cfpctr = CFPCTR_TBL[obj->ch][CAN_RECV];
|
---|
| 694 | *dmy_cfpctr = 0xFF;
|
---|
| 695 | retval = 1;
|
---|
| 696 | }
|
---|
| 697 |
|
---|
| 698 | return retval;
|
---|
| 699 | }
|
---|
| 700 |
|
---|
| 701 | unsigned char can_rderror(can_t *obj) {
|
---|
| 702 | __IO uint32_t *dmy_sts;
|
---|
| 703 |
|
---|
| 704 | dmy_sts = STS_MATCH[obj->ch];
|
---|
| 705 | return (unsigned char)((*dmy_sts >> 16) & 0xFF);
|
---|
| 706 | }
|
---|
| 707 |
|
---|
| 708 | unsigned char can_tderror(can_t *obj) {
|
---|
| 709 | __IO uint32_t *dmy_sts;
|
---|
| 710 |
|
---|
| 711 | dmy_sts = STS_MATCH[obj->ch];
|
---|
| 712 | return (unsigned char)((*dmy_sts >> 24) & 0xFF);
|
---|
| 713 | }
|
---|
| 714 |
|
---|
| 715 | int can_mode(can_t *obj, CanMode mode) {
|
---|
| 716 | __IO uint32_t *dmy_ctr;
|
---|
| 717 | __IO uint32_t *dmy_sts;
|
---|
| 718 | __IO uint32_t *dmy_cfcc;
|
---|
| 719 | int ch_cnt;
|
---|
| 720 | can_t *tmp_obj;
|
---|
| 721 | tmp_obj = obj;
|
---|
| 722 | int retval = 1;
|
---|
| 723 |
|
---|
| 724 | switch (mode) {
|
---|
| 725 | case MODE_RESET:
|
---|
| 726 | can_set_global_mode(GL_RESET);
|
---|
| 727 | can_set_channel_mode(obj->ch, CH_RESET);
|
---|
| 728 | for (ch_cnt = 0; ch_cnt < CAN_NUM; ch_cnt++) {
|
---|
| 729 | can_initialized[ch_cnt] = 0;
|
---|
| 730 | }
|
---|
| 731 | break;
|
---|
| 732 | case MODE_NORMAL:
|
---|
| 733 | can_set_global_mode(GL_OPE);
|
---|
| 734 | can_set_channel_mode(obj->ch, CH_COMM);
|
---|
| 735 | break;
|
---|
| 736 | case MODE_SILENT:
|
---|
| 737 | can_set_channel_mode(obj->ch, CH_HOLD);
|
---|
| 738 | /* set listen only mode, enable communication test mode */
|
---|
| 739 | dmy_ctr = CTR_MATCH[obj->ch];
|
---|
| 740 | *dmy_ctr = ((*dmy_ctr & 0x00FFFFFF) | 0x03000000);
|
---|
| 741 | can_set_channel_mode(obj->ch, CH_COMM);
|
---|
| 742 | break;
|
---|
| 743 | case MODE_TEST_LOCAL:
|
---|
| 744 | can_set_channel_mode(obj->ch, CH_HOLD);
|
---|
| 745 | /* set self test mode 0, enable communication test mode */
|
---|
| 746 | dmy_ctr = CTR_MATCH[obj->ch];
|
---|
| 747 | *dmy_ctr = ((*dmy_ctr & 0x00FFFFFF) | 0x05000000);
|
---|
| 748 | can_set_channel_mode(obj->ch, CH_COMM);
|
---|
| 749 | break;
|
---|
| 750 | case MODE_TEST_GLOBAL:
|
---|
| 751 | /* set the channel between the communication test on channel 1 and channel 2 */
|
---|
| 752 | /* set Channel Hold mode */
|
---|
| 753 | for (tmp_obj->ch = CAN_1; tmp_obj->ch <= CAN_2; tmp_obj->ch++) {
|
---|
| 754 | dmy_sts = STS_MATCH[tmp_obj->ch];
|
---|
| 755 | if ((*dmy_sts & 0x04) == 0x04) {
|
---|
| 756 | /* Channel Stop mode */
|
---|
| 757 | /* clear Channel Stop mode bit */
|
---|
| 758 | dmy_ctr = CTR_MATCH[tmp_obj->ch];
|
---|
| 759 | *dmy_ctr &= 0xFFFFFFFB;
|
---|
| 760 | can_set_channel_mode(tmp_obj->ch, CH_RESET);
|
---|
| 761 | }
|
---|
| 762 | can_set_channel_mode(tmp_obj->ch, CH_HOLD);
|
---|
| 763 | }
|
---|
| 764 | can_set_global_mode(GL_TEST);
|
---|
| 765 | /* enable communication test between channel1 and channel2 */
|
---|
| 766 | RSCAN0GTSTCFG = 0x06;
|
---|
| 767 | RSCAN0GTSTCTR = 0x01;
|
---|
| 768 | /* send and receive setting of channel1 and channel2 */
|
---|
| 769 | for (tmp_obj->ch = CAN_1; tmp_obj->ch <= CAN_2; tmp_obj->ch++) {
|
---|
| 770 | can_reset_buffer(tmp_obj);
|
---|
| 771 | /* set global interrrupt */
|
---|
| 772 | /* THLEIE, MEIE and DEIE interrupts are disable */
|
---|
| 773 | RSCAN0GCTR &= 0xFFFFF8FF;
|
---|
| 774 | /* BLIE, OLIE, BORIE and BOEIE interrupts are disable */
|
---|
| 775 | /* TAIE, ALIE, EPIE, EWIE and BEIE interrupts are enable */
|
---|
| 776 | dmy_ctr = CTR_MATCH[tmp_obj->ch];
|
---|
| 777 | *dmy_ctr &= 0x00018700;
|
---|
| 778 | can_set_global_mode(GL_OPE);
|
---|
| 779 | can_set_channel_mode(tmp_obj->ch, CH_COMM);
|
---|
| 780 | /* Use send/receive FIFO buffer */
|
---|
| 781 | dmy_cfcc = CFCC_TBL[tmp_obj->ch][CAN_SEND];
|
---|
| 782 | *dmy_cfcc |= 0x01;
|
---|
| 783 | dmy_cfcc = CFCC_TBL[tmp_obj->ch][CAN_RECV];
|
---|
| 784 | *dmy_cfcc |= 0x01;
|
---|
| 785 | }
|
---|
| 786 | break;
|
---|
| 787 | case MODE_TEST_SILENT:
|
---|
| 788 | /* not supported */
|
---|
| 789 | /* fall through */
|
---|
| 790 | default:
|
---|
| 791 | retval = 0;
|
---|
| 792 | break;
|
---|
| 793 | }
|
---|
| 794 |
|
---|
| 795 | return retval;
|
---|
| 796 | }
|
---|
| 797 |
|
---|
| 798 | int can_filter(can_t *obj, uint32_t id, uint32_t mask, CANFormat format, int32_t handle) {
|
---|
| 799 | int retval = 0;
|
---|
| 800 |
|
---|
| 801 | if ((format == CANStandard) || (format == CANExtended)) {
|
---|
| 802 | if (((format == CANStandard) && (id <= 0x07FF)) || ((format == CANExtended) && (id <= 0x03FFFF))) {
|
---|
| 803 | /* set Global Reset mode and Channel Reset mode */
|
---|
| 804 | can_set_global_mode(GL_RESET);
|
---|
| 805 | can_set_channel_mode(obj->ch, CH_RESET);
|
---|
| 806 | /* enable receive rule table writing */
|
---|
| 807 | RSCAN0GAFLECTR = 0x00000100;
|
---|
| 808 | /* set the page number of receive rule table(page number = 0) */
|
---|
| 809 | RSCAN0GAFLECTR |= (obj->ch * 4);
|
---|
| 810 | /* set IDE format */
|
---|
| 811 | *dmy_gaflid = (format << 31);
|
---|
| 812 | if (format == CANExtended) {
|
---|
| 813 | /* set receive rule ID for bit28-11 */
|
---|
| 814 | *dmy_gaflid |= (id << 11);
|
---|
| 815 | } else {
|
---|
| 816 | /* set receive rule ID for bit10-0 */
|
---|
| 817 | *dmy_gaflid |= id;
|
---|
| 818 | }
|
---|
| 819 | /* set ID mask bit */
|
---|
| 820 | *dmy_gaflm = (0xC0000000 | mask);
|
---|
| 821 | /* disable receive rule table writing */
|
---|
| 822 | RSCAN0GAFLECTR &= 0xFFFFFEFF;
|
---|
| 823 | /* reconfigure channel which is already initialized */
|
---|
| 824 | can_reconfigure_channel();
|
---|
| 825 | retval = 1;
|
---|
| 826 | }
|
---|
| 827 | }
|
---|
| 828 |
|
---|
| 829 | return retval;
|
---|
| 830 | }
|
---|
| 831 |
|
---|
| 832 | void can_monitor(can_t *obj, int silent) {
|
---|
| 833 | __IO uint32_t *dmy_ctr;
|
---|
| 834 |
|
---|
| 835 | /* set Channel Hold mode */
|
---|
| 836 | can_set_channel_mode(obj->ch, CH_HOLD);
|
---|
| 837 | if (silent) {
|
---|
| 838 | /* set listen only mode, enable communication test mode */
|
---|
| 839 | dmy_ctr = CTR_MATCH[obj->ch];
|
---|
| 840 | *dmy_ctr = ((*dmy_ctr & 0x00FFFFFF) | 0x03000000);
|
---|
| 841 | can_set_channel_mode(obj->ch, CH_COMM);
|
---|
| 842 | } else {
|
---|
| 843 | /* set normal test mode, disable communication test mode */
|
---|
| 844 | dmy_ctr = CTR_MATCH[obj->ch];
|
---|
| 845 | *dmy_ctr &= 0x00FFFFFF;
|
---|
| 846 | /* reset register */
|
---|
| 847 | can_reset_reg(obj);
|
---|
| 848 | /* reconfigure channel which is already initialized */
|
---|
| 849 | can_reconfigure_channel();
|
---|
| 850 | }
|
---|
| 851 | }
|
---|
| 852 |
|
---|
| 853 | static void can_reset_reg(can_t *obj) {
|
---|
| 854 | __IO uint32_t *dmy_ctr;
|
---|
| 855 |
|
---|
| 856 | /* time stamp source uses peripheral clock (pclk(P1_phi)/2), CAN clock uses clkc(P1_phi/2), */
|
---|
| 857 | /* mirror off, DLC not transfer, DLC check permit, transmit buffer priority, clock source not divided */
|
---|
| 858 | RSCAN0GCFG = 0x00000003;
|
---|
| 859 | /* set default frequency at 100k */
|
---|
| 860 | can_set_frequency(obj, 100000);
|
---|
| 861 | /* set receive rule */
|
---|
| 862 | can_reset_recv_rule(obj);
|
---|
| 863 | /* set buffer */
|
---|
| 864 | can_reset_buffer(obj);
|
---|
| 865 | /* set global interrrupt */
|
---|
| 866 | /* THLEIE, MEIE and DEIE interrupts are disable */
|
---|
| 867 | RSCAN0GCTR &= 0xFFFFF8FF;
|
---|
| 868 | /* ALIE, BLIE, OLIE, BORIE, BOEIE, EPIE, EWIE and BEIE interrupts are disable */
|
---|
| 869 | dmy_ctr = CTR_MATCH[obj->ch];
|
---|
| 870 | *dmy_ctr &= 0xFFFF00FF;
|
---|
| 871 | }
|
---|
| 872 |
|
---|
| 873 | static void can_reset_recv_rule(can_t *obj) {
|
---|
| 874 | /* number of receive rules of each chanel = 64 */
|
---|
| 875 | RSCAN0GAFLCFG0 = 0x40404040;
|
---|
| 876 | RSCAN0GAFLCFG1 = 0x40000000;
|
---|
| 877 | /* enable receive rule table writing */
|
---|
| 878 | RSCAN0GAFLECTR = 0x00000100;
|
---|
| 879 | /* set the page number of receive rule table(ex: id ch = 1, page number = 4) */
|
---|
| 880 | RSCAN0GAFLECTR |= (obj->ch * 4);
|
---|
| 881 | /* set standard ID, data frame and receive rule ID */
|
---|
| 882 | *dmy_gaflid = 0x07FF;
|
---|
| 883 | /* IDE bit, RTR bit and ID bit(28-0) are not compared */
|
---|
| 884 | *dmy_gaflm = 0;
|
---|
| 885 | /* DLC check is 1 bytes, not use a receive buffer */
|
---|
| 886 | *dmy_gaflp0 = 0x10000000;
|
---|
| 887 | /* use a send/receive FIFO buffer(ex: if ch = 1, FIFO buffer number = 4 and bit = 12) */
|
---|
| 888 | *dmy_gaflp1 = (1 << ((obj->ch + 3) * 3));
|
---|
| 889 | /* disable receive rule table writing */
|
---|
| 890 | RSCAN0GAFLECTR &= 0xFFFFFEFF;
|
---|
| 891 | }
|
---|
| 892 |
|
---|
| 893 | static void can_reset_buffer(can_t *obj) {
|
---|
| 894 | __IO uint32_t *dmy_rfcc;
|
---|
| 895 | __IO uint32_t *dmy_cfcc;
|
---|
| 896 | __IO uint32_t *dmy_txqcc;
|
---|
| 897 | __IO uint32_t *dmy_thlcc;
|
---|
| 898 | int cnt;
|
---|
| 899 |
|
---|
| 900 | /* set linked send buffer number(ex: if ch = 1 and mode = send, buffer number = 16), interval timer is pclk/2 */
|
---|
| 901 | /* number of rows of send/receive FIFO buffer = 4 */
|
---|
| 902 | dmy_cfcc = CFCC_TBL[obj->ch][CAN_SEND];
|
---|
| 903 | *dmy_cfcc = 0x00011100; /* send/receive FIFO mode is send */
|
---|
| 904 | dmy_cfcc = CFCC_TBL[obj->ch][CAN_RECV];
|
---|
| 905 | *dmy_cfcc = 0x00001100; /* send/receive FIFO mode is receive */
|
---|
| 906 | /* receive buffer is not used */
|
---|
| 907 | RSCAN0RMNB = 0;
|
---|
| 908 | /* receive FIFO buffer is not used */
|
---|
| 909 | for (cnt = 0; cnt < 8; cnt++) {
|
---|
| 910 | dmy_rfcc = RFCC_MATCH[cnt];
|
---|
| 911 | *dmy_rfcc = 0;
|
---|
| 912 | }
|
---|
| 913 | /* send queue is not used */
|
---|
| 914 | dmy_txqcc = TXQCC_MATCH[obj->ch];
|
---|
| 915 | *dmy_txqcc = 0;
|
---|
| 916 | /* send history is not used */
|
---|
| 917 | dmy_thlcc = THLCC_MATCH[obj->ch];
|
---|
| 918 | *dmy_thlcc = 0;
|
---|
| 919 |
|
---|
| 920 | /* CFTXIE and CFRXIE interrupts are enable */
|
---|
| 921 | dmy_cfcc = CFCC_TBL[obj->ch][CAN_SEND];
|
---|
| 922 | *dmy_cfcc |= 0x04;
|
---|
| 923 | dmy_cfcc = CFCC_TBL[obj->ch][CAN_RECV];
|
---|
| 924 | *dmy_cfcc |= 0x02;
|
---|
| 925 | /* TMIEp interrupt is disable */
|
---|
| 926 | RSCAN0TMIEC0 = 0x00000000;
|
---|
| 927 | RSCAN0TMIEC1 = 0x00000000;
|
---|
| 928 | RSCAN0TMIEC2 = 0x00000000;
|
---|
| 929 | }
|
---|
| 930 |
|
---|
| 931 | static void can_reconfigure_channel(void) {
|
---|
| 932 | __IO uint32_t *dmy_cfcc;
|
---|
| 933 | int ch_cnt;
|
---|
| 934 |
|
---|
| 935 | for (ch_cnt = 0; ch_cnt < CAN_NUM; ch_cnt++) {
|
---|
| 936 | if (can_initialized[ch_cnt] == 1) {
|
---|
| 937 | /* set Global Operation mode and Channel Communication mode */
|
---|
| 938 | can_set_global_mode(GL_OPE);
|
---|
| 939 | can_set_channel_mode(ch_cnt, CH_COMM);
|
---|
| 940 | /* Use send/receive FIFO buffer */
|
---|
| 941 | dmy_cfcc = CFCC_TBL[ch_cnt][CAN_SEND];
|
---|
| 942 | *dmy_cfcc |= 0x01;
|
---|
| 943 | dmy_cfcc = CFCC_TBL[ch_cnt][CAN_RECV];
|
---|
| 944 | *dmy_cfcc |= 0x01;
|
---|
| 945 | }
|
---|
| 946 | }
|
---|
| 947 | }
|
---|
| 948 |
|
---|
| 949 | static void can_set_frequency(can_t *obj, int f) {
|
---|
| 950 | __IO uint32_t *dmy_cfg;
|
---|
| 951 | int oldfreq = 0;
|
---|
| 952 | int newfreq = 0;
|
---|
| 953 | uint32_t clkc_val;
|
---|
| 954 | uint8_t tmp_tq;
|
---|
| 955 | uint8_t tq = 0;
|
---|
| 956 | uint8_t tmp_brp;
|
---|
| 957 | uint8_t brp = 0;
|
---|
| 958 | uint8_t tseg1 = 0;
|
---|
| 959 | uint8_t tseg2 = 0;
|
---|
| 960 |
|
---|
| 961 | /* set clkc */
|
---|
| 962 | if (RZ_A1_IsClockMode0() == false) {
|
---|
| 963 | clkc_val = CM1_RENESAS_RZ_A1_P1_CLK / 2;
|
---|
| 964 | } else {
|
---|
| 965 | clkc_val = CM0_RENESAS_RZ_A1_P1_CLK / 2;
|
---|
| 966 | }
|
---|
| 967 | /* calculate BRP bit and Choose max value of calculated frequency */
|
---|
| 968 | for (tmp_tq = 8; tmp_tq <= 25; tmp_tq++) {
|
---|
| 969 | /* f = fCAN / ((BRP+1) * Tq) */
|
---|
| 970 | /* BRP = (fCAN / (f * Tq)) - 1 */
|
---|
| 971 | tmp_brp = ((clkc_val / (f * tmp_tq)) - 1) + 1; // carry(decimal point is carry)
|
---|
| 972 | newfreq = clkc_val / ((tmp_brp + 1) * tmp_tq);
|
---|
| 973 | if (newfreq >= oldfreq) {
|
---|
| 974 | oldfreq = newfreq;
|
---|
| 975 | tq = tmp_tq;
|
---|
| 976 | brp = tmp_brp;
|
---|
| 977 | }
|
---|
| 978 | }
|
---|
| 979 | /* calculate TSEG1 bit and TSEG2 bit */
|
---|
| 980 | tseg1 = (tq - 1) * 0.666666667;
|
---|
| 981 | tseg2 = (tq - 1) - tseg1;
|
---|
| 982 | /* set RSCAN0CmCFG register */
|
---|
| 983 | dmy_cfg = CFG_MATCH[obj->ch];
|
---|
| 984 | *dmy_cfg = ((tseg2 - 1) << 20) | ((tseg1 - 1) << 16) | brp;
|
---|
| 985 | }
|
---|
| 986 |
|
---|
| 987 | static void can_set_global_mode(int mode) {
|
---|
| 988 | /* set Global mode */
|
---|
| 989 | RSCAN0GCTR = ((RSCAN0GCTR & 0xFFFFFFFC) | mode);
|
---|
| 990 | /* Wait to cahnge into Global XXXX mode */
|
---|
| 991 | while ((RSCAN0GSTS & 0x07) != mode) {
|
---|
| 992 | __NOP();
|
---|
| 993 | }
|
---|
| 994 | }
|
---|
| 995 |
|
---|
| 996 | static void can_set_channel_mode(uint32_t ch, int mode) {
|
---|
| 997 | __IO uint32_t *dmy_ctr;
|
---|
| 998 | __IO uint32_t *dmy_sts;
|
---|
| 999 |
|
---|
| 1000 | /* set Channel mode */
|
---|
| 1001 | dmy_ctr = CTR_MATCH[ch];
|
---|
| 1002 | *dmy_ctr = ((*dmy_ctr & 0xFFFFFFFC) | mode);
|
---|
| 1003 | /* Wait to cahnge into Channel XXXX mode */
|
---|
| 1004 | dmy_sts = STS_MATCH[ch];
|
---|
| 1005 | while ((*dmy_sts & 0x07) != mode) {
|
---|
| 1006 | __NOP();
|
---|
| 1007 | }
|
---|
| 1008 | }
|
---|
| 1009 |
|
---|