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1/**************************************************************************//**
2 * @file core_cm7.h
3 * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File
4 * @version V4.10
5 * @date 18. March 2015
6 *
7 * @note
8 *
9 ******************************************************************************/
10/* Copyright (c) 2009 - 2015 ARM LIMITED
11
12 All rights reserved.
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 - Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 - Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 - Neither the name of ARM nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23 *
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ---------------------------------------------------------------------------*/
36
37
38#if defined ( __ICCARM__ )
39 #pragma system_include /* treat file as system include file for MISRA check */
40#endif
41
42#ifndef __CORE_CM7_H_GENERIC
43#define __CORE_CM7_H_GENERIC
44
45#ifdef __cplusplus
46 extern "C" {
47#endif
48
49/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
50 CMSIS violates the following MISRA-C:2004 rules:
51
52 \li Required Rule 8.5, object/function definition in header file.<br>
53 Function definitions in header files are used to allow 'inlining'.
54
55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
56 Unions are used for effective representation of core registers.
57
58 \li Advisory Rule 19.7, Function-like macro defined.<br>
59 Function-like macros are used to allow more efficient code.
60 */
61
62
63/*******************************************************************************
64 * CMSIS definitions
65 ******************************************************************************/
66/** \ingroup Cortex_M7
67 @{
68 */
69
70/* CMSIS CM7 definitions */
71#define __CM7_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
72#define __CM7_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
73#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16) | \
74 __CM7_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
75
76#define __CORTEX_M (0x07) /*!< Cortex-M Core */
77
78
79#if defined ( __CC_ARM )
80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
82 #define __STATIC_INLINE static __inline
83
84#elif defined ( __GNUC__ )
85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
87 #define __STATIC_INLINE static inline
88
89#elif defined ( __ICCARM__ )
90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
92 #define __STATIC_INLINE static inline
93
94#elif defined ( __TMS470__ )
95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
96 #define __STATIC_INLINE static inline
97
98#elif defined ( __TASKING__ )
99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
101 #define __STATIC_INLINE static inline
102
103#elif defined ( __CSMC__ )
104 #define __packed
105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
107 #define __STATIC_INLINE static inline
108
109#endif
110
111/** __FPU_USED indicates whether an FPU is used or not.
112 For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
113*/
114#if defined ( __CC_ARM )
115 #if defined __TARGET_FPU_VFP
116 #if (__FPU_PRESENT == 1)
117 #define __FPU_USED 1
118 #else
119 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
120 #define __FPU_USED 0
121 #endif
122 #else
123 #define __FPU_USED 0
124 #endif
125
126#elif defined ( __GNUC__ )
127 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
128 #if (__FPU_PRESENT == 1)
129 #define __FPU_USED 1
130 #else
131 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
132 #define __FPU_USED 0
133 #endif
134 #else
135 #define __FPU_USED 0
136 #endif
137
138#elif defined ( __ICCARM__ )
139 #if defined __ARMVFP__
140 #if (__FPU_PRESENT == 1)
141 #define __FPU_USED 1
142 #else
143 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
144 #define __FPU_USED 0
145 #endif
146 #else
147 #define __FPU_USED 0
148 #endif
149
150#elif defined ( __TMS470__ )
151 #if defined __TI_VFP_SUPPORT__
152 #if (__FPU_PRESENT == 1)
153 #define __FPU_USED 1
154 #else
155 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
156 #define __FPU_USED 0
157 #endif
158 #else
159 #define __FPU_USED 0
160 #endif
161
162#elif defined ( __TASKING__ )
163 #if defined __FPU_VFP__
164 #if (__FPU_PRESENT == 1)
165 #define __FPU_USED 1
166 #else
167 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
168 #define __FPU_USED 0
169 #endif
170 #else
171 #define __FPU_USED 0
172 #endif
173
174#elif defined ( __CSMC__ ) /* Cosmic */
175 #if ( __CSMC__ & 0x400) // FPU present for parser
176 #if (__FPU_PRESENT == 1)
177 #define __FPU_USED 1
178 #else
179 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
180 #define __FPU_USED 0
181 #endif
182 #else
183 #define __FPU_USED 0
184 #endif
185#endif
186
187#include <stdint.h> /* standard types definitions */
188#include <core_cmInstr.h> /* Core Instruction Access */
189#include <core_cmFunc.h> /* Core Function Access */
190#include <core_cmSimd.h> /* Compiler specific SIMD Intrinsics */
191
192#ifdef __cplusplus
193}
194#endif
195
196#endif /* __CORE_CM7_H_GENERIC */
197
198#ifndef __CMSIS_GENERIC
199
200#ifndef __CORE_CM7_H_DEPENDANT
201#define __CORE_CM7_H_DEPENDANT
202
203#ifdef __cplusplus
204 extern "C" {
205#endif
206
207/* check device defines and use defaults */
208#if defined __CHECK_DEVICE_DEFINES
209 #ifndef __CM7_REV
210 #define __CM7_REV 0x0000
211 #warning "__CM7_REV not defined in device header file; using default!"
212 #endif
213
214 #ifndef __FPU_PRESENT
215 #define __FPU_PRESENT 0
216 #warning "__FPU_PRESENT not defined in device header file; using default!"
217 #endif
218
219 #ifndef __MPU_PRESENT
220 #define __MPU_PRESENT 0
221 #warning "__MPU_PRESENT not defined in device header file; using default!"
222 #endif
223
224 #ifndef __ICACHE_PRESENT
225 #define __ICACHE_PRESENT 0
226 #warning "__ICACHE_PRESENT not defined in device header file; using default!"
227 #endif
228
229 #ifndef __DCACHE_PRESENT
230 #define __DCACHE_PRESENT 0
231 #warning "__DCACHE_PRESENT not defined in device header file; using default!"
232 #endif
233
234 #ifndef __DTCM_PRESENT
235 #define __DTCM_PRESENT 0
236 #warning "__DTCM_PRESENT not defined in device header file; using default!"
237 #endif
238
239 #ifndef __NVIC_PRIO_BITS
240 #define __NVIC_PRIO_BITS 3
241 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
242 #endif
243
244 #ifndef __Vendor_SysTickConfig
245 #define __Vendor_SysTickConfig 0
246 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
247 #endif
248#endif
249
250/* IO definitions (access restrictions to peripheral registers) */
251/**
252 \defgroup CMSIS_glob_defs CMSIS Global Defines
253
254 <strong>IO Type Qualifiers</strong> are used
255 \li to specify the access to peripheral variables.
256 \li for automatic generation of peripheral register debug information.
257*/
258#ifdef __cplusplus
259 #define __I volatile /*!< Defines 'read only' permissions */
260#else
261 #define __I volatile const /*!< Defines 'read only' permissions */
262#endif
263#define __O volatile /*!< Defines 'write only' permissions */
264#define __IO volatile /*!< Defines 'read / write' permissions */
265
266/*@} end of group Cortex_M7 */
267
268
269
270/*******************************************************************************
271 * Register Abstraction
272 Core Register contain:
273 - Core Register
274 - Core NVIC Register
275 - Core SCB Register
276 - Core SysTick Register
277 - Core Debug Register
278 - Core MPU Register
279 - Core FPU Register
280 ******************************************************************************/
281/** \defgroup CMSIS_core_register Defines and Type Definitions
282 \brief Type definitions and defines for Cortex-M processor based devices.
283*/
284
285/** \ingroup CMSIS_core_register
286 \defgroup CMSIS_CORE Status and Control Registers
287 \brief Core Register type definitions.
288 @{
289 */
290
291/** \brief Union type to access the Application Program Status Register (APSR).
292 */
293typedef union
294{
295 struct
296 {
297 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
298 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
299 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
300 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
301 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
302 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
303 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
304 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
305 } b; /*!< Structure used for bit access */
306 uint32_t w; /*!< Type used for word access */
307} APSR_Type;
308
309/* APSR Register Definitions */
310#define APSR_N_Pos 31 /*!< APSR: N Position */
311#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
312
313#define APSR_Z_Pos 30 /*!< APSR: Z Position */
314#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
315
316#define APSR_C_Pos 29 /*!< APSR: C Position */
317#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
318
319#define APSR_V_Pos 28 /*!< APSR: V Position */
320#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
321
322#define APSR_Q_Pos 27 /*!< APSR: Q Position */
323#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
324
325#define APSR_GE_Pos 16 /*!< APSR: GE Position */
326#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
327
328
329/** \brief Union type to access the Interrupt Program Status Register (IPSR).
330 */
331typedef union
332{
333 struct
334 {
335 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
336 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
337 } b; /*!< Structure used for bit access */
338 uint32_t w; /*!< Type used for word access */
339} IPSR_Type;
340
341/* IPSR Register Definitions */
342#define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
343#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
344
345
346/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
347 */
348typedef union
349{
350 struct
351 {
352 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
353 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
354 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
355 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
356 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
357 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
358 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
359 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
360 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
361 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
362 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
363 } b; /*!< Structure used for bit access */
364 uint32_t w; /*!< Type used for word access */
365} xPSR_Type;
366
367/* xPSR Register Definitions */
368#define xPSR_N_Pos 31 /*!< xPSR: N Position */
369#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
370
371#define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
372#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
373
374#define xPSR_C_Pos 29 /*!< xPSR: C Position */
375#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
376
377#define xPSR_V_Pos 28 /*!< xPSR: V Position */
378#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
379
380#define xPSR_Q_Pos 27 /*!< xPSR: Q Position */
381#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
382
383#define xPSR_IT_Pos 25 /*!< xPSR: IT Position */
384#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
385
386#define xPSR_T_Pos 24 /*!< xPSR: T Position */
387#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
388
389#define xPSR_GE_Pos 16 /*!< xPSR: GE Position */
390#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
391
392#define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
393#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
394
395
396/** \brief Union type to access the Control Registers (CONTROL).
397 */
398typedef union
399{
400 struct
401 {
402 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
403 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
404 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
405 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
406 } b; /*!< Structure used for bit access */
407 uint32_t w; /*!< Type used for word access */
408} CONTROL_Type;
409
410/* CONTROL Register Definitions */
411#define CONTROL_FPCA_Pos 2 /*!< CONTROL: FPCA Position */
412#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
413
414#define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
415#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
416
417#define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
418#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
419
420/*@} end of group CMSIS_CORE */
421
422
423/** \ingroup CMSIS_core_register
424 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
425 \brief Type definitions for the NVIC Registers
426 @{
427 */
428
429/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
430 */
431typedef struct
432{
433 __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
434 uint32_t RESERVED0[24];
435 __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
436 uint32_t RSERVED1[24];
437 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
438 uint32_t RESERVED2[24];
439 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
440 uint32_t RESERVED3[24];
441 __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
442 uint32_t RESERVED4[56];
443 __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
444 uint32_t RESERVED5[644];
445 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
446} NVIC_Type;
447
448/* Software Triggered Interrupt Register Definitions */
449#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
450#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
451
452/*@} end of group CMSIS_NVIC */
453
454
455/** \ingroup CMSIS_core_register
456 \defgroup CMSIS_SCB System Control Block (SCB)
457 \brief Type definitions for the System Control Block Registers
458 @{
459 */
460
461/** \brief Structure type to access the System Control Block (SCB).
462 */
463typedef struct
464{
465 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
466 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
467 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
468 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
469 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
470 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
471 __IO uint8_t SHPR[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
472 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
473 __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
474 __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
475 __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
476 __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
477 __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
478 __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
479 __I uint32_t ID_PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
480 __I uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
481 __I uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
482 __I uint32_t ID_MFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
483 __I uint32_t ID_ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
484 uint32_t RESERVED0[1];
485 __I uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
486 __I uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
487 __I uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
488 __IO uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
489 __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
490 uint32_t RESERVED3[93];
491 __O uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
492 uint32_t RESERVED4[15];
493 __I uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
494 __I uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
495 __I uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */
496 uint32_t RESERVED5[1];
497 __O uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
498 uint32_t RESERVED6[1];
499 __O uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
500 __O uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
501 __O uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
502 __O uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
503 __O uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
504 __O uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
505 __O uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
506 __O uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
507 uint32_t RESERVED7[6];
508 __IO uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */
509 __IO uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */
510 __IO uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */
511 __IO uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */
512 __IO uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */
513 uint32_t RESERVED8[1];
514 __IO uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */
515} SCB_Type;
516
517/* SCB CPUID Register Definitions */
518#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
519#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
520
521#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
522#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
523
524#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
525#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
526
527#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
528#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
529
530#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
531#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
532
533/* SCB Interrupt Control State Register Definitions */
534#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
535#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
536
537#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
538#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
539
540#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
541#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
542
543#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
544#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
545
546#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
547#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
548
549#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
550#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
551
552#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
553#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
554
555#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
556#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
557
558#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
559#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
560
561#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
562#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
563
564/* SCB Vector Table Offset Register Definitions */
565#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
566#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
567
568/* SCB Application Interrupt and Reset Control Register Definitions */
569#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
570#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
571
572#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
573#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
574
575#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
576#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
577
578#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
579#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
580
581#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
582#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
583
584#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
585#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
586
587#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
588#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
589
590/* SCB System Control Register Definitions */
591#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
592#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
593
594#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
595#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
596
597#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
598#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
599
600/* SCB Configuration Control Register Definitions */
601#define SCB_CCR_BP_Pos 18 /*!< SCB CCR: Branch prediction enable bit Position */
602#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */
603
604#define SCB_CCR_IC_Pos 17 /*!< SCB CCR: Instruction cache enable bit Position */
605#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */
606
607#define SCB_CCR_DC_Pos 16 /*!< SCB CCR: Cache enable bit Position */
608#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */
609
610#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
611#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
612
613#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
614#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
615
616#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
617#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
618
619#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
620#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
621
622#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
623#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
624
625#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
626#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
627
628/* SCB System Handler Control and State Register Definitions */
629#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
630#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
631
632#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
633#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
634
635#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
636#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
637
638#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
639#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
640
641#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
642#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
643
644#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
645#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
646
647#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
648#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
649
650#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
651#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
652
653#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
654#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
655
656#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
657#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
658
659#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
660#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
661
662#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
663#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
664
665#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
666#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
667
668#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
669#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
670
671/* SCB Configurable Fault Status Registers Definitions */
672#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
673#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
674
675#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
676#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
677
678#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
679#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
680
681/* SCB Hard Fault Status Registers Definitions */
682#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
683#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
684
685#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
686#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
687
688#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
689#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
690
691/* SCB Debug Fault Status Register Definitions */
692#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
693#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
694
695#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
696#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
697
698#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
699#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
700
701#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
702#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
703
704#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
705#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
706
707/* Cache Level ID register */
708#define SCB_CLIDR_LOUU_Pos 27 /*!< SCB CLIDR: LoUU Position */
709#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
710
711#define SCB_CLIDR_LOC_Pos 24 /*!< SCB CLIDR: LoC Position */
712#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_FORMAT_Pos) /*!< SCB CLIDR: LoC Mask */
713
714/* Cache Type register */
715#define SCB_CTR_FORMAT_Pos 29 /*!< SCB CTR: Format Position */
716#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
717
718#define SCB_CTR_CWG_Pos 24 /*!< SCB CTR: CWG Position */
719#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
720
721#define SCB_CTR_ERG_Pos 20 /*!< SCB CTR: ERG Position */
722#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
723
724#define SCB_CTR_DMINLINE_Pos 16 /*!< SCB CTR: DminLine Position */
725#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
726
727#define SCB_CTR_IMINLINE_Pos 0 /*!< SCB CTR: ImInLine Position */
728#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
729
730/* Cache Size ID Register */
731#define SCB_CCSIDR_WT_Pos 31 /*!< SCB CCSIDR: WT Position */
732#define SCB_CCSIDR_WT_Msk (7UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
733
734#define SCB_CCSIDR_WB_Pos 30 /*!< SCB CCSIDR: WB Position */
735#define SCB_CCSIDR_WB_Msk (7UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
736
737#define SCB_CCSIDR_RA_Pos 29 /*!< SCB CCSIDR: RA Position */
738#define SCB_CCSIDR_RA_Msk (7UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
739
740#define SCB_CCSIDR_WA_Pos 28 /*!< SCB CCSIDR: WA Position */
741#define SCB_CCSIDR_WA_Msk (7UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
742
743#define SCB_CCSIDR_NUMSETS_Pos 13 /*!< SCB CCSIDR: NumSets Position */
744#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
745
746#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3 /*!< SCB CCSIDR: Associativity Position */
747#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
748
749#define SCB_CCSIDR_LINESIZE_Pos 0 /*!< SCB CCSIDR: LineSize Position */
750#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
751
752/* Cache Size Selection Register */
753#define SCB_CSSELR_LEVEL_Pos 1 /*!< SCB CSSELR: Level Position */
754#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
755
756#define SCB_CSSELR_IND_Pos 0 /*!< SCB CSSELR: InD Position */
757#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
758
759/* SCB Software Triggered Interrupt Register */
760#define SCB_STIR_INTID_Pos 0 /*!< SCB STIR: INTID Position */
761#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
762
763/* Instruction Tightly-Coupled Memory Control Register*/
764#define SCB_ITCMCR_SZ_Pos 3 /*!< SCB ITCMCR: SZ Position */
765#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */
766
767#define SCB_ITCMCR_RETEN_Pos 2 /*!< SCB ITCMCR: RETEN Position */
768#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */
769
770#define SCB_ITCMCR_RMW_Pos 1 /*!< SCB ITCMCR: RMW Position */
771#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */
772
773#define SCB_ITCMCR_EN_Pos 0 /*!< SCB ITCMCR: EN Position */
774#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */
775
776/* Data Tightly-Coupled Memory Control Registers */
777#define SCB_DTCMCR_SZ_Pos 3 /*!< SCB DTCMCR: SZ Position */
778#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */
779
780#define SCB_DTCMCR_RETEN_Pos 2 /*!< SCB DTCMCR: RETEN Position */
781#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */
782
783#define SCB_DTCMCR_RMW_Pos 1 /*!< SCB DTCMCR: RMW Position */
784#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */
785
786#define SCB_DTCMCR_EN_Pos 0 /*!< SCB DTCMCR: EN Position */
787#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */
788
789/* AHBP Control Register */
790#define SCB_AHBPCR_SZ_Pos 1 /*!< SCB AHBPCR: SZ Position */
791#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */
792
793#define SCB_AHBPCR_EN_Pos 0 /*!< SCB AHBPCR: EN Position */
794#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */
795
796/* L1 Cache Control Register */
797#define SCB_CACR_FORCEWT_Pos 2 /*!< SCB CACR: FORCEWT Position */
798#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */
799
800#define SCB_CACR_ECCEN_Pos 1 /*!< SCB CACR: ECCEN Position */
801#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */
802
803#define SCB_CACR_SIWT_Pos 0 /*!< SCB CACR: SIWT Position */
804#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */
805
806/* AHBS control register */
807#define SCB_AHBSCR_INITCOUNT_Pos 11 /*!< SCB AHBSCR: INITCOUNT Position */
808#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */
809
810#define SCB_AHBSCR_TPRI_Pos 2 /*!< SCB AHBSCR: TPRI Position */
811#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */
812
813#define SCB_AHBSCR_CTL_Pos 0 /*!< SCB AHBSCR: CTL Position*/
814#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */
815
816/* Auxiliary Bus Fault Status Register */
817#define SCB_ABFSR_AXIMTYPE_Pos 8 /*!< SCB ABFSR: AXIMTYPE Position*/
818#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */
819
820#define SCB_ABFSR_EPPB_Pos 4 /*!< SCB ABFSR: EPPB Position*/
821#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */
822
823#define SCB_ABFSR_AXIM_Pos 3 /*!< SCB ABFSR: AXIM Position*/
824#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */
825
826#define SCB_ABFSR_AHBP_Pos 2 /*!< SCB ABFSR: AHBP Position*/
827#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */
828
829#define SCB_ABFSR_DTCM_Pos 1 /*!< SCB ABFSR: DTCM Position*/
830#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */
831
832#define SCB_ABFSR_ITCM_Pos 0 /*!< SCB ABFSR: ITCM Position*/
833#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */
834
835/*@} end of group CMSIS_SCB */
836
837
838/** \ingroup CMSIS_core_register
839 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
840 \brief Type definitions for the System Control and ID Register not in the SCB
841 @{
842 */
843
844/** \brief Structure type to access the System Control and ID Register not in the SCB.
845 */
846typedef struct
847{
848 uint32_t RESERVED0[1];
849 __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
850 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
851} SCnSCB_Type;
852
853/* Interrupt Controller Type Register Definitions */
854#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
855#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
856
857/* Auxiliary Control Register Definitions */
858#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12 /*!< ACTLR: DISITMATBFLUSH Position */
859#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */
860
861#define SCnSCB_ACTLR_DISRAMODE_Pos 11 /*!< ACTLR: DISRAMODE Position */
862#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */
863
864#define SCnSCB_ACTLR_FPEXCODIS_Pos 10 /*!< ACTLR: FPEXCODIS Position */
865#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */
866
867#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
868#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
869
870#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
871#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
872
873/*@} end of group CMSIS_SCnotSCB */
874
875
876/** \ingroup CMSIS_core_register
877 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
878 \brief Type definitions for the System Timer Registers.
879 @{
880 */
881
882/** \brief Structure type to access the System Timer (SysTick).
883 */
884typedef struct
885{
886 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
887 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
888 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
889 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
890} SysTick_Type;
891
892/* SysTick Control / Status Register Definitions */
893#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
894#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
895
896#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
897#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
898
899#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
900#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
901
902#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
903#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
904
905/* SysTick Reload Register Definitions */
906#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
907#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
908
909/* SysTick Current Register Definitions */
910#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
911#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
912
913/* SysTick Calibration Register Definitions */
914#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
915#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
916
917#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
918#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
919
920#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
921#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
922
923/*@} end of group CMSIS_SysTick */
924
925
926/** \ingroup CMSIS_core_register
927 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
928 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
929 @{
930 */
931
932/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
933 */
934typedef struct
935{
936 __O union
937 {
938 __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
939 __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
940 __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
941 } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
942 uint32_t RESERVED0[864];
943 __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
944 uint32_t RESERVED1[15];
945 __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
946 uint32_t RESERVED2[15];
947 __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
948 uint32_t RESERVED3[29];
949 __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
950 __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
951 __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
952 uint32_t RESERVED4[43];
953 __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
954 __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
955 uint32_t RESERVED5[6];
956 __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
957 __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
958 __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
959 __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
960 __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
961 __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
962 __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
963 __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
964 __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
965 __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
966 __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
967 __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
968} ITM_Type;
969
970/* ITM Trace Privilege Register Definitions */
971#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
972#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
973
974/* ITM Trace Control Register Definitions */
975#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
976#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
977
978#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
979#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
980
981#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
982#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
983
984#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
985#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
986
987#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
988#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
989
990#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
991#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
992
993#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
994#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
995
996#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
997#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
998
999#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
1000#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
1001
1002/* ITM Integration Write Register Definitions */
1003#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
1004#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
1005
1006/* ITM Integration Read Register Definitions */
1007#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
1008#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
1009
1010/* ITM Integration Mode Control Register Definitions */
1011#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
1012#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
1013
1014/* ITM Lock Status Register Definitions */
1015#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
1016#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
1017
1018#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
1019#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
1020
1021#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
1022#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
1023
1024/*@}*/ /* end of group CMSIS_ITM */
1025
1026
1027/** \ingroup CMSIS_core_register
1028 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
1029 \brief Type definitions for the Data Watchpoint and Trace (DWT)
1030 @{
1031 */
1032
1033/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
1034 */
1035typedef struct
1036{
1037 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
1038 __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
1039 __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
1040 __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
1041 __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
1042 __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
1043 __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
1044 __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
1045 __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
1046 __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
1047 __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
1048 uint32_t RESERVED0[1];
1049 __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
1050 __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
1051 __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
1052 uint32_t RESERVED1[1];
1053 __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
1054 __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
1055 __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
1056 uint32_t RESERVED2[1];
1057 __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
1058 __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
1059 __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
1060 uint32_t RESERVED3[981];
1061 __O uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */
1062 __I uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
1063} DWT_Type;
1064
1065/* DWT Control Register Definitions */
1066#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
1067#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
1068
1069#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
1070#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
1071
1072#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
1073#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
1074
1075#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
1076#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
1077
1078#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
1079#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
1080
1081#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
1082#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
1083
1084#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
1085#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
1086
1087#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
1088#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
1089
1090#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
1091#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
1092
1093#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
1094#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
1095
1096#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
1097#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
1098
1099#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
1100#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
1101
1102#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
1103#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
1104
1105#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
1106#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
1107
1108#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
1109#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
1110
1111#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
1112#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
1113
1114#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
1115#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
1116
1117#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
1118#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
1119
1120/* DWT CPI Count Register Definitions */
1121#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
1122#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
1123
1124/* DWT Exception Overhead Count Register Definitions */
1125#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
1126#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
1127
1128/* DWT Sleep Count Register Definitions */
1129#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
1130#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
1131
1132/* DWT LSU Count Register Definitions */
1133#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
1134#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
1135
1136/* DWT Folded-instruction Count Register Definitions */
1137#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
1138#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
1139
1140/* DWT Comparator Mask Register Definitions */
1141#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
1142#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
1143
1144/* DWT Comparator Function Register Definitions */
1145#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
1146#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
1147
1148#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
1149#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
1150
1151#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
1152#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
1153
1154#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
1155#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
1156
1157#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
1158#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
1159
1160#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
1161#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
1162
1163#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
1164#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
1165
1166#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
1167#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
1168
1169#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
1170#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
1171
1172/*@}*/ /* end of group CMSIS_DWT */
1173
1174
1175/** \ingroup CMSIS_core_register
1176 \defgroup CMSIS_TPI Trace Port Interface (TPI)
1177 \brief Type definitions for the Trace Port Interface (TPI)
1178 @{
1179 */
1180
1181/** \brief Structure type to access the Trace Port Interface Register (TPI).
1182 */
1183typedef struct
1184{
1185 __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
1186 __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
1187 uint32_t RESERVED0[2];
1188 __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
1189 uint32_t RESERVED1[55];
1190 __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
1191 uint32_t RESERVED2[131];
1192 __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
1193 __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
1194 __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
1195 uint32_t RESERVED3[759];
1196 __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
1197 __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
1198 __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
1199 uint32_t RESERVED4[1];
1200 __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
1201 __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
1202 __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
1203 uint32_t RESERVED5[39];
1204 __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
1205 __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
1206 uint32_t RESERVED7[8];
1207 __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
1208 __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
1209} TPI_Type;
1210
1211/* TPI Asynchronous Clock Prescaler Register Definitions */
1212#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
1213#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
1214
1215/* TPI Selected Pin Protocol Register Definitions */
1216#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
1217#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
1218
1219/* TPI Formatter and Flush Status Register Definitions */
1220#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
1221#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
1222
1223#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
1224#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
1225
1226#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
1227#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
1228
1229#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
1230#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
1231
1232/* TPI Formatter and Flush Control Register Definitions */
1233#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
1234#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
1235
1236#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
1237#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
1238
1239/* TPI TRIGGER Register Definitions */
1240#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
1241#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
1242
1243/* TPI Integration ETM Data Register Definitions (FIFO0) */
1244#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
1245#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
1246
1247#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
1248#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
1249
1250#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
1251#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
1252
1253#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
1254#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
1255
1256#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
1257#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
1258
1259#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
1260#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
1261
1262#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
1263#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
1264
1265/* TPI ITATBCTR2 Register Definitions */
1266#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
1267#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
1268
1269/* TPI Integration ITM Data Register Definitions (FIFO1) */
1270#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
1271#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
1272
1273#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
1274#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
1275
1276#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
1277#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
1278
1279#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
1280#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
1281
1282#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
1283#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
1284
1285#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
1286#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
1287
1288#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
1289#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
1290
1291/* TPI ITATBCTR0 Register Definitions */
1292#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
1293#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
1294
1295/* TPI Integration Mode Control Register Definitions */
1296#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
1297#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
1298
1299/* TPI DEVID Register Definitions */
1300#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
1301#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
1302
1303#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
1304#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
1305
1306#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
1307#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
1308
1309#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
1310#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
1311
1312#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
1313#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
1314
1315#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
1316#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
1317
1318/* TPI DEVTYPE Register Definitions */
1319#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
1320#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
1321
1322#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
1323#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
1324
1325/*@}*/ /* end of group CMSIS_TPI */
1326
1327
1328#if (__MPU_PRESENT == 1)
1329/** \ingroup CMSIS_core_register
1330 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
1331 \brief Type definitions for the Memory Protection Unit (MPU)
1332 @{
1333 */
1334
1335/** \brief Structure type to access the Memory Protection Unit (MPU).
1336 */
1337typedef struct
1338{
1339 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
1340 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
1341 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
1342 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
1343 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
1344 __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
1345 __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
1346 __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
1347 __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
1348 __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
1349 __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
1350} MPU_Type;
1351
1352/* MPU Type Register */
1353#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
1354#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
1355
1356#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
1357#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
1358
1359#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
1360#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
1361
1362/* MPU Control Register */
1363#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
1364#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
1365
1366#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
1367#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
1368
1369#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
1370#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
1371
1372/* MPU Region Number Register */
1373#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
1374#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
1375
1376/* MPU Region Base Address Register */
1377#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
1378#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
1379
1380#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
1381#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
1382
1383#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
1384#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
1385
1386/* MPU Region Attribute and Size Register */
1387#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
1388#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
1389
1390#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
1391#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
1392
1393#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
1394#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
1395
1396#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
1397#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
1398
1399#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
1400#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
1401
1402#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
1403#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
1404
1405#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
1406#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
1407
1408#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
1409#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
1410
1411#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
1412#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
1413
1414#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
1415#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
1416
1417/*@} end of group CMSIS_MPU */
1418#endif
1419
1420
1421#if (__FPU_PRESENT == 1)
1422/** \ingroup CMSIS_core_register
1423 \defgroup CMSIS_FPU Floating Point Unit (FPU)
1424 \brief Type definitions for the Floating Point Unit (FPU)
1425 @{
1426 */
1427
1428/** \brief Structure type to access the Floating Point Unit (FPU).
1429 */
1430typedef struct
1431{
1432 uint32_t RESERVED0[1];
1433 __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
1434 __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
1435 __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
1436 __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
1437 __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
1438 __I uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */
1439} FPU_Type;
1440
1441/* Floating-Point Context Control Register */
1442#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */
1443#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
1444
1445#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */
1446#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
1447
1448#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */
1449#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
1450
1451#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */
1452#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
1453
1454#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */
1455#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
1456
1457#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */
1458#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
1459
1460#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */
1461#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
1462
1463#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */
1464#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
1465
1466#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */
1467#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
1468
1469/* Floating-Point Context Address Register */
1470#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */
1471#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
1472
1473/* Floating-Point Default Status Control Register */
1474#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */
1475#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
1476
1477#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */
1478#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
1479
1480#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */
1481#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
1482
1483#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */
1484#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
1485
1486/* Media and FP Feature Register 0 */
1487#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */
1488#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
1489
1490#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */
1491#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
1492
1493#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */
1494#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
1495
1496#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */
1497#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
1498
1499#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */
1500#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
1501
1502#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */
1503#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
1504
1505#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */
1506#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
1507
1508#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */
1509#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
1510
1511/* Media and FP Feature Register 1 */
1512#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */
1513#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
1514
1515#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */
1516#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
1517
1518#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */
1519#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
1520
1521#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */
1522#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
1523
1524/* Media and FP Feature Register 2 */
1525
1526/*@} end of group CMSIS_FPU */
1527#endif
1528
1529
1530/** \ingroup CMSIS_core_register
1531 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
1532 \brief Type definitions for the Core Debug Registers
1533 @{
1534 */
1535
1536/** \brief Structure type to access the Core Debug Register (CoreDebug).
1537 */
1538typedef struct
1539{
1540 __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
1541 __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
1542 __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
1543 __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
1544} CoreDebug_Type;
1545
1546/* Debug Halting Control and Status Register */
1547#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
1548#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
1549
1550#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
1551#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
1552
1553#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
1554#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
1555
1556#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
1557#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
1558
1559#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
1560#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
1561
1562#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
1563#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
1564
1565#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
1566#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
1567
1568#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
1569#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
1570
1571#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
1572#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
1573
1574#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
1575#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
1576
1577#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
1578#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
1579
1580#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
1581#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
1582
1583/* Debug Core Register Selector Register */
1584#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
1585#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
1586
1587#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
1588#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
1589
1590/* Debug Exception and Monitor Control Register */
1591#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
1592#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
1593
1594#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
1595#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
1596
1597#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
1598#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
1599
1600#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
1601#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
1602
1603#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
1604#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
1605
1606#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
1607#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
1608
1609#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
1610#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
1611
1612#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
1613#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
1614
1615#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
1616#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
1617
1618#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
1619#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
1620
1621#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
1622#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
1623
1624#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
1625#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
1626
1627#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
1628#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
1629
1630/*@} end of group CMSIS_CoreDebug */
1631
1632
1633/** \ingroup CMSIS_core_register
1634 \defgroup CMSIS_core_base Core Definitions
1635 \brief Definitions for base addresses, unions, and structures.
1636 @{
1637 */
1638
1639/* Memory mapping of Cortex-M4 Hardware */
1640#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
1641#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
1642#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
1643#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
1644#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
1645#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
1646#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
1647#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
1648
1649#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
1650#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
1651#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
1652#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
1653#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
1654#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
1655#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
1656#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
1657
1658#if (__MPU_PRESENT == 1)
1659 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
1660 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
1661#endif
1662
1663#if (__FPU_PRESENT == 1)
1664 #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
1665 #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
1666#endif
1667
1668/*@} */
1669
1670
1671
1672/*******************************************************************************
1673 * Hardware Abstraction Layer
1674 Core Function Interface contains:
1675 - Core NVIC Functions
1676 - Core SysTick Functions
1677 - Core Debug Functions
1678 - Core Register Access Functions
1679 ******************************************************************************/
1680/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
1681*/
1682
1683
1684
1685/* ########################## NVIC functions #################################### */
1686/** \ingroup CMSIS_Core_FunctionInterface
1687 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
1688 \brief Functions that manage interrupts and exceptions via the NVIC.
1689 @{
1690 */
1691
1692/** \brief Set Priority Grouping
1693
1694 The function sets the priority grouping field using the required unlock sequence.
1695 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
1696 Only values from 0..7 are used.
1697 In case of a conflict between priority grouping and available
1698 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
1699
1700 \param [in] PriorityGroup Priority grouping field.
1701 */
1702__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
1703{
1704 uint32_t reg_value;
1705 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1706
1707 reg_value = SCB->AIRCR; /* read old register configuration */
1708 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
1709 reg_value = (reg_value |
1710 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
1711 (PriorityGroupTmp << 8) ); /* Insert write key and priorty group */
1712 SCB->AIRCR = reg_value;
1713}
1714
1715
1716/** \brief Get Priority Grouping
1717
1718 The function reads the priority grouping field from the NVIC Interrupt Controller.
1719
1720 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
1721 */
1722__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
1723{
1724 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
1725}
1726
1727
1728/** \brief Enable External Interrupt
1729
1730 The function enables a device-specific interrupt in the NVIC interrupt controller.
1731
1732 \param [in] IRQn External interrupt number. Value cannot be negative.
1733 */
1734__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
1735{
1736 NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
1737}
1738
1739
1740/** \brief Disable External Interrupt
1741
1742 The function disables a device-specific interrupt in the NVIC interrupt controller.
1743
1744 \param [in] IRQn External interrupt number. Value cannot be negative.
1745 */
1746__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
1747{
1748 NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
1749}
1750
1751
1752/** \brief Get Pending Interrupt
1753
1754 The function reads the pending register in the NVIC and returns the pending bit
1755 for the specified interrupt.
1756
1757 \param [in] IRQn Interrupt number.
1758
1759 \return 0 Interrupt status is not pending.
1760 \return 1 Interrupt status is pending.
1761 */
1762__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
1763{
1764 return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1765}
1766
1767
1768/** \brief Set Pending Interrupt
1769
1770 The function sets the pending bit of an external interrupt.
1771
1772 \param [in] IRQn Interrupt number. Value cannot be negative.
1773 */
1774__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
1775{
1776 NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
1777}
1778
1779
1780/** \brief Clear Pending Interrupt
1781
1782 The function clears the pending bit of an external interrupt.
1783
1784 \param [in] IRQn External interrupt number. Value cannot be negative.
1785 */
1786__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
1787{
1788 NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
1789}
1790
1791
1792/** \brief Get Active Interrupt
1793
1794 The function reads the active register in NVIC and returns the active bit.
1795
1796 \param [in] IRQn Interrupt number.
1797
1798 \return 0 Interrupt status is not active.
1799 \return 1 Interrupt status is active.
1800 */
1801__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
1802{
1803 return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1804}
1805
1806
1807/** \brief Set Interrupt Priority
1808
1809 The function sets the priority of an interrupt.
1810
1811 \note The priority cannot be set for every core interrupt.
1812
1813 \param [in] IRQn Interrupt number.
1814 \param [in] priority Priority to set.
1815 */
1816__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
1817{
1818 if((int32_t)IRQn < 0) {
1819 SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
1820 }
1821 else {
1822 NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
1823 }
1824}
1825
1826
1827/** \brief Get Interrupt Priority
1828
1829 The function reads the priority of an interrupt. The interrupt
1830 number can be positive to specify an external (device specific)
1831 interrupt, or negative to specify an internal (core) interrupt.
1832
1833
1834 \param [in] IRQn Interrupt number.
1835 \return Interrupt Priority. Value is aligned automatically to the implemented
1836 priority bits of the microcontroller.
1837 */
1838__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
1839{
1840
1841 if((int32_t)IRQn < 0) {
1842 return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
1843 }
1844 else {
1845 return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS)));
1846 }
1847}
1848
1849
1850/** \brief Encode Priority
1851
1852 The function encodes the priority for an interrupt with the given priority group,
1853 preemptive priority value, and subpriority value.
1854 In case of a conflict between priority grouping and available
1855 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
1856
1857 \param [in] PriorityGroup Used priority group.
1858 \param [in] PreemptPriority Preemptive priority value (starting from 0).
1859 \param [in] SubPriority Subpriority value (starting from 0).
1860 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
1861 */
1862__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
1863{
1864 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1865 uint32_t PreemptPriorityBits;
1866 uint32_t SubPriorityBits;
1867
1868 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
1869 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
1870
1871 return (
1872 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
1873 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
1874 );
1875}
1876
1877
1878/** \brief Decode Priority
1879
1880 The function decodes an interrupt priority value with a given priority group to
1881 preemptive priority value and subpriority value.
1882 In case of a conflict between priority grouping and available
1883 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
1884
1885 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
1886 \param [in] PriorityGroup Used priority group.
1887 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
1888 \param [out] pSubPriority Subpriority value (starting from 0).
1889 */
1890__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
1891{
1892 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1893 uint32_t PreemptPriorityBits;
1894 uint32_t SubPriorityBits;
1895
1896 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
1897 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
1898
1899 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
1900 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
1901}
1902
1903
1904/** \brief System Reset
1905
1906 The function initiates a system reset request to reset the MCU.
1907 */
1908__STATIC_INLINE void NVIC_SystemReset(void)
1909{
1910 __DSB(); /* Ensure all outstanding memory accesses included
1911 buffered write are completed before reset */
1912 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
1913 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
1914 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
1915 __DSB(); /* Ensure completion of memory access */
1916 while(1) { __NOP(); } /* wait until reset */
1917}
1918
1919/*@} end of CMSIS_Core_NVICFunctions */
1920
1921
1922/* ########################## FPU functions #################################### */
1923/** \ingroup CMSIS_Core_FunctionInterface
1924 \defgroup CMSIS_Core_FpuFunctions FPU Functions
1925 \brief Function that provides FPU type.
1926 @{
1927 */
1928
1929/**
1930 \fn uint32_t SCB_GetFPUType(void)
1931 \brief get FPU type
1932 \returns
1933 - \b 0: No FPU
1934 - \b 1: Single precision FPU
1935 - \b 2: Double + Single precision FPU
1936 */
1937__STATIC_INLINE uint32_t SCB_GetFPUType(void)
1938{
1939 uint32_t mvfr0;
1940
1941 mvfr0 = SCB->MVFR0;
1942 if ((mvfr0 & 0x00000FF0UL) == 0x220UL) {
1943 return 2UL; // Double + Single precision FPU
1944 } else if ((mvfr0 & 0x00000FF0UL) == 0x020UL) {
1945 return 1UL; // Single precision FPU
1946 } else {
1947 return 0UL; // No FPU
1948 }
1949}
1950
1951
1952/*@} end of CMSIS_Core_FpuFunctions */
1953
1954
1955
1956/* ########################## Cache functions #################################### */
1957/** \ingroup CMSIS_Core_FunctionInterface
1958 \defgroup CMSIS_Core_CacheFunctions Cache Functions
1959 \brief Functions that configure Instruction and Data cache.
1960 @{
1961 */
1962
1963/* Cache Size ID Register Macros */
1964#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
1965#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
1966#define CCSIDR_LSSHIFT(x) (((x) & SCB_CCSIDR_LINESIZE_Msk ) /*>> SCB_CCSIDR_LINESIZE_Pos*/ )
1967
1968
1969/** \brief Enable I-Cache
1970
1971 The function turns on I-Cache
1972 */
1973__STATIC_INLINE void SCB_EnableICache (void)
1974{
1975 #if (__ICACHE_PRESENT == 1)
1976 __DSB();
1977 __ISB();
1978 SCB->ICIALLU = 0UL; // invalidate I-Cache
1979 SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; // enable I-Cache
1980 __DSB();
1981 __ISB();
1982 #endif
1983}
1984
1985
1986/** \brief Disable I-Cache
1987
1988 The function turns off I-Cache
1989 */
1990__STATIC_INLINE void SCB_DisableICache (void)
1991{
1992 #if (__ICACHE_PRESENT == 1)
1993 __DSB();
1994 __ISB();
1995 SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; // disable I-Cache
1996 SCB->ICIALLU = 0UL; // invalidate I-Cache
1997 __DSB();
1998 __ISB();
1999 #endif
2000}
2001
2002
2003/** \brief Invalidate I-Cache
2004
2005 The function invalidates I-Cache
2006 */
2007__STATIC_INLINE void SCB_InvalidateICache (void)
2008{
2009 #if (__ICACHE_PRESENT == 1)
2010 __DSB();
2011 __ISB();
2012 SCB->ICIALLU = 0UL;
2013 __DSB();
2014 __ISB();
2015 #endif
2016}
2017
2018
2019/** \brief Enable D-Cache
2020
2021 The function turns on D-Cache
2022 */
2023__STATIC_INLINE void SCB_EnableDCache (void)
2024{
2025 #if (__DCACHE_PRESENT == 1)
2026 uint32_t ccsidr, sshift, wshift, sw;
2027 uint32_t sets, ways;
2028
2029 SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache
2030 ccsidr = SCB->CCSIDR;
2031 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
2032 sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
2033 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
2034 wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
2035
2036 __DSB();
2037
2038 do { // invalidate D-Cache
2039 uint32_t tmpways = ways;
2040 do {
2041 sw = ((tmpways << wshift) | (sets << sshift));
2042 SCB->DCISW = sw;
2043 } while(tmpways--);
2044 } while(sets--);
2045 __DSB();
2046
2047 SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; // enable D-Cache
2048
2049 __DSB();
2050 __ISB();
2051 #endif
2052}
2053
2054
2055/** \brief Disable D-Cache
2056
2057 The function turns off D-Cache
2058 */
2059__STATIC_INLINE void SCB_DisableDCache (void)
2060{
2061 #if (__DCACHE_PRESENT == 1)
2062 uint32_t ccsidr, sshift, wshift, sw;
2063 uint32_t sets, ways;
2064
2065 SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache
2066 ccsidr = SCB->CCSIDR;
2067 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
2068 sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
2069 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
2070 wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
2071
2072 __DSB();
2073
2074 SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; // disable D-Cache
2075
2076 do { // clean & invalidate D-Cache
2077 uint32_t tmpways = ways;
2078 do {
2079 sw = ((tmpways << wshift) | (sets << sshift));
2080 SCB->DCCISW = sw;
2081 } while(tmpways--);
2082 } while(sets--);
2083
2084
2085 __DSB();
2086 __ISB();
2087 #endif
2088}
2089
2090
2091/** \brief Invalidate D-Cache
2092
2093 The function invalidates D-Cache
2094 */
2095__STATIC_INLINE void SCB_InvalidateDCache (void)
2096{
2097 #if (__DCACHE_PRESENT == 1)
2098 uint32_t ccsidr, sshift, wshift, sw;
2099 uint32_t sets, ways;
2100
2101 SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache
2102 ccsidr = SCB->CCSIDR;
2103 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
2104 sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
2105 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
2106 wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
2107
2108 __DSB();
2109
2110 do { // invalidate D-Cache
2111 uint32_t tmpways = ways;
2112 do {
2113 sw = ((tmpways << wshift) | (sets << sshift));
2114 SCB->DCISW = sw;
2115 } while(tmpways--);
2116 } while(sets--);
2117
2118 __DSB();
2119 __ISB();
2120 #endif
2121}
2122
2123
2124/** \brief Clean D-Cache
2125
2126 The function cleans D-Cache
2127 */
2128__STATIC_INLINE void SCB_CleanDCache (void)
2129{
2130 #if (__DCACHE_PRESENT == 1)
2131 uint32_t ccsidr, sshift, wshift, sw;
2132 uint32_t sets, ways;
2133
2134 SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache
2135 ccsidr = SCB->CCSIDR;
2136 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
2137 sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
2138 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
2139 wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
2140
2141 __DSB();
2142
2143 do { // clean D-Cache
2144 uint32_t tmpways = ways;
2145 do {
2146 sw = ((tmpways << wshift) | (sets << sshift));
2147 SCB->DCCSW = sw;
2148 } while(tmpways--);
2149 } while(sets--);
2150
2151 __DSB();
2152 __ISB();
2153 #endif
2154}
2155
2156
2157/** \brief Clean & Invalidate D-Cache
2158
2159 The function cleans and Invalidates D-Cache
2160 */
2161__STATIC_INLINE void SCB_CleanInvalidateDCache (void)
2162{
2163 #if (__DCACHE_PRESENT == 1)
2164 uint32_t ccsidr, sshift, wshift, sw;
2165 uint32_t sets, ways;
2166
2167 SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache
2168 ccsidr = SCB->CCSIDR;
2169 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
2170 sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
2171 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
2172 wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
2173
2174 __DSB();
2175
2176 do { // clean & invalidate D-Cache
2177 uint32_t tmpways = ways;
2178 do {
2179 sw = ((tmpways << wshift) | (sets << sshift));
2180 SCB->DCCISW = sw;
2181 } while(tmpways--);
2182 } while(sets--);
2183
2184 __DSB();
2185 __ISB();
2186 #endif
2187}
2188
2189
2190/**
2191 \fn void SCB_InvalidateDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
2192 \brief D-Cache Invalidate by address
2193 \param[in] addr address (aligned to 32-byte boundary)
2194 \param[in] dsize size of memory block (in number of bytes)
2195*/
2196__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
2197{
2198 #if (__DCACHE_PRESENT == 1)
2199 int32_t op_size = dsize;
2200 uint32_t op_addr = (uint32_t)addr;
2201 uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
2202
2203 __DSB();
2204
2205 while (op_size > 0) {
2206 SCB->DCIMVAC = op_addr;
2207 op_addr += linesize;
2208 op_size -= (int32_t)linesize;
2209 }
2210
2211 __DSB();
2212 __ISB();
2213 #endif
2214}
2215
2216
2217/**
2218 \fn void SCB_CleanDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
2219 \brief D-Cache Clean by address
2220 \param[in] addr address (aligned to 32-byte boundary)
2221 \param[in] dsize size of memory block (in number of bytes)
2222*/
2223__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
2224{
2225 #if (__DCACHE_PRESENT == 1)
2226 int32_t op_size = dsize;
2227 uint32_t op_addr = (uint32_t) addr;
2228 uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
2229
2230 __DSB();
2231
2232 while (op_size > 0) {
2233 SCB->DCCMVAC = op_addr;
2234 op_addr += linesize;
2235 op_size -= (int32_t)linesize;
2236 }
2237
2238 __DSB();
2239 __ISB();
2240 #endif
2241}
2242
2243
2244/**
2245 \fn void SCB_CleanInvalidateDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
2246 \brief D-Cache Clean and Invalidate by address
2247 \param[in] addr address (aligned to 32-byte boundary)
2248 \param[in] dsize size of memory block (in number of bytes)
2249*/
2250__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
2251{
2252 #if (__DCACHE_PRESENT == 1)
2253 int32_t op_size = dsize;
2254 uint32_t op_addr = (uint32_t) addr;
2255 uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
2256
2257 __DSB();
2258
2259 while (op_size > 0) {
2260 SCB->DCCIMVAC = op_addr;
2261 op_addr += linesize;
2262 op_size -= (int32_t)linesize;
2263 }
2264
2265 __DSB();
2266 __ISB();
2267 #endif
2268}
2269
2270
2271/*@} end of CMSIS_Core_CacheFunctions */
2272
2273
2274
2275/* ################################## SysTick function ############################################ */
2276/** \ingroup CMSIS_Core_FunctionInterface
2277 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
2278 \brief Functions that configure the System.
2279 @{
2280 */
2281
2282#if (__Vendor_SysTickConfig == 0)
2283
2284/** \brief System Tick Configuration
2285
2286 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
2287 Counter is in free running mode to generate periodic interrupts.
2288
2289 \param [in] ticks Number of ticks between two interrupts.
2290
2291 \return 0 Function succeeded.
2292 \return 1 Function failed.
2293
2294 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
2295 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
2296 must contain a vendor-specific implementation of this function.
2297
2298 */
2299__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
2300{
2301 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
2302
2303 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
2304 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
2305 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
2306 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
2307 SysTick_CTRL_TICKINT_Msk |
2308 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
2309 return (0UL); /* Function successful */
2310}
2311
2312#endif
2313
2314/*@} end of CMSIS_Core_SysTickFunctions */
2315
2316
2317
2318/* ##################################### Debug In/Output function ########################################### */
2319/** \ingroup CMSIS_Core_FunctionInterface
2320 \defgroup CMSIS_core_DebugFunctions ITM Functions
2321 \brief Functions that access the ITM debug interface.
2322 @{
2323 */
2324
2325extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
2326#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
2327
2328
2329/** \brief ITM Send Character
2330
2331 The function transmits a character via the ITM channel 0, and
2332 \li Just returns when no debugger is connected that has booked the output.
2333 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
2334
2335 \param [in] ch Character to transmit.
2336
2337 \returns Character to transmit.
2338 */
2339__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
2340{
2341 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
2342 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
2343 {
2344 while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
2345 ITM->PORT[0].u8 = (uint8_t)ch;
2346 }
2347 return (ch);
2348}
2349
2350
2351/** \brief ITM Receive Character
2352
2353 The function inputs a character via the external variable \ref ITM_RxBuffer.
2354
2355 \return Received character.
2356 \return -1 No character pending.
2357 */
2358__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
2359 int32_t ch = -1; /* no character available */
2360
2361 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
2362 ch = ITM_RxBuffer;
2363 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
2364 }
2365
2366 return (ch);
2367}
2368
2369
2370/** \brief ITM Check Character
2371
2372 The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
2373
2374 \return 0 No character available.
2375 \return 1 Character available.
2376 */
2377__STATIC_INLINE int32_t ITM_CheckChar (void) {
2378
2379 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
2380 return (0); /* no character available */
2381 } else {
2382 return (1); /* character available */
2383 }
2384}
2385
2386/*@} end of CMSIS_core_DebugFunctions */
2387
2388
2389
2390
2391#ifdef __cplusplus
2392}
2393#endif
2394
2395#endif /* __CORE_CM7_H_DEPENDANT */
2396
2397#endif /* __CMSIS_GENERIC */
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