1 | /**************************************************************************//**
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2 | * @file core_cm4_simd.h
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3 | * @brief CMSIS Cortex-M4 SIMD Header File
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4 | * @version V3.20
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5 | * @date 25. February 2013
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6 | *
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7 | * @note
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8 | *
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9 | ******************************************************************************/
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10 | /* Copyright (c) 2009 - 2013 ARM LIMITED
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11 |
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12 | All rights reserved.
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13 | Redistribution and use in source and binary forms, with or without
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14 | modification, are permitted provided that the following conditions are met:
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15 | - Redistributions of source code must retain the above copyright
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16 | notice, this list of conditions and the following disclaimer.
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17 | - Redistributions in binary form must reproduce the above copyright
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18 | notice, this list of conditions and the following disclaimer in the
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19 | documentation and/or other materials provided with the distribution.
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20 | - Neither the name of ARM nor the names of its contributors may be used
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21 | to endorse or promote products derived from this software without
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22 | specific prior written permission.
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23 | *
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24 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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25 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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26 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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27 | ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
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28 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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29 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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30 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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31 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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32 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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33 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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34 | POSSIBILITY OF SUCH DAMAGE.
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35 | ---------------------------------------------------------------------------*/
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36 |
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37 |
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38 | #ifdef __cplusplus
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39 | extern "C" {
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40 | #endif
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41 |
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42 | #ifndef __CORE_CM4_SIMD_H
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43 | #define __CORE_CM4_SIMD_H
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44 |
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45 |
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46 | /*******************************************************************************
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47 | * Hardware Abstraction Layer
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48 | ******************************************************************************/
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49 |
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50 |
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51 | /* ################### Compiler specific Intrinsics ########################### */
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52 | /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
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53 | Access to dedicated SIMD instructions
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54 | @{
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55 | */
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56 |
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57 | #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
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58 | /* ARM armcc specific functions */
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59 |
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60 | /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
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61 | #define __SADD8 __sadd8
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62 | #define __QADD8 __qadd8
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63 | #define __SHADD8 __shadd8
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64 | #define __UADD8 __uadd8
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65 | #define __UQADD8 __uqadd8
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66 | #define __UHADD8 __uhadd8
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67 | #define __SSUB8 __ssub8
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68 | #define __QSUB8 __qsub8
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69 | #define __SHSUB8 __shsub8
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70 | #define __USUB8 __usub8
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71 | #define __UQSUB8 __uqsub8
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72 | #define __UHSUB8 __uhsub8
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73 | #define __SADD16 __sadd16
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74 | #define __QADD16 __qadd16
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75 | #define __SHADD16 __shadd16
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76 | #define __UADD16 __uadd16
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77 | #define __UQADD16 __uqadd16
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78 | #define __UHADD16 __uhadd16
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79 | #define __SSUB16 __ssub16
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80 | #define __QSUB16 __qsub16
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81 | #define __SHSUB16 __shsub16
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82 | #define __USUB16 __usub16
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83 | #define __UQSUB16 __uqsub16
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84 | #define __UHSUB16 __uhsub16
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85 | #define __SASX __sasx
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86 | #define __QASX __qasx
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87 | #define __SHASX __shasx
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88 | #define __UASX __uasx
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89 | #define __UQASX __uqasx
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90 | #define __UHASX __uhasx
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91 | #define __SSAX __ssax
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92 | #define __QSAX __qsax
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93 | #define __SHSAX __shsax
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94 | #define __USAX __usax
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95 | #define __UQSAX __uqsax
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96 | #define __UHSAX __uhsax
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97 | #define __USAD8 __usad8
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98 | #define __USADA8 __usada8
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99 | #define __SSAT16 __ssat16
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100 | #define __USAT16 __usat16
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101 | #define __UXTB16 __uxtb16
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102 | #define __UXTAB16 __uxtab16
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103 | #define __SXTB16 __sxtb16
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104 | #define __SXTAB16 __sxtab16
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105 | #define __SMUAD __smuad
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106 | #define __SMUADX __smuadx
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107 | #define __SMLAD __smlad
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108 | #define __SMLADX __smladx
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109 | #define __SMLALD __smlald
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110 | #define __SMLALDX __smlaldx
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111 | #define __SMUSD __smusd
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112 | #define __SMUSDX __smusdx
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113 | #define __SMLSD __smlsd
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114 | #define __SMLSDX __smlsdx
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115 | #define __SMLSLD __smlsld
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116 | #define __SMLSLDX __smlsldx
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117 | #define __SEL __sel
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118 | #define __QADD __qadd
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119 | #define __QSUB __qsub
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120 |
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121 | #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
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122 | ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
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123 |
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124 | #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
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125 | ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
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126 |
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127 | #define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
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128 | ((int64_t)(ARG3) << 32) ) >> 32))
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129 |
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130 | /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
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131 |
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132 |
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133 |
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134 | #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
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135 | /* IAR iccarm specific functions */
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136 |
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137 | /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
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138 | #include <cmsis_iar.h>
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139 |
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140 | /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
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141 |
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142 |
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143 |
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144 | #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
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145 | /* TI CCS specific functions */
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146 |
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147 | /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
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148 | #include <cmsis_ccs.h>
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149 |
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150 | /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
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151 |
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152 |
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153 |
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154 | #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
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155 | /* GNU gcc specific functions */
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156 |
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157 | /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
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158 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
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159 | {
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160 | uint32_t result;
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161 |
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162 | __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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163 | return(result);
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164 | }
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165 |
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166 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
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167 | {
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168 | uint32_t result;
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169 |
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170 | __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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171 | return(result);
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172 | }
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173 |
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174 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
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175 | {
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176 | uint32_t result;
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177 |
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178 | __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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179 | return(result);
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180 | }
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181 |
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182 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
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183 | {
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184 | uint32_t result;
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185 |
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186 | __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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187 | return(result);
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188 | }
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189 |
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190 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
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191 | {
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192 | uint32_t result;
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193 |
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194 | __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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195 | return(result);
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196 | }
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197 |
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198 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
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199 | {
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200 | uint32_t result;
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201 |
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202 | __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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203 | return(result);
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204 | }
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205 |
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206 |
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207 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
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208 | {
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209 | uint32_t result;
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210 |
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211 | __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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212 | return(result);
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213 | }
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214 |
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215 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
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216 | {
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217 | uint32_t result;
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218 |
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219 | __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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220 | return(result);
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221 | }
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222 |
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223 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
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224 | {
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225 | uint32_t result;
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226 |
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227 | __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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228 | return(result);
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229 | }
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230 |
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231 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
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232 | {
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233 | uint32_t result;
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234 |
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235 | __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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236 | return(result);
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237 | }
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238 |
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239 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
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240 | {
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241 | uint32_t result;
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242 |
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243 | __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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244 | return(result);
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245 | }
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246 |
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247 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
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248 | {
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249 | uint32_t result;
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250 |
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251 | __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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252 | return(result);
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253 | }
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254 |
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255 |
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256 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
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257 | {
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258 | uint32_t result;
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259 |
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260 | __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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261 | return(result);
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262 | }
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263 |
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264 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
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265 | {
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266 | uint32_t result;
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267 |
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268 | __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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269 | return(result);
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270 | }
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271 |
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272 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
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273 | {
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274 | uint32_t result;
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275 |
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276 | __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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277 | return(result);
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278 | }
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279 |
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280 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
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281 | {
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282 | uint32_t result;
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283 |
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284 | __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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285 | return(result);
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286 | }
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287 |
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288 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
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289 | {
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290 | uint32_t result;
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291 |
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292 | __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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293 | return(result);
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294 | }
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295 |
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296 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
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297 | {
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298 | uint32_t result;
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299 |
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300 | __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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301 | return(result);
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302 | }
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303 |
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304 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
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305 | {
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306 | uint32_t result;
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307 |
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308 | __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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309 | return(result);
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310 | }
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311 |
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312 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
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313 | {
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314 | uint32_t result;
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315 |
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316 | __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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317 | return(result);
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318 | }
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319 |
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320 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
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321 | {
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322 | uint32_t result;
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323 |
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324 | __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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325 | return(result);
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326 | }
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327 |
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328 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
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329 | {
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330 | uint32_t result;
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331 |
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332 | __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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333 | return(result);
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334 | }
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335 |
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336 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
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337 | {
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338 | uint32_t result;
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339 |
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340 | __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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341 | return(result);
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342 | }
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343 |
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344 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
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345 | {
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346 | uint32_t result;
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347 |
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348 | __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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349 | return(result);
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350 | }
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351 |
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352 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
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353 | {
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354 | uint32_t result;
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355 |
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356 | __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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357 | return(result);
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358 | }
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359 |
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360 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
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361 | {
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362 | uint32_t result;
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363 |
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364 | __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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365 | return(result);
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366 | }
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367 |
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368 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
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369 | {
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370 | uint32_t result;
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371 |
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372 | __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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373 | return(result);
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374 | }
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375 |
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376 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
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377 | {
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378 | uint32_t result;
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379 |
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380 | __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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381 | return(result);
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382 | }
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383 |
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384 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
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385 | {
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386 | uint32_t result;
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387 |
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388 | __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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389 | return(result);
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390 | }
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391 |
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392 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
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393 | {
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394 | uint32_t result;
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395 |
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396 | __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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397 | return(result);
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398 | }
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399 |
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400 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
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401 | {
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402 | uint32_t result;
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403 |
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404 | __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
---|
405 | return(result);
|
---|
406 | }
|
---|
407 |
|
---|
408 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
|
---|
409 | {
|
---|
410 | uint32_t result;
|
---|
411 |
|
---|
412 | __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
---|
413 | return(result);
|
---|
414 | }
|
---|
415 |
|
---|
416 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
|
---|
417 | {
|
---|
418 | uint32_t result;
|
---|
419 |
|
---|
420 | __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
---|
421 | return(result);
|
---|
422 | }
|
---|
423 |
|
---|
424 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
|
---|
425 | {
|
---|
426 | uint32_t result;
|
---|
427 |
|
---|
428 | __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
---|
429 | return(result);
|
---|
430 | }
|
---|
431 |
|
---|
432 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
|
---|
433 | {
|
---|
434 | uint32_t result;
|
---|
435 |
|
---|
436 | __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
---|
437 | return(result);
|
---|
438 | }
|
---|
439 |
|
---|
440 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
|
---|
441 | {
|
---|
442 | uint32_t result;
|
---|
443 |
|
---|
444 | __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
---|
445 | return(result);
|
---|
446 | }
|
---|
447 |
|
---|
448 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
|
---|
449 | {
|
---|
450 | uint32_t result;
|
---|
451 |
|
---|
452 | __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
---|
453 | return(result);
|
---|
454 | }
|
---|
455 |
|
---|
456 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
|
---|
457 | {
|
---|
458 | uint32_t result;
|
---|
459 |
|
---|
460 | __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
|
---|
461 | return(result);
|
---|
462 | }
|
---|
463 |
|
---|
464 | #define __SSAT16(ARG1,ARG2) \
|
---|
465 | ({ \
|
---|
466 | uint32_t __RES, __ARG1 = (ARG1); \
|
---|
467 | __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
|
---|
468 | __RES; \
|
---|
469 | })
|
---|
470 |
|
---|
471 | #define __USAT16(ARG1,ARG2) \
|
---|
472 | ({ \
|
---|
473 | uint32_t __RES, __ARG1 = (ARG1); \
|
---|
474 | __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
|
---|
475 | __RES; \
|
---|
476 | })
|
---|
477 |
|
---|
478 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
|
---|
479 | {
|
---|
480 | uint32_t result;
|
---|
481 |
|
---|
482 | __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
|
---|
483 | return(result);
|
---|
484 | }
|
---|
485 |
|
---|
486 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
|
---|
487 | {
|
---|
488 | uint32_t result;
|
---|
489 |
|
---|
490 | __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
---|
491 | return(result);
|
---|
492 | }
|
---|
493 |
|
---|
494 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
|
---|
495 | {
|
---|
496 | uint32_t result;
|
---|
497 |
|
---|
498 | __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
|
---|
499 | return(result);
|
---|
500 | }
|
---|
501 |
|
---|
502 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
|
---|
503 | {
|
---|
504 | uint32_t result;
|
---|
505 |
|
---|
506 | __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
---|
507 | return(result);
|
---|
508 | }
|
---|
509 |
|
---|
510 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
|
---|
511 | {
|
---|
512 | uint32_t result;
|
---|
513 |
|
---|
514 | __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
---|
515 | return(result);
|
---|
516 | }
|
---|
517 |
|
---|
518 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
|
---|
519 | {
|
---|
520 | uint32_t result;
|
---|
521 |
|
---|
522 | __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
---|
523 | return(result);
|
---|
524 | }
|
---|
525 |
|
---|
526 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
|
---|
527 | {
|
---|
528 | uint32_t result;
|
---|
529 |
|
---|
530 | __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
|
---|
531 | return(result);
|
---|
532 | }
|
---|
533 |
|
---|
534 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
|
---|
535 | {
|
---|
536 | uint32_t result;
|
---|
537 |
|
---|
538 | __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
|
---|
539 | return(result);
|
---|
540 | }
|
---|
541 |
|
---|
542 | #define __SMLALD(ARG1,ARG2,ARG3) \
|
---|
543 | ({ \
|
---|
544 | uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
|
---|
545 | __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
|
---|
546 | (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
|
---|
547 | })
|
---|
548 |
|
---|
549 | #define __SMLALDX(ARG1,ARG2,ARG3) \
|
---|
550 | ({ \
|
---|
551 | uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
|
---|
552 | __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
|
---|
553 | (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
|
---|
554 | })
|
---|
555 |
|
---|
556 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
|
---|
557 | {
|
---|
558 | uint32_t result;
|
---|
559 |
|
---|
560 | __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
---|
561 | return(result);
|
---|
562 | }
|
---|
563 |
|
---|
564 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
|
---|
565 | {
|
---|
566 | uint32_t result;
|
---|
567 |
|
---|
568 | __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
---|
569 | return(result);
|
---|
570 | }
|
---|
571 |
|
---|
572 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
|
---|
573 | {
|
---|
574 | uint32_t result;
|
---|
575 |
|
---|
576 | __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
|
---|
577 | return(result);
|
---|
578 | }
|
---|
579 |
|
---|
580 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
|
---|
581 | {
|
---|
582 | uint32_t result;
|
---|
583 |
|
---|
584 | __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
|
---|
585 | return(result);
|
---|
586 | }
|
---|
587 |
|
---|
588 | #define __SMLSLD(ARG1,ARG2,ARG3) \
|
---|
589 | ({ \
|
---|
590 | uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
|
---|
591 | __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
|
---|
592 | (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
|
---|
593 | })
|
---|
594 |
|
---|
595 | #define __SMLSLDX(ARG1,ARG2,ARG3) \
|
---|
596 | ({ \
|
---|
597 | uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
|
---|
598 | __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
|
---|
599 | (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
|
---|
600 | })
|
---|
601 |
|
---|
602 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
|
---|
603 | {
|
---|
604 | uint32_t result;
|
---|
605 |
|
---|
606 | __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
---|
607 | return(result);
|
---|
608 | }
|
---|
609 |
|
---|
610 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
|
---|
611 | {
|
---|
612 | uint32_t result;
|
---|
613 |
|
---|
614 | __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
---|
615 | return(result);
|
---|
616 | }
|
---|
617 |
|
---|
618 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
|
---|
619 | {
|
---|
620 | uint32_t result;
|
---|
621 |
|
---|
622 | __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
---|
623 | return(result);
|
---|
624 | }
|
---|
625 |
|
---|
626 | #define __PKHBT(ARG1,ARG2,ARG3) \
|
---|
627 | ({ \
|
---|
628 | uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
|
---|
629 | __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
|
---|
630 | __RES; \
|
---|
631 | })
|
---|
632 |
|
---|
633 | #define __PKHTB(ARG1,ARG2,ARG3) \
|
---|
634 | ({ \
|
---|
635 | uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
|
---|
636 | if (ARG3 == 0) \
|
---|
637 | __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
|
---|
638 | else \
|
---|
639 | __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
|
---|
640 | __RES; \
|
---|
641 | })
|
---|
642 |
|
---|
643 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
|
---|
644 | {
|
---|
645 | int32_t result;
|
---|
646 |
|
---|
647 | __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
|
---|
648 | return(result);
|
---|
649 | }
|
---|
650 |
|
---|
651 | /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
|
---|
652 |
|
---|
653 |
|
---|
654 |
|
---|
655 | #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
|
---|
656 | /* TASKING carm specific functions */
|
---|
657 |
|
---|
658 |
|
---|
659 | /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
|
---|
660 | /* not yet supported */
|
---|
661 | /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
|
---|
662 |
|
---|
663 |
|
---|
664 | #endif
|
---|
665 |
|
---|
666 | /*@} end of group CMSIS_SIMD_intrinsics */
|
---|
667 |
|
---|
668 |
|
---|
669 | #endif /* __CORE_CM4_SIMD_H */
|
---|
670 |
|
---|
671 | #ifdef __cplusplus
|
---|
672 | }
|
---|
673 | #endif
|
---|