1 | /**************************************************************************//**
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2 | * @file core_cm4.h
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3 | * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
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4 | * @version V3.20
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5 | * @date 25. February 2013
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6 | *
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7 | * @note
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8 | *
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9 | ******************************************************************************/
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10 | /* Copyright (c) 2009 - 2013 ARM LIMITED
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11 |
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12 | All rights reserved.
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13 | Redistribution and use in source and binary forms, with or without
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14 | modification, are permitted provided that the following conditions are met:
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15 | - Redistributions of source code must retain the above copyright
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16 | notice, this list of conditions and the following disclaimer.
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17 | - Redistributions in binary form must reproduce the above copyright
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18 | notice, this list of conditions and the following disclaimer in the
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19 | documentation and/or other materials provided with the distribution.
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20 | - Neither the name of ARM nor the names of its contributors may be used
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21 | to endorse or promote products derived from this software without
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22 | specific prior written permission.
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23 | *
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24 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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25 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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26 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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27 | ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
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28 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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29 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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30 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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31 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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32 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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33 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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34 | POSSIBILITY OF SUCH DAMAGE.
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35 | ---------------------------------------------------------------------------*/
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36 |
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37 |
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38 | #if defined ( __ICCARM__ )
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39 | #pragma system_include /* treat file as system include file for MISRA check */
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40 | #endif
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41 |
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42 | #ifdef __cplusplus
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43 | extern "C" {
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44 | #endif
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45 |
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46 | #ifndef __CORE_CM4_H_GENERIC
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47 | #define __CORE_CM4_H_GENERIC
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48 |
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49 | /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
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50 | CMSIS violates the following MISRA-C:2004 rules:
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51 |
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52 | \li Required Rule 8.5, object/function definition in header file.<br>
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53 | Function definitions in header files are used to allow 'inlining'.
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54 |
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55 | \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
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56 | Unions are used for effective representation of core registers.
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57 |
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58 | \li Advisory Rule 19.7, Function-like macro defined.<br>
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59 | Function-like macros are used to allow more efficient code.
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60 | */
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61 |
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62 |
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63 | /*******************************************************************************
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64 | * CMSIS definitions
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65 | ******************************************************************************/
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66 | /** \ingroup Cortex_M4
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67 | @{
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68 | */
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69 |
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70 | /* CMSIS CM4 definitions */
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71 | #define __CM4_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
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72 | #define __CM4_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
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73 | #define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \
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74 | __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
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75 |
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76 | #define __CORTEX_M (0x04) /*!< Cortex-M Core */
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77 |
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78 |
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79 | #if defined ( __CC_ARM )
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80 | #define __ASM __asm /*!< asm keyword for ARM Compiler */
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81 | #define __INLINE __inline /*!< inline keyword for ARM Compiler */
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82 | #define __STATIC_INLINE static __inline
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83 |
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84 | #elif defined ( __ICCARM__ )
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85 | #define __ASM __asm /*!< asm keyword for IAR Compiler */
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86 | #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
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87 | #define __STATIC_INLINE static inline
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88 |
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89 | #elif defined ( __TMS470__ )
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90 | #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
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91 | #define __STATIC_INLINE static inline
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92 |
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93 | #elif defined ( __GNUC__ )
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94 | #define __ASM __asm /*!< asm keyword for GNU Compiler */
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95 | #define __INLINE inline /*!< inline keyword for GNU Compiler */
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96 | #define __STATIC_INLINE static inline
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97 |
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98 | #elif defined ( __TASKING__ )
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99 | #define __ASM __asm /*!< asm keyword for TASKING Compiler */
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100 | #define __INLINE inline /*!< inline keyword for TASKING Compiler */
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101 | #define __STATIC_INLINE static inline
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102 |
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103 | #endif
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104 |
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105 | /** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
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106 | */
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107 | #if defined ( __CC_ARM )
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108 | #if defined __TARGET_FPU_VFP
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109 | #if (__FPU_PRESENT == 1)
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110 | #define __FPU_USED 1
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111 | #else
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112 | #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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113 | #define __FPU_USED 0
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114 | #endif
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115 | #else
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116 | #define __FPU_USED 0
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117 | #endif
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118 |
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119 | #elif defined ( __ICCARM__ )
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120 | #if defined __ARMVFP__
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121 | #if (__FPU_PRESENT == 1)
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122 | #define __FPU_USED 1
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123 | #else
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124 | #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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125 | #define __FPU_USED 0
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126 | #endif
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127 | #else
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128 | #define __FPU_USED 0
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129 | #endif
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130 |
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131 | #elif defined ( __TMS470__ )
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132 | #if defined __TI_VFP_SUPPORT__
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133 | #if (__FPU_PRESENT == 1)
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134 | #define __FPU_USED 1
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135 | #else
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136 | #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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137 | #define __FPU_USED 0
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138 | #endif
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139 | #else
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140 | #define __FPU_USED 0
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141 | #endif
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142 |
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143 | #elif defined ( __GNUC__ )
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144 | #if defined (__VFP_FP__) && !defined(__SOFTFP__)
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145 | #if (__FPU_PRESENT == 1)
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146 | #define __FPU_USED 1
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147 | #else
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148 | #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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149 | #define __FPU_USED 0
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150 | #endif
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151 | #else
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152 | #define __FPU_USED 0
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153 | #endif
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154 |
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155 | #elif defined ( __TASKING__ )
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156 | #if defined __FPU_VFP__
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157 | #if (__FPU_PRESENT == 1)
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158 | #define __FPU_USED 1
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159 | #else
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160 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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161 | #define __FPU_USED 0
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162 | #endif
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163 | #else
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164 | #define __FPU_USED 0
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165 | #endif
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166 | #endif
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167 |
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168 | #include <stdint.h> /* standard types definitions */
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169 | #include <core_cmInstr.h> /* Core Instruction Access */
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170 | #include <core_cmFunc.h> /* Core Function Access */
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171 | #include <core_cm4_simd.h> /* Compiler specific SIMD Intrinsics */
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172 |
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173 | #endif /* __CORE_CM4_H_GENERIC */
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174 |
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175 | #ifndef __CMSIS_GENERIC
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176 |
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177 | #ifndef __CORE_CM4_H_DEPENDANT
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178 | #define __CORE_CM4_H_DEPENDANT
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179 |
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180 | /* check device defines and use defaults */
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181 | #if defined __CHECK_DEVICE_DEFINES
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182 | #ifndef __CM4_REV
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183 | #define __CM4_REV 0x0000
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184 | #warning "__CM4_REV not defined in device header file; using default!"
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185 | #endif
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186 |
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187 | #ifndef __FPU_PRESENT
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188 | #define __FPU_PRESENT 0
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189 | #warning "__FPU_PRESENT not defined in device header file; using default!"
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190 | #endif
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191 |
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192 | #ifndef __MPU_PRESENT
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193 | #define __MPU_PRESENT 0
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194 | #warning "__MPU_PRESENT not defined in device header file; using default!"
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195 | #endif
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196 |
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197 | #ifndef __NVIC_PRIO_BITS
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198 | #define __NVIC_PRIO_BITS 4
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199 | #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
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200 | #endif
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201 |
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202 | #ifndef __Vendor_SysTickConfig
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203 | #define __Vendor_SysTickConfig 0
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204 | #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
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205 | #endif
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206 | #endif
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207 |
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208 | /* IO definitions (access restrictions to peripheral registers) */
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209 | /**
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210 | \defgroup CMSIS_glob_defs CMSIS Global Defines
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211 |
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212 | <strong>IO Type Qualifiers</strong> are used
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213 | \li to specify the access to peripheral variables.
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214 | \li for automatic generation of peripheral register debug information.
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215 | */
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216 | #ifdef __cplusplus
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217 | #define __I volatile /*!< Defines 'read only' permissions */
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218 | #else
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219 | #define __I volatile const /*!< Defines 'read only' permissions */
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220 | #endif
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221 | #define __O volatile /*!< Defines 'write only' permissions */
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222 | #define __IO volatile /*!< Defines 'read / write' permissions */
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223 |
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224 | /*@} end of group Cortex_M4 */
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225 |
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226 |
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227 |
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228 | /*******************************************************************************
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229 | * Register Abstraction
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230 | Core Register contain:
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231 | - Core Register
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232 | - Core NVIC Register
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233 | - Core SCB Register
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234 | - Core SysTick Register
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235 | - Core Debug Register
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236 | - Core MPU Register
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237 | - Core FPU Register
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238 | ******************************************************************************/
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239 | /** \defgroup CMSIS_core_register Defines and Type Definitions
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240 | \brief Type definitions and defines for Cortex-M processor based devices.
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241 | */
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242 |
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243 | /** \ingroup CMSIS_core_register
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244 | \defgroup CMSIS_CORE Status and Control Registers
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245 | \brief Core Register type definitions.
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246 | @{
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247 | */
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248 |
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249 | /** \brief Union type to access the Application Program Status Register (APSR).
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250 | */
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251 | typedef union
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252 | {
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253 | struct
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254 | {
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255 | #if (__CORTEX_M != 0x04)
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256 | uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
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257 | #else
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258 | uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
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259 | uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
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260 | uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
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261 | #endif
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262 | uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
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263 | uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
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264 | uint32_t C:1; /*!< bit: 29 Carry condition code flag */
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265 | uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
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266 | uint32_t N:1; /*!< bit: 31 Negative condition code flag */
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267 | } b; /*!< Structure used for bit access */
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268 | uint32_t w; /*!< Type used for word access */
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269 | } APSR_Type;
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270 |
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271 |
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272 | /** \brief Union type to access the Interrupt Program Status Register (IPSR).
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273 | */
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274 | typedef union
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275 | {
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276 | struct
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277 | {
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278 | uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
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279 | uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
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280 | } b; /*!< Structure used for bit access */
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281 | uint32_t w; /*!< Type used for word access */
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282 | } IPSR_Type;
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283 |
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284 |
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285 | /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
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286 | */
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287 | typedef union
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288 | {
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289 | struct
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290 | {
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291 | uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
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292 | #if (__CORTEX_M != 0x04)
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293 | uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
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294 | #else
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295 | uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
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296 | uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
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297 | uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
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298 | #endif
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299 | uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
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300 | uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
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301 | uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
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302 | uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
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303 | uint32_t C:1; /*!< bit: 29 Carry condition code flag */
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304 | uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
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305 | uint32_t N:1; /*!< bit: 31 Negative condition code flag */
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306 | } b; /*!< Structure used for bit access */
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307 | uint32_t w; /*!< Type used for word access */
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308 | } xPSR_Type;
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309 |
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310 |
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311 | /** \brief Union type to access the Control Registers (CONTROL).
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312 | */
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313 | typedef union
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314 | {
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315 | struct
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316 | {
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317 | uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
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318 | uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
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319 | uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
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320 | uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
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321 | } b; /*!< Structure used for bit access */
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322 | uint32_t w; /*!< Type used for word access */
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323 | } CONTROL_Type;
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324 |
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325 | /*@} end of group CMSIS_CORE */
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326 |
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327 |
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328 | /** \ingroup CMSIS_core_register
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329 | \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
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330 | \brief Type definitions for the NVIC Registers
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331 | @{
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332 | */
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333 |
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334 | /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
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335 | */
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336 | typedef struct
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337 | {
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338 | __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
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339 | uint32_t RESERVED0[24];
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340 | __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
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341 | uint32_t RSERVED1[24];
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342 | __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
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343 | uint32_t RESERVED2[24];
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344 | __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
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345 | uint32_t RESERVED3[24];
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346 | __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
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347 | uint32_t RESERVED4[56];
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348 | __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
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349 | uint32_t RESERVED5[644];
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350 | __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
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351 | } NVIC_Type;
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352 |
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353 | /* Software Triggered Interrupt Register Definitions */
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354 | #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
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355 | #define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
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356 |
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357 | /*@} end of group CMSIS_NVIC */
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358 |
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359 |
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360 | /** \ingroup CMSIS_core_register
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361 | \defgroup CMSIS_SCB System Control Block (SCB)
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362 | \brief Type definitions for the System Control Block Registers
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363 | @{
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364 | */
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365 |
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366 | /** \brief Structure type to access the System Control Block (SCB).
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367 | */
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368 | typedef struct
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369 | {
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370 | __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
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371 | __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
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372 | __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
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373 | __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
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374 | __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
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375 | __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
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376 | __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
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377 | __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
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378 | __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
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379 | __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
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380 | __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
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381 | __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
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382 | __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
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383 | __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
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384 | __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
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385 | __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
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386 | __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
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387 | __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
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388 | __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
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389 | uint32_t RESERVED0[5];
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390 | __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
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391 | } SCB_Type;
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392 |
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393 | /* SCB CPUID Register Definitions */
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394 | #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
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395 | #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
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396 |
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397 | #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
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398 | #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
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399 |
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400 | #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
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401 | #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
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402 |
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403 | #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
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404 | #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
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405 |
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406 | #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
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407 | #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
|
---|
408 |
|
---|
409 | /* SCB Interrupt Control State Register Definitions */
|
---|
410 | #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
|
---|
411 | #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
|
---|
412 |
|
---|
413 | #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
|
---|
414 | #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
|
---|
415 |
|
---|
416 | #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
|
---|
417 | #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
|
---|
418 |
|
---|
419 | #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
|
---|
420 | #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
|
---|
421 |
|
---|
422 | #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
|
---|
423 | #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
|
---|
424 |
|
---|
425 | #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
|
---|
426 | #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
|
---|
427 |
|
---|
428 | #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
|
---|
429 | #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
|
---|
430 |
|
---|
431 | #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
|
---|
432 | #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
|
---|
433 |
|
---|
434 | #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
|
---|
435 | #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
|
---|
436 |
|
---|
437 | #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
|
---|
438 | #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
|
---|
439 |
|
---|
440 | /* SCB Vector Table Offset Register Definitions */
|
---|
441 | #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
|
---|
442 | #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
|
---|
443 |
|
---|
444 | /* SCB Application Interrupt and Reset Control Register Definitions */
|
---|
445 | #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
|
---|
446 | #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
|
---|
447 |
|
---|
448 | #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
|
---|
449 | #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
|
---|
450 |
|
---|
451 | #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
|
---|
452 | #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
|
---|
453 |
|
---|
454 | #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
|
---|
455 | #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
|
---|
456 |
|
---|
457 | #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
|
---|
458 | #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
|
---|
459 |
|
---|
460 | #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
|
---|
461 | #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
|
---|
462 |
|
---|
463 | #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
|
---|
464 | #define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
|
---|
465 |
|
---|
466 | /* SCB System Control Register Definitions */
|
---|
467 | #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
|
---|
468 | #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
|
---|
469 |
|
---|
470 | #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
|
---|
471 | #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
|
---|
472 |
|
---|
473 | #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
|
---|
474 | #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
|
---|
475 |
|
---|
476 | /* SCB Configuration Control Register Definitions */
|
---|
477 | #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
|
---|
478 | #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
|
---|
479 |
|
---|
480 | #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
|
---|
481 | #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
|
---|
482 |
|
---|
483 | #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
|
---|
484 | #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
|
---|
485 |
|
---|
486 | #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
|
---|
487 | #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
|
---|
488 |
|
---|
489 | #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
|
---|
490 | #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
|
---|
491 |
|
---|
492 | #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
|
---|
493 | #define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
|
---|
494 |
|
---|
495 | /* SCB System Handler Control and State Register Definitions */
|
---|
496 | #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
|
---|
497 | #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
|
---|
498 |
|
---|
499 | #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
|
---|
500 | #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
|
---|
501 |
|
---|
502 | #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
|
---|
503 | #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
|
---|
504 |
|
---|
505 | #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
|
---|
506 | #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
|
---|
507 |
|
---|
508 | #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
|
---|
509 | #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
|
---|
510 |
|
---|
511 | #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
|
---|
512 | #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
|
---|
513 |
|
---|
514 | #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
|
---|
515 | #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
|
---|
516 |
|
---|
517 | #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
|
---|
518 | #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
|
---|
519 |
|
---|
520 | #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
|
---|
521 | #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
|
---|
522 |
|
---|
523 | #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
|
---|
524 | #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
|
---|
525 |
|
---|
526 | #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
|
---|
527 | #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
|
---|
528 |
|
---|
529 | #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
|
---|
530 | #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
|
---|
531 |
|
---|
532 | #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
|
---|
533 | #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
|
---|
534 |
|
---|
535 | #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
|
---|
536 | #define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
|
---|
537 |
|
---|
538 | /* SCB Configurable Fault Status Registers Definitions */
|
---|
539 | #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
|
---|
540 | #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
|
---|
541 |
|
---|
542 | #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
|
---|
543 | #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
|
---|
544 |
|
---|
545 | #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
|
---|
546 | #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
|
---|
547 |
|
---|
548 | /* SCB Hard Fault Status Registers Definitions */
|
---|
549 | #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
|
---|
550 | #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
|
---|
551 |
|
---|
552 | #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
|
---|
553 | #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
|
---|
554 |
|
---|
555 | #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
|
---|
556 | #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
|
---|
557 |
|
---|
558 | /* SCB Debug Fault Status Register Definitions */
|
---|
559 | #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
|
---|
560 | #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
|
---|
561 |
|
---|
562 | #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
|
---|
563 | #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
|
---|
564 |
|
---|
565 | #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
|
---|
566 | #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
|
---|
567 |
|
---|
568 | #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
|
---|
569 | #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
|
---|
570 |
|
---|
571 | #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
|
---|
572 | #define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
|
---|
573 |
|
---|
574 | /*@} end of group CMSIS_SCB */
|
---|
575 |
|
---|
576 |
|
---|
577 | /** \ingroup CMSIS_core_register
|
---|
578 | \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
|
---|
579 | \brief Type definitions for the System Control and ID Register not in the SCB
|
---|
580 | @{
|
---|
581 | */
|
---|
582 |
|
---|
583 | /** \brief Structure type to access the System Control and ID Register not in the SCB.
|
---|
584 | */
|
---|
585 | typedef struct
|
---|
586 | {
|
---|
587 | uint32_t RESERVED0[1];
|
---|
588 | __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
|
---|
589 | __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
|
---|
590 | } SCnSCB_Type;
|
---|
591 |
|
---|
592 | /* Interrupt Controller Type Register Definitions */
|
---|
593 | #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
|
---|
594 | #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
|
---|
595 |
|
---|
596 | /* Auxiliary Control Register Definitions */
|
---|
597 | #define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */
|
---|
598 | #define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
|
---|
599 |
|
---|
600 | #define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */
|
---|
601 | #define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
|
---|
602 |
|
---|
603 | #define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
|
---|
604 | #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
|
---|
605 |
|
---|
606 | #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
|
---|
607 | #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
|
---|
608 |
|
---|
609 | #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
|
---|
610 | #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
|
---|
611 |
|
---|
612 | /*@} end of group CMSIS_SCnotSCB */
|
---|
613 |
|
---|
614 |
|
---|
615 | /** \ingroup CMSIS_core_register
|
---|
616 | \defgroup CMSIS_SysTick System Tick Timer (SysTick)
|
---|
617 | \brief Type definitions for the System Timer Registers.
|
---|
618 | @{
|
---|
619 | */
|
---|
620 |
|
---|
621 | /** \brief Structure type to access the System Timer (SysTick).
|
---|
622 | */
|
---|
623 | typedef struct
|
---|
624 | {
|
---|
625 | __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
|
---|
626 | __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
|
---|
627 | __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
|
---|
628 | __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
|
---|
629 | } SysTick_Type;
|
---|
630 |
|
---|
631 | /* SysTick Control / Status Register Definitions */
|
---|
632 | #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
|
---|
633 | #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
|
---|
634 |
|
---|
635 | #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
|
---|
636 | #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
|
---|
637 |
|
---|
638 | #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
|
---|
639 | #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
|
---|
640 |
|
---|
641 | #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
|
---|
642 | #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
|
---|
643 |
|
---|
644 | /* SysTick Reload Register Definitions */
|
---|
645 | #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
|
---|
646 | #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
|
---|
647 |
|
---|
648 | /* SysTick Current Register Definitions */
|
---|
649 | #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
|
---|
650 | #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
|
---|
651 |
|
---|
652 | /* SysTick Calibration Register Definitions */
|
---|
653 | #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
|
---|
654 | #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
|
---|
655 |
|
---|
656 | #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
|
---|
657 | #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
|
---|
658 |
|
---|
659 | #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
|
---|
660 | #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
|
---|
661 |
|
---|
662 | /*@} end of group CMSIS_SysTick */
|
---|
663 |
|
---|
664 |
|
---|
665 | /** \ingroup CMSIS_core_register
|
---|
666 | \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
|
---|
667 | \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
|
---|
668 | @{
|
---|
669 | */
|
---|
670 |
|
---|
671 | /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
|
---|
672 | */
|
---|
673 | typedef struct
|
---|
674 | {
|
---|
675 | __O union
|
---|
676 | {
|
---|
677 | __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
|
---|
678 | __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
|
---|
679 | __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
|
---|
680 | } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
|
---|
681 | uint32_t RESERVED0[864];
|
---|
682 | __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
|
---|
683 | uint32_t RESERVED1[15];
|
---|
684 | __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
|
---|
685 | uint32_t RESERVED2[15];
|
---|
686 | __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
|
---|
687 | uint32_t RESERVED3[29];
|
---|
688 | __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
|
---|
689 | __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
|
---|
690 | __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
|
---|
691 | uint32_t RESERVED4[43];
|
---|
692 | __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
|
---|
693 | __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
|
---|
694 | uint32_t RESERVED5[6];
|
---|
695 | __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
|
---|
696 | __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
|
---|
697 | __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
|
---|
698 | __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
|
---|
699 | __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
|
---|
700 | __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
|
---|
701 | __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
|
---|
702 | __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
|
---|
703 | __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
|
---|
704 | __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
|
---|
705 | __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
|
---|
706 | __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
|
---|
707 | } ITM_Type;
|
---|
708 |
|
---|
709 | /* ITM Trace Privilege Register Definitions */
|
---|
710 | #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
|
---|
711 | #define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
|
---|
712 |
|
---|
713 | /* ITM Trace Control Register Definitions */
|
---|
714 | #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
|
---|
715 | #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
|
---|
716 |
|
---|
717 | #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
|
---|
718 | #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
|
---|
719 |
|
---|
720 | #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
|
---|
721 | #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
|
---|
722 |
|
---|
723 | #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
|
---|
724 | #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
|
---|
725 |
|
---|
726 | #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
|
---|
727 | #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
|
---|
728 |
|
---|
729 | #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
|
---|
730 | #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
|
---|
731 |
|
---|
732 | #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
|
---|
733 | #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
|
---|
734 |
|
---|
735 | #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
|
---|
736 | #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
|
---|
737 |
|
---|
738 | #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
|
---|
739 | #define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
|
---|
740 |
|
---|
741 | /* ITM Integration Write Register Definitions */
|
---|
742 | #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
|
---|
743 | #define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
|
---|
744 |
|
---|
745 | /* ITM Integration Read Register Definitions */
|
---|
746 | #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
|
---|
747 | #define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
|
---|
748 |
|
---|
749 | /* ITM Integration Mode Control Register Definitions */
|
---|
750 | #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
|
---|
751 | #define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
|
---|
752 |
|
---|
753 | /* ITM Lock Status Register Definitions */
|
---|
754 | #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
|
---|
755 | #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
|
---|
756 |
|
---|
757 | #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
|
---|
758 | #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
|
---|
759 |
|
---|
760 | #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
|
---|
761 | #define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
|
---|
762 |
|
---|
763 | /*@}*/ /* end of group CMSIS_ITM */
|
---|
764 |
|
---|
765 |
|
---|
766 | /** \ingroup CMSIS_core_register
|
---|
767 | \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
|
---|
768 | \brief Type definitions for the Data Watchpoint and Trace (DWT)
|
---|
769 | @{
|
---|
770 | */
|
---|
771 |
|
---|
772 | /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
|
---|
773 | */
|
---|
774 | typedef struct
|
---|
775 | {
|
---|
776 | __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
|
---|
777 | __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
|
---|
778 | __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
|
---|
779 | __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
|
---|
780 | __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
|
---|
781 | __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
|
---|
782 | __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
|
---|
783 | __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
|
---|
784 | __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
|
---|
785 | __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
|
---|
786 | __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
|
---|
787 | uint32_t RESERVED0[1];
|
---|
788 | __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
|
---|
789 | __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
|
---|
790 | __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
|
---|
791 | uint32_t RESERVED1[1];
|
---|
792 | __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
|
---|
793 | __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
|
---|
794 | __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
|
---|
795 | uint32_t RESERVED2[1];
|
---|
796 | __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
|
---|
797 | __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
|
---|
798 | __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
|
---|
799 | } DWT_Type;
|
---|
800 |
|
---|
801 | /* DWT Control Register Definitions */
|
---|
802 | #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
|
---|
803 | #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
|
---|
804 |
|
---|
805 | #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
|
---|
806 | #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
|
---|
807 |
|
---|
808 | #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
|
---|
809 | #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
|
---|
810 |
|
---|
811 | #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
|
---|
812 | #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
|
---|
813 |
|
---|
814 | #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
|
---|
815 | #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
|
---|
816 |
|
---|
817 | #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
|
---|
818 | #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
|
---|
819 |
|
---|
820 | #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
|
---|
821 | #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
|
---|
822 |
|
---|
823 | #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
|
---|
824 | #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
|
---|
825 |
|
---|
826 | #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
|
---|
827 | #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
|
---|
828 |
|
---|
829 | #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
|
---|
830 | #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
|
---|
831 |
|
---|
832 | #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
|
---|
833 | #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
|
---|
834 |
|
---|
835 | #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
|
---|
836 | #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
|
---|
837 |
|
---|
838 | #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
|
---|
839 | #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
|
---|
840 |
|
---|
841 | #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
|
---|
842 | #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
|
---|
843 |
|
---|
844 | #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
|
---|
845 | #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
|
---|
846 |
|
---|
847 | #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
|
---|
848 | #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
|
---|
849 |
|
---|
850 | #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
|
---|
851 | #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
|
---|
852 |
|
---|
853 | #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
|
---|
854 | #define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */
|
---|
855 |
|
---|
856 | /* DWT CPI Count Register Definitions */
|
---|
857 | #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
|
---|
858 | #define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */
|
---|
859 |
|
---|
860 | /* DWT Exception Overhead Count Register Definitions */
|
---|
861 | #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
|
---|
862 | #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */
|
---|
863 |
|
---|
864 | /* DWT Sleep Count Register Definitions */
|
---|
865 | #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
|
---|
866 | #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
|
---|
867 |
|
---|
868 | /* DWT LSU Count Register Definitions */
|
---|
869 | #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
|
---|
870 | #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */
|
---|
871 |
|
---|
872 | /* DWT Folded-instruction Count Register Definitions */
|
---|
873 | #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
|
---|
874 | #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */
|
---|
875 |
|
---|
876 | /* DWT Comparator Mask Register Definitions */
|
---|
877 | #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
|
---|
878 | #define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */
|
---|
879 |
|
---|
880 | /* DWT Comparator Function Register Definitions */
|
---|
881 | #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
|
---|
882 | #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
|
---|
883 |
|
---|
884 | #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
|
---|
885 | #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
|
---|
886 |
|
---|
887 | #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
|
---|
888 | #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
|
---|
889 |
|
---|
890 | #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
|
---|
891 | #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
|
---|
892 |
|
---|
893 | #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
|
---|
894 | #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
|
---|
895 |
|
---|
896 | #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
|
---|
897 | #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
|
---|
898 |
|
---|
899 | #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
|
---|
900 | #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
|
---|
901 |
|
---|
902 | #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
|
---|
903 | #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
|
---|
904 |
|
---|
905 | #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
|
---|
906 | #define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */
|
---|
907 |
|
---|
908 | /*@}*/ /* end of group CMSIS_DWT */
|
---|
909 |
|
---|
910 |
|
---|
911 | /** \ingroup CMSIS_core_register
|
---|
912 | \defgroup CMSIS_TPI Trace Port Interface (TPI)
|
---|
913 | \brief Type definitions for the Trace Port Interface (TPI)
|
---|
914 | @{
|
---|
915 | */
|
---|
916 |
|
---|
917 | /** \brief Structure type to access the Trace Port Interface Register (TPI).
|
---|
918 | */
|
---|
919 | typedef struct
|
---|
920 | {
|
---|
921 | __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
|
---|
922 | __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
|
---|
923 | uint32_t RESERVED0[2];
|
---|
924 | __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
|
---|
925 | uint32_t RESERVED1[55];
|
---|
926 | __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
|
---|
927 | uint32_t RESERVED2[131];
|
---|
928 | __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
|
---|
929 | __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
|
---|
930 | __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
|
---|
931 | uint32_t RESERVED3[759];
|
---|
932 | __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
|
---|
933 | __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
|
---|
934 | __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
|
---|
935 | uint32_t RESERVED4[1];
|
---|
936 | __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
|
---|
937 | __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
|
---|
938 | __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
|
---|
939 | uint32_t RESERVED5[39];
|
---|
940 | __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
|
---|
941 | __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
|
---|
942 | uint32_t RESERVED7[8];
|
---|
943 | __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
|
---|
944 | __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
|
---|
945 | } TPI_Type;
|
---|
946 |
|
---|
947 | /* TPI Asynchronous Clock Prescaler Register Definitions */
|
---|
948 | #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
|
---|
949 | #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */
|
---|
950 |
|
---|
951 | /* TPI Selected Pin Protocol Register Definitions */
|
---|
952 | #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
|
---|
953 | #define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */
|
---|
954 |
|
---|
955 | /* TPI Formatter and Flush Status Register Definitions */
|
---|
956 | #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
|
---|
957 | #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
|
---|
958 |
|
---|
959 | #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
|
---|
960 | #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
|
---|
961 |
|
---|
962 | #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
|
---|
963 | #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
|
---|
964 |
|
---|
965 | #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
|
---|
966 | #define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */
|
---|
967 |
|
---|
968 | /* TPI Formatter and Flush Control Register Definitions */
|
---|
969 | #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
|
---|
970 | #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
|
---|
971 |
|
---|
972 | #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
|
---|
973 | #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
|
---|
974 |
|
---|
975 | /* TPI TRIGGER Register Definitions */
|
---|
976 | #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
|
---|
977 | #define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */
|
---|
978 |
|
---|
979 | /* TPI Integration ETM Data Register Definitions (FIFO0) */
|
---|
980 | #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
|
---|
981 | #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
|
---|
982 |
|
---|
983 | #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
|
---|
984 | #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
|
---|
985 |
|
---|
986 | #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
|
---|
987 | #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
|
---|
988 |
|
---|
989 | #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
|
---|
990 | #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
|
---|
991 |
|
---|
992 | #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
|
---|
993 | #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
|
---|
994 |
|
---|
995 | #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
|
---|
996 | #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
|
---|
997 |
|
---|
998 | #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
|
---|
999 | #define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */
|
---|
1000 |
|
---|
1001 | /* TPI ITATBCTR2 Register Definitions */
|
---|
1002 | #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
|
---|
1003 | #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */
|
---|
1004 |
|
---|
1005 | /* TPI Integration ITM Data Register Definitions (FIFO1) */
|
---|
1006 | #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
|
---|
1007 | #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
|
---|
1008 |
|
---|
1009 | #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
|
---|
1010 | #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
|
---|
1011 |
|
---|
1012 | #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
|
---|
1013 | #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
|
---|
1014 |
|
---|
1015 | #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
|
---|
1016 | #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
|
---|
1017 |
|
---|
1018 | #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
|
---|
1019 | #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
|
---|
1020 |
|
---|
1021 | #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
|
---|
1022 | #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
|
---|
1023 |
|
---|
1024 | #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
|
---|
1025 | #define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */
|
---|
1026 |
|
---|
1027 | /* TPI ITATBCTR0 Register Definitions */
|
---|
1028 | #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
|
---|
1029 | #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */
|
---|
1030 |
|
---|
1031 | /* TPI Integration Mode Control Register Definitions */
|
---|
1032 | #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
|
---|
1033 | #define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */
|
---|
1034 |
|
---|
1035 | /* TPI DEVID Register Definitions */
|
---|
1036 | #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
|
---|
1037 | #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
|
---|
1038 |
|
---|
1039 | #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
|
---|
1040 | #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
|
---|
1041 |
|
---|
1042 | #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
|
---|
1043 | #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
|
---|
1044 |
|
---|
1045 | #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
|
---|
1046 | #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
|
---|
1047 |
|
---|
1048 | #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
|
---|
1049 | #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
|
---|
1050 |
|
---|
1051 | #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
|
---|
1052 | #define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */
|
---|
1053 |
|
---|
1054 | /* TPI DEVTYPE Register Definitions */
|
---|
1055 | #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
|
---|
1056 | #define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */
|
---|
1057 |
|
---|
1058 | #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
|
---|
1059 | #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
|
---|
1060 |
|
---|
1061 | /*@}*/ /* end of group CMSIS_TPI */
|
---|
1062 |
|
---|
1063 |
|
---|
1064 | #if (__MPU_PRESENT == 1)
|
---|
1065 | /** \ingroup CMSIS_core_register
|
---|
1066 | \defgroup CMSIS_MPU Memory Protection Unit (MPU)
|
---|
1067 | \brief Type definitions for the Memory Protection Unit (MPU)
|
---|
1068 | @{
|
---|
1069 | */
|
---|
1070 |
|
---|
1071 | /** \brief Structure type to access the Memory Protection Unit (MPU).
|
---|
1072 | */
|
---|
1073 | typedef struct
|
---|
1074 | {
|
---|
1075 | __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
|
---|
1076 | __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
|
---|
1077 | __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
|
---|
1078 | __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
|
---|
1079 | __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
|
---|
1080 | __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
|
---|
1081 | __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
|
---|
1082 | __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
|
---|
1083 | __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
|
---|
1084 | __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
|
---|
1085 | __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
|
---|
1086 | } MPU_Type;
|
---|
1087 |
|
---|
1088 | /* MPU Type Register */
|
---|
1089 | #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
|
---|
1090 | #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
|
---|
1091 |
|
---|
1092 | #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
|
---|
1093 | #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
|
---|
1094 |
|
---|
1095 | #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
|
---|
1096 | #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
|
---|
1097 |
|
---|
1098 | /* MPU Control Register */
|
---|
1099 | #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
|
---|
1100 | #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
|
---|
1101 |
|
---|
1102 | #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
|
---|
1103 | #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
|
---|
1104 |
|
---|
1105 | #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
|
---|
1106 | #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
|
---|
1107 |
|
---|
1108 | /* MPU Region Number Register */
|
---|
1109 | #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
|
---|
1110 | #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
|
---|
1111 |
|
---|
1112 | /* MPU Region Base Address Register */
|
---|
1113 | #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
|
---|
1114 | #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
|
---|
1115 |
|
---|
1116 | #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
|
---|
1117 | #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
|
---|
1118 |
|
---|
1119 | #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
|
---|
1120 | #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
|
---|
1121 |
|
---|
1122 | /* MPU Region Attribute and Size Register */
|
---|
1123 | #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
|
---|
1124 | #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
|
---|
1125 |
|
---|
1126 | #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
|
---|
1127 | #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
|
---|
1128 |
|
---|
1129 | #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
|
---|
1130 | #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
|
---|
1131 |
|
---|
1132 | #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
|
---|
1133 | #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
|
---|
1134 |
|
---|
1135 | #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
|
---|
1136 | #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
|
---|
1137 |
|
---|
1138 | #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
|
---|
1139 | #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
|
---|
1140 |
|
---|
1141 | #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
|
---|
1142 | #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
|
---|
1143 |
|
---|
1144 | #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
|
---|
1145 | #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
|
---|
1146 |
|
---|
1147 | #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
|
---|
1148 | #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
|
---|
1149 |
|
---|
1150 | #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
|
---|
1151 | #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
|
---|
1152 |
|
---|
1153 | /*@} end of group CMSIS_MPU */
|
---|
1154 | #endif
|
---|
1155 |
|
---|
1156 |
|
---|
1157 | #if (__FPU_PRESENT == 1)
|
---|
1158 | /** \ingroup CMSIS_core_register
|
---|
1159 | \defgroup CMSIS_FPU Floating Point Unit (FPU)
|
---|
1160 | \brief Type definitions for the Floating Point Unit (FPU)
|
---|
1161 | @{
|
---|
1162 | */
|
---|
1163 |
|
---|
1164 | /** \brief Structure type to access the Floating Point Unit (FPU).
|
---|
1165 | */
|
---|
1166 | typedef struct
|
---|
1167 | {
|
---|
1168 | uint32_t RESERVED0[1];
|
---|
1169 | __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
|
---|
1170 | __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
|
---|
1171 | __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
|
---|
1172 | __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
|
---|
1173 | __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
|
---|
1174 | } FPU_Type;
|
---|
1175 |
|
---|
1176 | /* Floating-Point Context Control Register */
|
---|
1177 | #define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */
|
---|
1178 | #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
|
---|
1179 |
|
---|
1180 | #define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */
|
---|
1181 | #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
|
---|
1182 |
|
---|
1183 | #define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */
|
---|
1184 | #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
|
---|
1185 |
|
---|
1186 | #define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */
|
---|
1187 | #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
|
---|
1188 |
|
---|
1189 | #define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */
|
---|
1190 | #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
|
---|
1191 |
|
---|
1192 | #define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */
|
---|
1193 | #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
|
---|
1194 |
|
---|
1195 | #define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */
|
---|
1196 | #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
|
---|
1197 |
|
---|
1198 | #define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */
|
---|
1199 | #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
|
---|
1200 |
|
---|
1201 | #define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */
|
---|
1202 | #define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */
|
---|
1203 |
|
---|
1204 | /* Floating-Point Context Address Register */
|
---|
1205 | #define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */
|
---|
1206 | #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
|
---|
1207 |
|
---|
1208 | /* Floating-Point Default Status Control Register */
|
---|
1209 | #define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */
|
---|
1210 | #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
|
---|
1211 |
|
---|
1212 | #define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */
|
---|
1213 | #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
|
---|
1214 |
|
---|
1215 | #define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */
|
---|
1216 | #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
|
---|
1217 |
|
---|
1218 | #define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */
|
---|
1219 | #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
|
---|
1220 |
|
---|
1221 | /* Media and FP Feature Register 0 */
|
---|
1222 | #define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */
|
---|
1223 | #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
|
---|
1224 |
|
---|
1225 | #define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */
|
---|
1226 | #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
|
---|
1227 |
|
---|
1228 | #define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */
|
---|
1229 | #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
|
---|
1230 |
|
---|
1231 | #define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */
|
---|
1232 | #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
|
---|
1233 |
|
---|
1234 | #define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */
|
---|
1235 | #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
|
---|
1236 |
|
---|
1237 | #define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */
|
---|
1238 | #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
|
---|
1239 |
|
---|
1240 | #define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */
|
---|
1241 | #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
|
---|
1242 |
|
---|
1243 | #define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */
|
---|
1244 | #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */
|
---|
1245 |
|
---|
1246 | /* Media and FP Feature Register 1 */
|
---|
1247 | #define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */
|
---|
1248 | #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
|
---|
1249 |
|
---|
1250 | #define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */
|
---|
1251 | #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
|
---|
1252 |
|
---|
1253 | #define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */
|
---|
1254 | #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
|
---|
1255 |
|
---|
1256 | #define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */
|
---|
1257 | #define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */
|
---|
1258 |
|
---|
1259 | /*@} end of group CMSIS_FPU */
|
---|
1260 | #endif
|
---|
1261 |
|
---|
1262 |
|
---|
1263 | /** \ingroup CMSIS_core_register
|
---|
1264 | \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
|
---|
1265 | \brief Type definitions for the Core Debug Registers
|
---|
1266 | @{
|
---|
1267 | */
|
---|
1268 |
|
---|
1269 | /** \brief Structure type to access the Core Debug Register (CoreDebug).
|
---|
1270 | */
|
---|
1271 | typedef struct
|
---|
1272 | {
|
---|
1273 | __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
|
---|
1274 | __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
|
---|
1275 | __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
|
---|
1276 | __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
|
---|
1277 | } CoreDebug_Type;
|
---|
1278 |
|
---|
1279 | /* Debug Halting Control and Status Register */
|
---|
1280 | #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
|
---|
1281 | #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
|
---|
1282 |
|
---|
1283 | #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
|
---|
1284 | #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
|
---|
1285 |
|
---|
1286 | #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
|
---|
1287 | #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
|
---|
1288 |
|
---|
1289 | #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
|
---|
1290 | #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
|
---|
1291 |
|
---|
1292 | #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
|
---|
1293 | #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
|
---|
1294 |
|
---|
1295 | #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
|
---|
1296 | #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
|
---|
1297 |
|
---|
1298 | #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
|
---|
1299 | #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
|
---|
1300 |
|
---|
1301 | #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
|
---|
1302 | #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
|
---|
1303 |
|
---|
1304 | #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
|
---|
1305 | #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
|
---|
1306 |
|
---|
1307 | #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
|
---|
1308 | #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
|
---|
1309 |
|
---|
1310 | #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
|
---|
1311 | #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
|
---|
1312 |
|
---|
1313 | #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
|
---|
1314 | #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
|
---|
1315 |
|
---|
1316 | /* Debug Core Register Selector Register */
|
---|
1317 | #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
|
---|
1318 | #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
|
---|
1319 |
|
---|
1320 | #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
|
---|
1321 | #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
|
---|
1322 |
|
---|
1323 | /* Debug Exception and Monitor Control Register */
|
---|
1324 | #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
|
---|
1325 | #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
|
---|
1326 |
|
---|
1327 | #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
|
---|
1328 | #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
|
---|
1329 |
|
---|
1330 | #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
|
---|
1331 | #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
|
---|
1332 |
|
---|
1333 | #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
|
---|
1334 | #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
|
---|
1335 |
|
---|
1336 | #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
|
---|
1337 | #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
|
---|
1338 |
|
---|
1339 | #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
|
---|
1340 | #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
|
---|
1341 |
|
---|
1342 | #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
|
---|
1343 | #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
|
---|
1344 |
|
---|
1345 | #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
|
---|
1346 | #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
|
---|
1347 |
|
---|
1348 | #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
|
---|
1349 | #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
|
---|
1350 |
|
---|
1351 | #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
|
---|
1352 | #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
|
---|
1353 |
|
---|
1354 | #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
|
---|
1355 | #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
|
---|
1356 |
|
---|
1357 | #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
|
---|
1358 | #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
|
---|
1359 |
|
---|
1360 | #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
|
---|
1361 | #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
|
---|
1362 |
|
---|
1363 | /*@} end of group CMSIS_CoreDebug */
|
---|
1364 |
|
---|
1365 |
|
---|
1366 | /** \ingroup CMSIS_core_register
|
---|
1367 | \defgroup CMSIS_core_base Core Definitions
|
---|
1368 | \brief Definitions for base addresses, unions, and structures.
|
---|
1369 | @{
|
---|
1370 | */
|
---|
1371 |
|
---|
1372 | /* Memory mapping of Cortex-M4 Hardware */
|
---|
1373 | #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
|
---|
1374 | #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
|
---|
1375 | #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
|
---|
1376 | #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
|
---|
1377 | #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
|
---|
1378 | #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
|
---|
1379 | #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
|
---|
1380 | #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
|
---|
1381 |
|
---|
1382 | #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
|
---|
1383 | #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
|
---|
1384 | #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
|
---|
1385 | #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
|
---|
1386 | #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
|
---|
1387 | #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
|
---|
1388 | #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
|
---|
1389 | #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
|
---|
1390 |
|
---|
1391 | #if (__MPU_PRESENT == 1)
|
---|
1392 | #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
|
---|
1393 | #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
|
---|
1394 | #endif
|
---|
1395 |
|
---|
1396 | #if (__FPU_PRESENT == 1)
|
---|
1397 | #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
|
---|
1398 | #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
|
---|
1399 | #endif
|
---|
1400 |
|
---|
1401 | /*@} */
|
---|
1402 |
|
---|
1403 |
|
---|
1404 |
|
---|
1405 | /*******************************************************************************
|
---|
1406 | * Hardware Abstraction Layer
|
---|
1407 | Core Function Interface contains:
|
---|
1408 | - Core NVIC Functions
|
---|
1409 | - Core SysTick Functions
|
---|
1410 | - Core Debug Functions
|
---|
1411 | - Core Register Access Functions
|
---|
1412 | ******************************************************************************/
|
---|
1413 | /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
|
---|
1414 | */
|
---|
1415 |
|
---|
1416 |
|
---|
1417 |
|
---|
1418 | /* ########################## NVIC functions #################################### */
|
---|
1419 | /** \ingroup CMSIS_Core_FunctionInterface
|
---|
1420 | \defgroup CMSIS_Core_NVICFunctions NVIC Functions
|
---|
1421 | \brief Functions that manage interrupts and exceptions via the NVIC.
|
---|
1422 | @{
|
---|
1423 | */
|
---|
1424 |
|
---|
1425 | /** \brief Set Priority Grouping
|
---|
1426 |
|
---|
1427 | The function sets the priority grouping field using the required unlock sequence.
|
---|
1428 | The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
|
---|
1429 | Only values from 0..7 are used.
|
---|
1430 | In case of a conflict between priority grouping and available
|
---|
1431 | priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
|
---|
1432 |
|
---|
1433 | \param [in] PriorityGroup Priority grouping field.
|
---|
1434 | */
|
---|
1435 | __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
---|
1436 | {
|
---|
1437 | uint32_t reg_value;
|
---|
1438 | uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
|
---|
1439 |
|
---|
1440 | reg_value = SCB->AIRCR; /* read old register configuration */
|
---|
1441 | reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
|
---|
1442 | reg_value = (reg_value |
|
---|
1443 | ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
|
---|
1444 | (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
|
---|
1445 | SCB->AIRCR = reg_value;
|
---|
1446 | }
|
---|
1447 |
|
---|
1448 |
|
---|
1449 | /** \brief Get Priority Grouping
|
---|
1450 |
|
---|
1451 | The function reads the priority grouping field from the NVIC Interrupt Controller.
|
---|
1452 |
|
---|
1453 | \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
|
---|
1454 | */
|
---|
1455 | __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
|
---|
1456 | {
|
---|
1457 | return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
|
---|
1458 | }
|
---|
1459 |
|
---|
1460 |
|
---|
1461 | /** \brief Enable External Interrupt
|
---|
1462 |
|
---|
1463 | The function enables a device-specific interrupt in the NVIC interrupt controller.
|
---|
1464 |
|
---|
1465 | \param [in] IRQn External interrupt number. Value cannot be negative.
|
---|
1466 | */
|
---|
1467 | __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
|
---|
1468 | {
|
---|
1469 | /* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */
|
---|
1470 | NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */
|
---|
1471 | }
|
---|
1472 |
|
---|
1473 |
|
---|
1474 | /** \brief Disable External Interrupt
|
---|
1475 |
|
---|
1476 | The function disables a device-specific interrupt in the NVIC interrupt controller.
|
---|
1477 |
|
---|
1478 | \param [in] IRQn External interrupt number. Value cannot be negative.
|
---|
1479 | */
|
---|
1480 | __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
|
---|
1481 | {
|
---|
1482 | NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
|
---|
1483 | }
|
---|
1484 |
|
---|
1485 |
|
---|
1486 | /** \brief Get Pending Interrupt
|
---|
1487 |
|
---|
1488 | The function reads the pending register in the NVIC and returns the pending bit
|
---|
1489 | for the specified interrupt.
|
---|
1490 |
|
---|
1491 | \param [in] IRQn Interrupt number.
|
---|
1492 |
|
---|
1493 | \return 0 Interrupt status is not pending.
|
---|
1494 | \return 1 Interrupt status is pending.
|
---|
1495 | */
|
---|
1496 | __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
---|
1497 | {
|
---|
1498 | return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
|
---|
1499 | }
|
---|
1500 |
|
---|
1501 |
|
---|
1502 | /** \brief Set Pending Interrupt
|
---|
1503 |
|
---|
1504 | The function sets the pending bit of an external interrupt.
|
---|
1505 |
|
---|
1506 | \param [in] IRQn Interrupt number. Value cannot be negative.
|
---|
1507 | */
|
---|
1508 | __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
---|
1509 | {
|
---|
1510 | NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
|
---|
1511 | }
|
---|
1512 |
|
---|
1513 |
|
---|
1514 | /** \brief Clear Pending Interrupt
|
---|
1515 |
|
---|
1516 | The function clears the pending bit of an external interrupt.
|
---|
1517 |
|
---|
1518 | \param [in] IRQn External interrupt number. Value cannot be negative.
|
---|
1519 | */
|
---|
1520 | __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
---|
1521 | {
|
---|
1522 | NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
|
---|
1523 | }
|
---|
1524 |
|
---|
1525 |
|
---|
1526 | /** \brief Get Active Interrupt
|
---|
1527 |
|
---|
1528 | The function reads the active register in NVIC and returns the active bit.
|
---|
1529 |
|
---|
1530 | \param [in] IRQn Interrupt number.
|
---|
1531 |
|
---|
1532 | \return 0 Interrupt status is not active.
|
---|
1533 | \return 1 Interrupt status is active.
|
---|
1534 | */
|
---|
1535 | __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
|
---|
1536 | {
|
---|
1537 | return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
|
---|
1538 | }
|
---|
1539 |
|
---|
1540 |
|
---|
1541 | /** \brief Set Interrupt Priority
|
---|
1542 |
|
---|
1543 | The function sets the priority of an interrupt.
|
---|
1544 |
|
---|
1545 | \note The priority cannot be set for every core interrupt.
|
---|
1546 |
|
---|
1547 | \param [in] IRQn Interrupt number.
|
---|
1548 | \param [in] priority Priority to set.
|
---|
1549 | */
|
---|
1550 | __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
---|
1551 | {
|
---|
1552 | if(IRQn < 0) {
|
---|
1553 | SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
|
---|
1554 | else {
|
---|
1555 | NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
|
---|
1556 | }
|
---|
1557 |
|
---|
1558 |
|
---|
1559 | /** \brief Get Interrupt Priority
|
---|
1560 |
|
---|
1561 | The function reads the priority of an interrupt. The interrupt
|
---|
1562 | number can be positive to specify an external (device specific)
|
---|
1563 | interrupt, or negative to specify an internal (core) interrupt.
|
---|
1564 |
|
---|
1565 |
|
---|
1566 | \param [in] IRQn Interrupt number.
|
---|
1567 | \return Interrupt Priority. Value is aligned automatically to the implemented
|
---|
1568 | priority bits of the microcontroller.
|
---|
1569 | */
|
---|
1570 | __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
|
---|
1571 | {
|
---|
1572 |
|
---|
1573 | if(IRQn < 0) {
|
---|
1574 | return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
|
---|
1575 | else {
|
---|
1576 | return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
|
---|
1577 | }
|
---|
1578 |
|
---|
1579 |
|
---|
1580 | /** \brief Encode Priority
|
---|
1581 |
|
---|
1582 | The function encodes the priority for an interrupt with the given priority group,
|
---|
1583 | preemptive priority value, and subpriority value.
|
---|
1584 | In case of a conflict between priority grouping and available
|
---|
1585 | priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
|
---|
1586 |
|
---|
1587 | \param [in] PriorityGroup Used priority group.
|
---|
1588 | \param [in] PreemptPriority Preemptive priority value (starting from 0).
|
---|
1589 | \param [in] SubPriority Subpriority value (starting from 0).
|
---|
1590 | \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
|
---|
1591 | */
|
---|
1592 | __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
|
---|
1593 | {
|
---|
1594 | uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
|
---|
1595 | uint32_t PreemptPriorityBits;
|
---|
1596 | uint32_t SubPriorityBits;
|
---|
1597 |
|
---|
1598 | PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
|
---|
1599 | SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
|
---|
1600 |
|
---|
1601 | return (
|
---|
1602 | ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
|
---|
1603 | ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
|
---|
1604 | );
|
---|
1605 | }
|
---|
1606 |
|
---|
1607 |
|
---|
1608 | /** \brief Decode Priority
|
---|
1609 |
|
---|
1610 | The function decodes an interrupt priority value with a given priority group to
|
---|
1611 | preemptive priority value and subpriority value.
|
---|
1612 | In case of a conflict between priority grouping and available
|
---|
1613 | priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
|
---|
1614 |
|
---|
1615 | \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
|
---|
1616 | \param [in] PriorityGroup Used priority group.
|
---|
1617 | \param [out] pPreemptPriority Preemptive priority value (starting from 0).
|
---|
1618 | \param [out] pSubPriority Subpriority value (starting from 0).
|
---|
1619 | */
|
---|
1620 | __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
|
---|
1621 | {
|
---|
1622 | uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
|
---|
1623 | uint32_t PreemptPriorityBits;
|
---|
1624 | uint32_t SubPriorityBits;
|
---|
1625 |
|
---|
1626 | PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
|
---|
1627 | SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
|
---|
1628 |
|
---|
1629 | *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
|
---|
1630 | *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
|
---|
1631 | }
|
---|
1632 |
|
---|
1633 |
|
---|
1634 | /** \brief System Reset
|
---|
1635 |
|
---|
1636 | The function initiates a system reset request to reset the MCU.
|
---|
1637 | */
|
---|
1638 | __STATIC_INLINE void NVIC_SystemReset(void)
|
---|
1639 | {
|
---|
1640 | __DSB(); /* Ensure all outstanding memory accesses included
|
---|
1641 | buffered write are completed before reset */
|
---|
1642 | SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
|
---|
1643 | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
|
---|
1644 | SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
|
---|
1645 | __DSB(); /* Ensure completion of memory access */
|
---|
1646 | while(1); /* wait until reset */
|
---|
1647 | }
|
---|
1648 |
|
---|
1649 | /*@} end of CMSIS_Core_NVICFunctions */
|
---|
1650 |
|
---|
1651 |
|
---|
1652 |
|
---|
1653 | /* ################################## SysTick function ############################################ */
|
---|
1654 | /** \ingroup CMSIS_Core_FunctionInterface
|
---|
1655 | \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
|
---|
1656 | \brief Functions that configure the System.
|
---|
1657 | @{
|
---|
1658 | */
|
---|
1659 |
|
---|
1660 | #if (__Vendor_SysTickConfig == 0)
|
---|
1661 |
|
---|
1662 | /** \brief System Tick Configuration
|
---|
1663 |
|
---|
1664 | The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
|
---|
1665 | Counter is in free running mode to generate periodic interrupts.
|
---|
1666 |
|
---|
1667 | \param [in] ticks Number of ticks between two interrupts.
|
---|
1668 |
|
---|
1669 | \return 0 Function succeeded.
|
---|
1670 | \return 1 Function failed.
|
---|
1671 |
|
---|
1672 | \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
|
---|
1673 | function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
|
---|
1674 | must contain a vendor-specific implementation of this function.
|
---|
1675 |
|
---|
1676 | */
|
---|
1677 | __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
---|
1678 | {
|
---|
1679 | if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
|
---|
1680 |
|
---|
1681 | SysTick->LOAD = ticks - 1; /* set reload register */
|
---|
1682 | NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
|
---|
1683 | SysTick->VAL = 0; /* Load the SysTick Counter Value */
|
---|
1684 | SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
---|
1685 | SysTick_CTRL_TICKINT_Msk |
|
---|
1686 | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
|
---|
1687 | return (0); /* Function successful */
|
---|
1688 | }
|
---|
1689 |
|
---|
1690 | #endif
|
---|
1691 |
|
---|
1692 | /*@} end of CMSIS_Core_SysTickFunctions */
|
---|
1693 |
|
---|
1694 |
|
---|
1695 |
|
---|
1696 | /* ##################################### Debug In/Output function ########################################### */
|
---|
1697 | /** \ingroup CMSIS_Core_FunctionInterface
|
---|
1698 | \defgroup CMSIS_core_DebugFunctions ITM Functions
|
---|
1699 | \brief Functions that access the ITM debug interface.
|
---|
1700 | @{
|
---|
1701 | */
|
---|
1702 |
|
---|
1703 | extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
|
---|
1704 | #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
|
---|
1705 |
|
---|
1706 |
|
---|
1707 | /** \brief ITM Send Character
|
---|
1708 |
|
---|
1709 | The function transmits a character via the ITM channel 0, and
|
---|
1710 | \li Just returns when no debugger is connected that has booked the output.
|
---|
1711 | \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
|
---|
1712 |
|
---|
1713 | \param [in] ch Character to transmit.
|
---|
1714 |
|
---|
1715 | \returns Character to transmit.
|
---|
1716 | */
|
---|
1717 | __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
|
---|
1718 | {
|
---|
1719 | if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
|
---|
1720 | (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
|
---|
1721 | {
|
---|
1722 | while (ITM->PORT[0].u32 == 0);
|
---|
1723 | ITM->PORT[0].u8 = (uint8_t) ch;
|
---|
1724 | }
|
---|
1725 | return (ch);
|
---|
1726 | }
|
---|
1727 |
|
---|
1728 |
|
---|
1729 | /** \brief ITM Receive Character
|
---|
1730 |
|
---|
1731 | The function inputs a character via the external variable \ref ITM_RxBuffer.
|
---|
1732 |
|
---|
1733 | \return Received character.
|
---|
1734 | \return -1 No character pending.
|
---|
1735 | */
|
---|
1736 | __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
|
---|
1737 | int32_t ch = -1; /* no character available */
|
---|
1738 |
|
---|
1739 | if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
|
---|
1740 | ch = ITM_RxBuffer;
|
---|
1741 | ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
|
---|
1742 | }
|
---|
1743 |
|
---|
1744 | return (ch);
|
---|
1745 | }
|
---|
1746 |
|
---|
1747 |
|
---|
1748 | /** \brief ITM Check Character
|
---|
1749 |
|
---|
1750 | The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
|
---|
1751 |
|
---|
1752 | \return 0 No character available.
|
---|
1753 | \return 1 Character available.
|
---|
1754 | */
|
---|
1755 | __STATIC_INLINE int32_t ITM_CheckChar (void) {
|
---|
1756 |
|
---|
1757 | if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
|
---|
1758 | return (0); /* no character available */
|
---|
1759 | } else {
|
---|
1760 | return (1); /* character available */
|
---|
1761 | }
|
---|
1762 | }
|
---|
1763 |
|
---|
1764 | /*@} end of CMSIS_core_DebugFunctions */
|
---|
1765 |
|
---|
1766 | #endif /* __CORE_CM4_H_DEPENDANT */
|
---|
1767 |
|
---|
1768 | #endif /* __CMSIS_GENERIC */
|
---|
1769 |
|
---|
1770 | #ifdef __cplusplus
|
---|
1771 | }
|
---|
1772 | #endif
|
---|