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1/**************************************************************************//**
2 * @file core_cm3.h
3 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
4 * @version V3.20
5 * @date 25. February 2013
6 *
7 * @note
8 *
9 ******************************************************************************/
10/* Copyright (c) 2009 - 2013 ARM LIMITED
11
12 All rights reserved.
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 - Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 - Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 - Neither the name of ARM nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23 *
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ---------------------------------------------------------------------------*/
36
37
38#if defined ( __ICCARM__ )
39 #pragma system_include /* treat file as system include file for MISRA check */
40#endif
41
42#ifdef __cplusplus
43 extern "C" {
44#endif
45
46#ifndef __CORE_CM3_H_GENERIC
47#define __CORE_CM3_H_GENERIC
48
49/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
50 CMSIS violates the following MISRA-C:2004 rules:
51
52 \li Required Rule 8.5, object/function definition in header file.<br>
53 Function definitions in header files are used to allow 'inlining'.
54
55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
56 Unions are used for effective representation of core registers.
57
58 \li Advisory Rule 19.7, Function-like macro defined.<br>
59 Function-like macros are used to allow more efficient code.
60 */
61
62
63/*******************************************************************************
64 * CMSIS definitions
65 ******************************************************************************/
66/** \ingroup Cortex_M3
67 @{
68 */
69
70/* CMSIS CM3 definitions */
71#define __CM3_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
72#define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
73#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \
74 __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
75
76#define __CORTEX_M (0x03) /*!< Cortex-M Core */
77
78
79#if defined ( __CC_ARM )
80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
82 #define __STATIC_INLINE static __inline
83
84#elif defined ( __ICCARM__ )
85 #define __ASM __asm /*!< asm keyword for IAR Compiler */
86 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
87 #define __STATIC_INLINE static inline
88
89#elif defined ( __TMS470__ )
90 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
91 #define __STATIC_INLINE static inline
92
93#elif defined ( __GNUC__ )
94 #define __ASM __asm /*!< asm keyword for GNU Compiler */
95 #define __INLINE inline /*!< inline keyword for GNU Compiler */
96 #define __STATIC_INLINE static inline
97
98#elif defined ( __TASKING__ )
99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
101 #define __STATIC_INLINE static inline
102
103#endif
104
105/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
106*/
107#define __FPU_USED 0
108
109#if defined ( __CC_ARM )
110 #if defined __TARGET_FPU_VFP
111 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
112 #endif
113
114#elif defined ( __ICCARM__ )
115 #if defined __ARMVFP__
116 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
117 #endif
118
119#elif defined ( __TMS470__ )
120 #if defined __TI__VFP_SUPPORT____
121 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
122 #endif
123
124#elif defined ( __GNUC__ )
125 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
126 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
127 #endif
128
129#elif defined ( __TASKING__ )
130 #if defined __FPU_VFP__
131 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
132 #endif
133#endif
134
135#include <stdint.h> /* standard types definitions */
136#include <core_cmInstr.h> /* Core Instruction Access */
137#include <core_cmFunc.h> /* Core Function Access */
138
139#endif /* __CORE_CM3_H_GENERIC */
140
141#ifndef __CMSIS_GENERIC
142
143#ifndef __CORE_CM3_H_DEPENDANT
144#define __CORE_CM3_H_DEPENDANT
145
146/* check device defines and use defaults */
147#if defined __CHECK_DEVICE_DEFINES
148 #ifndef __CM3_REV
149 #define __CM3_REV 0x0200
150 #warning "__CM3_REV not defined in device header file; using default!"
151 #endif
152
153 #ifndef __MPU_PRESENT
154 #define __MPU_PRESENT 0
155 #warning "__MPU_PRESENT not defined in device header file; using default!"
156 #endif
157
158 #ifndef __NVIC_PRIO_BITS
159 #define __NVIC_PRIO_BITS 4
160 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
161 #endif
162
163 #ifndef __Vendor_SysTickConfig
164 #define __Vendor_SysTickConfig 0
165 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
166 #endif
167#endif
168
169/* IO definitions (access restrictions to peripheral registers) */
170/**
171 \defgroup CMSIS_glob_defs CMSIS Global Defines
172
173 <strong>IO Type Qualifiers</strong> are used
174 \li to specify the access to peripheral variables.
175 \li for automatic generation of peripheral register debug information.
176*/
177#ifdef __cplusplus
178 #define __I volatile /*!< Defines 'read only' permissions */
179#else
180 #define __I volatile const /*!< Defines 'read only' permissions */
181#endif
182#define __O volatile /*!< Defines 'write only' permissions */
183#define __IO volatile /*!< Defines 'read / write' permissions */
184
185/*@} end of group Cortex_M3 */
186
187
188
189/*******************************************************************************
190 * Register Abstraction
191 Core Register contain:
192 - Core Register
193 - Core NVIC Register
194 - Core SCB Register
195 - Core SysTick Register
196 - Core Debug Register
197 - Core MPU Register
198 ******************************************************************************/
199/** \defgroup CMSIS_core_register Defines and Type Definitions
200 \brief Type definitions and defines for Cortex-M processor based devices.
201*/
202
203/** \ingroup CMSIS_core_register
204 \defgroup CMSIS_CORE Status and Control Registers
205 \brief Core Register type definitions.
206 @{
207 */
208
209/** \brief Union type to access the Application Program Status Register (APSR).
210 */
211typedef union
212{
213 struct
214 {
215#if (__CORTEX_M != 0x04)
216 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
217#else
218 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
219 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
220 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
221#endif
222 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
223 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
224 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
225 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
226 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
227 } b; /*!< Structure used for bit access */
228 uint32_t w; /*!< Type used for word access */
229} APSR_Type;
230
231
232/** \brief Union type to access the Interrupt Program Status Register (IPSR).
233 */
234typedef union
235{
236 struct
237 {
238 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
239 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
240 } b; /*!< Structure used for bit access */
241 uint32_t w; /*!< Type used for word access */
242} IPSR_Type;
243
244
245/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
246 */
247typedef union
248{
249 struct
250 {
251 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
252#if (__CORTEX_M != 0x04)
253 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
254#else
255 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
256 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
257 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
258#endif
259 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
260 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
261 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
262 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
263 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
264 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
265 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
266 } b; /*!< Structure used for bit access */
267 uint32_t w; /*!< Type used for word access */
268} xPSR_Type;
269
270
271/** \brief Union type to access the Control Registers (CONTROL).
272 */
273typedef union
274{
275 struct
276 {
277 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
278 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
279 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
280 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
281 } b; /*!< Structure used for bit access */
282 uint32_t w; /*!< Type used for word access */
283} CONTROL_Type;
284
285/*@} end of group CMSIS_CORE */
286
287
288/** \ingroup CMSIS_core_register
289 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
290 \brief Type definitions for the NVIC Registers
291 @{
292 */
293
294/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
295 */
296typedef struct
297{
298 __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
299 uint32_t RESERVED0[24];
300 __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
301 uint32_t RSERVED1[24];
302 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
303 uint32_t RESERVED2[24];
304 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
305 uint32_t RESERVED3[24];
306 __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
307 uint32_t RESERVED4[56];
308 __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
309 uint32_t RESERVED5[644];
310 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
311} NVIC_Type;
312
313/* Software Triggered Interrupt Register Definitions */
314#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
315#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
316
317/*@} end of group CMSIS_NVIC */
318
319
320/** \ingroup CMSIS_core_register
321 \defgroup CMSIS_SCB System Control Block (SCB)
322 \brief Type definitions for the System Control Block Registers
323 @{
324 */
325
326/** \brief Structure type to access the System Control Block (SCB).
327 */
328typedef struct
329{
330 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
331 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
332 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
333 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
334 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
335 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
336 __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
337 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
338 __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
339 __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
340 __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
341 __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
342 __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
343 __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
344 __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
345 __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
346 __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
347 __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
348 __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
349 uint32_t RESERVED0[5];
350 __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
351} SCB_Type;
352
353/* SCB CPUID Register Definitions */
354#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
355#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
356
357#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
358#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
359
360#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
361#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
362
363#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
364#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
365
366#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
367#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
368
369/* SCB Interrupt Control State Register Definitions */
370#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
371#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
372
373#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
374#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
375
376#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
377#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
378
379#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
380#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
381
382#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
383#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
384
385#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
386#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
387
388#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
389#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
390
391#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
392#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
393
394#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
395#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
396
397#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
398#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
399
400/* SCB Vector Table Offset Register Definitions */
401#if (__CM3_REV < 0x0201) /* core r2p1 */
402#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
403#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
404
405#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
406#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
407#else
408#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
409#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
410#endif
411
412/* SCB Application Interrupt and Reset Control Register Definitions */
413#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
414#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
415
416#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
417#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
418
419#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
420#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
421
422#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
423#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
424
425#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
426#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
427
428#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
429#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
430
431#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
432#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
433
434/* SCB System Control Register Definitions */
435#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
436#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
437
438#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
439#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
440
441#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
442#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
443
444/* SCB Configuration Control Register Definitions */
445#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
446#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
447
448#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
449#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
450
451#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
452#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
453
454#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
455#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
456
457#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
458#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
459
460#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
461#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
462
463/* SCB System Handler Control and State Register Definitions */
464#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
465#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
466
467#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
468#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
469
470#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
471#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
472
473#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
474#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
475
476#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
477#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
478
479#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
480#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
481
482#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
483#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
484
485#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
486#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
487
488#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
489#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
490
491#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
492#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
493
494#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
495#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
496
497#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
498#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
499
500#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
501#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
502
503#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
504#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
505
506/* SCB Configurable Fault Status Registers Definitions */
507#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
508#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
509
510#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
511#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
512
513#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
514#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
515
516/* SCB Hard Fault Status Registers Definitions */
517#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
518#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
519
520#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
521#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
522
523#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
524#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
525
526/* SCB Debug Fault Status Register Definitions */
527#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
528#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
529
530#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
531#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
532
533#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
534#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
535
536#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
537#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
538
539#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
540#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
541
542/*@} end of group CMSIS_SCB */
543
544
545/** \ingroup CMSIS_core_register
546 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
547 \brief Type definitions for the System Control and ID Register not in the SCB
548 @{
549 */
550
551/** \brief Structure type to access the System Control and ID Register not in the SCB.
552 */
553typedef struct
554{
555 uint32_t RESERVED0[1];
556 __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
557#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
558 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
559#else
560 uint32_t RESERVED1[1];
561#endif
562} SCnSCB_Type;
563
564/* Interrupt Controller Type Register Definitions */
565#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
566#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
567
568/* Auxiliary Control Register Definitions */
569
570#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
571#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
572
573#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
574#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
575
576#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
577#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
578
579/*@} end of group CMSIS_SCnotSCB */
580
581
582/** \ingroup CMSIS_core_register
583 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
584 \brief Type definitions for the System Timer Registers.
585 @{
586 */
587
588/** \brief Structure type to access the System Timer (SysTick).
589 */
590typedef struct
591{
592 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
593 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
594 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
595 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
596} SysTick_Type;
597
598/* SysTick Control / Status Register Definitions */
599#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
600#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
601
602#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
603#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
604
605#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
606#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
607
608#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
609#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
610
611/* SysTick Reload Register Definitions */
612#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
613#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
614
615/* SysTick Current Register Definitions */
616#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
617#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
618
619/* SysTick Calibration Register Definitions */
620#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
621#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
622
623#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
624#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
625
626#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
627#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
628
629/*@} end of group CMSIS_SysTick */
630
631
632/** \ingroup CMSIS_core_register
633 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
634 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
635 @{
636 */
637
638/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
639 */
640typedef struct
641{
642 __O union
643 {
644 __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
645 __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
646 __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
647 } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
648 uint32_t RESERVED0[864];
649 __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
650 uint32_t RESERVED1[15];
651 __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
652 uint32_t RESERVED2[15];
653 __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
654 uint32_t RESERVED3[29];
655 __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
656 __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
657 __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
658 uint32_t RESERVED4[43];
659 __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
660 __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
661 uint32_t RESERVED5[6];
662 __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
663 __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
664 __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
665 __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
666 __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
667 __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
668 __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
669 __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
670 __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
671 __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
672 __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
673 __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
674} ITM_Type;
675
676/* ITM Trace Privilege Register Definitions */
677#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
678#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
679
680/* ITM Trace Control Register Definitions */
681#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
682#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
683
684#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
685#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
686
687#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
688#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
689
690#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
691#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
692
693#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
694#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
695
696#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
697#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
698
699#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
700#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
701
702#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
703#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
704
705#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
706#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
707
708/* ITM Integration Write Register Definitions */
709#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
710#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
711
712/* ITM Integration Read Register Definitions */
713#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
714#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
715
716/* ITM Integration Mode Control Register Definitions */
717#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
718#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
719
720/* ITM Lock Status Register Definitions */
721#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
722#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
723
724#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
725#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
726
727#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
728#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
729
730/*@}*/ /* end of group CMSIS_ITM */
731
732
733/** \ingroup CMSIS_core_register
734 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
735 \brief Type definitions for the Data Watchpoint and Trace (DWT)
736 @{
737 */
738
739/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
740 */
741typedef struct
742{
743 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
744 __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
745 __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
746 __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
747 __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
748 __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
749 __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
750 __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
751 __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
752 __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
753 __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
754 uint32_t RESERVED0[1];
755 __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
756 __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
757 __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
758 uint32_t RESERVED1[1];
759 __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
760 __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
761 __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
762 uint32_t RESERVED2[1];
763 __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
764 __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
765 __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
766} DWT_Type;
767
768/* DWT Control Register Definitions */
769#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
770#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
771
772#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
773#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
774
775#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
776#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
777
778#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
779#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
780
781#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
782#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
783
784#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
785#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
786
787#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
788#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
789
790#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
791#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
792
793#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
794#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
795
796#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
797#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
798
799#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
800#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
801
802#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
803#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
804
805#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
806#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
807
808#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
809#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
810
811#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
812#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
813
814#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
815#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
816
817#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
818#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
819
820#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
821#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */
822
823/* DWT CPI Count Register Definitions */
824#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
825#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */
826
827/* DWT Exception Overhead Count Register Definitions */
828#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
829#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */
830
831/* DWT Sleep Count Register Definitions */
832#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
833#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
834
835/* DWT LSU Count Register Definitions */
836#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
837#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */
838
839/* DWT Folded-instruction Count Register Definitions */
840#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
841#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */
842
843/* DWT Comparator Mask Register Definitions */
844#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
845#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */
846
847/* DWT Comparator Function Register Definitions */
848#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
849#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
850
851#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
852#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
853
854#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
855#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
856
857#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
858#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
859
860#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
861#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
862
863#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
864#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
865
866#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
867#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
868
869#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
870#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
871
872#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
873#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */
874
875/*@}*/ /* end of group CMSIS_DWT */
876
877
878/** \ingroup CMSIS_core_register
879 \defgroup CMSIS_TPI Trace Port Interface (TPI)
880 \brief Type definitions for the Trace Port Interface (TPI)
881 @{
882 */
883
884/** \brief Structure type to access the Trace Port Interface Register (TPI).
885 */
886typedef struct
887{
888 __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
889 __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
890 uint32_t RESERVED0[2];
891 __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
892 uint32_t RESERVED1[55];
893 __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
894 uint32_t RESERVED2[131];
895 __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
896 __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
897 __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
898 uint32_t RESERVED3[759];
899 __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
900 __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
901 __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
902 uint32_t RESERVED4[1];
903 __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
904 __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
905 __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
906 uint32_t RESERVED5[39];
907 __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
908 __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
909 uint32_t RESERVED7[8];
910 __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
911 __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
912} TPI_Type;
913
914/* TPI Asynchronous Clock Prescaler Register Definitions */
915#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
916#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */
917
918/* TPI Selected Pin Protocol Register Definitions */
919#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
920#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */
921
922/* TPI Formatter and Flush Status Register Definitions */
923#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
924#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
925
926#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
927#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
928
929#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
930#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
931
932#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
933#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */
934
935/* TPI Formatter and Flush Control Register Definitions */
936#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
937#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
938
939#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
940#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
941
942/* TPI TRIGGER Register Definitions */
943#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
944#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */
945
946/* TPI Integration ETM Data Register Definitions (FIFO0) */
947#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
948#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
949
950#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
951#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
952
953#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
954#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
955
956#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
957#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
958
959#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
960#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
961
962#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
963#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
964
965#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
966#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */
967
968/* TPI ITATBCTR2 Register Definitions */
969#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
970#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */
971
972/* TPI Integration ITM Data Register Definitions (FIFO1) */
973#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
974#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
975
976#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
977#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
978
979#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
980#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
981
982#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
983#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
984
985#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
986#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
987
988#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
989#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
990
991#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
992#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */
993
994/* TPI ITATBCTR0 Register Definitions */
995#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
996#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */
997
998/* TPI Integration Mode Control Register Definitions */
999#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
1000#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */
1001
1002/* TPI DEVID Register Definitions */
1003#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
1004#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
1005
1006#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
1007#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
1008
1009#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
1010#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
1011
1012#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
1013#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
1014
1015#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
1016#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
1017
1018#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
1019#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */
1020
1021/* TPI DEVTYPE Register Definitions */
1022#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
1023#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */
1024
1025#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
1026#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
1027
1028/*@}*/ /* end of group CMSIS_TPI */
1029
1030
1031#if (__MPU_PRESENT == 1)
1032/** \ingroup CMSIS_core_register
1033 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
1034 \brief Type definitions for the Memory Protection Unit (MPU)
1035 @{
1036 */
1037
1038/** \brief Structure type to access the Memory Protection Unit (MPU).
1039 */
1040typedef struct
1041{
1042 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
1043 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
1044 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
1045 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
1046 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
1047 __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
1048 __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
1049 __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
1050 __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
1051 __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
1052 __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
1053} MPU_Type;
1054
1055/* MPU Type Register */
1056#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
1057#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
1058
1059#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
1060#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
1061
1062#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
1063#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
1064
1065/* MPU Control Register */
1066#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
1067#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
1068
1069#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
1070#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
1071
1072#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
1073#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
1074
1075/* MPU Region Number Register */
1076#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
1077#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
1078
1079/* MPU Region Base Address Register */
1080#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
1081#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
1082
1083#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
1084#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
1085
1086#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
1087#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
1088
1089/* MPU Region Attribute and Size Register */
1090#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
1091#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
1092
1093#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
1094#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
1095
1096#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
1097#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
1098
1099#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
1100#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
1101
1102#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
1103#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
1104
1105#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
1106#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
1107
1108#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
1109#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
1110
1111#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
1112#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
1113
1114#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
1115#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
1116
1117#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
1118#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
1119
1120/*@} end of group CMSIS_MPU */
1121#endif
1122
1123
1124/** \ingroup CMSIS_core_register
1125 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
1126 \brief Type definitions for the Core Debug Registers
1127 @{
1128 */
1129
1130/** \brief Structure type to access the Core Debug Register (CoreDebug).
1131 */
1132typedef struct
1133{
1134 __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
1135 __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
1136 __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
1137 __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
1138} CoreDebug_Type;
1139
1140/* Debug Halting Control and Status Register */
1141#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
1142#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
1143
1144#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
1145#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
1146
1147#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
1148#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
1149
1150#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
1151#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
1152
1153#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
1154#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
1155
1156#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
1157#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
1158
1159#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
1160#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
1161
1162#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
1163#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
1164
1165#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
1166#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
1167
1168#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
1169#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
1170
1171#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
1172#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
1173
1174#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
1175#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
1176
1177/* Debug Core Register Selector Register */
1178#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
1179#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
1180
1181#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
1182#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
1183
1184/* Debug Exception and Monitor Control Register */
1185#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
1186#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
1187
1188#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
1189#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
1190
1191#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
1192#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
1193
1194#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
1195#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
1196
1197#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
1198#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
1199
1200#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
1201#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
1202
1203#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
1204#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
1205
1206#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
1207#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
1208
1209#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
1210#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
1211
1212#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
1213#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
1214
1215#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
1216#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
1217
1218#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
1219#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
1220
1221#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
1222#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
1223
1224/*@} end of group CMSIS_CoreDebug */
1225
1226
1227/** \ingroup CMSIS_core_register
1228 \defgroup CMSIS_core_base Core Definitions
1229 \brief Definitions for base addresses, unions, and structures.
1230 @{
1231 */
1232
1233/* Memory mapping of Cortex-M3 Hardware */
1234#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
1235#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
1236#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
1237#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
1238#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
1239#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
1240#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
1241#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
1242
1243#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
1244#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
1245#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
1246#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
1247#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
1248#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
1249#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
1250#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
1251
1252#if (__MPU_PRESENT == 1)
1253 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
1254 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
1255#endif
1256
1257/*@} */
1258
1259
1260
1261/*******************************************************************************
1262 * Hardware Abstraction Layer
1263 Core Function Interface contains:
1264 - Core NVIC Functions
1265 - Core SysTick Functions
1266 - Core Debug Functions
1267 - Core Register Access Functions
1268 ******************************************************************************/
1269/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
1270*/
1271
1272
1273
1274/* ########################## NVIC functions #################################### */
1275/** \ingroup CMSIS_Core_FunctionInterface
1276 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
1277 \brief Functions that manage interrupts and exceptions via the NVIC.
1278 @{
1279 */
1280
1281/** \brief Set Priority Grouping
1282
1283 The function sets the priority grouping field using the required unlock sequence.
1284 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
1285 Only values from 0..7 are used.
1286 In case of a conflict between priority grouping and available
1287 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
1288
1289 \param [in] PriorityGroup Priority grouping field.
1290 */
1291__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
1292{
1293 uint32_t reg_value;
1294 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
1295
1296 reg_value = SCB->AIRCR; /* read old register configuration */
1297 reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
1298 reg_value = (reg_value |
1299 ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
1300 (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
1301 SCB->AIRCR = reg_value;
1302}
1303
1304
1305/** \brief Get Priority Grouping
1306
1307 The function reads the priority grouping field from the NVIC Interrupt Controller.
1308
1309 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
1310 */
1311__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
1312{
1313 return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
1314}
1315
1316
1317/** \brief Enable External Interrupt
1318
1319 The function enables a device-specific interrupt in the NVIC interrupt controller.
1320
1321 \param [in] IRQn External interrupt number. Value cannot be negative.
1322 */
1323__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
1324{
1325 NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
1326}
1327
1328
1329/** \brief Disable External Interrupt
1330
1331 The function disables a device-specific interrupt in the NVIC interrupt controller.
1332
1333 \param [in] IRQn External interrupt number. Value cannot be negative.
1334 */
1335__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
1336{
1337 NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
1338}
1339
1340
1341/** \brief Get Pending Interrupt
1342
1343 The function reads the pending register in the NVIC and returns the pending bit
1344 for the specified interrupt.
1345
1346 \param [in] IRQn Interrupt number.
1347
1348 \return 0 Interrupt status is not pending.
1349 \return 1 Interrupt status is pending.
1350 */
1351__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
1352{
1353 return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
1354}
1355
1356
1357/** \brief Set Pending Interrupt
1358
1359 The function sets the pending bit of an external interrupt.
1360
1361 \param [in] IRQn Interrupt number. Value cannot be negative.
1362 */
1363__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
1364{
1365 NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
1366}
1367
1368
1369/** \brief Clear Pending Interrupt
1370
1371 The function clears the pending bit of an external interrupt.
1372
1373 \param [in] IRQn External interrupt number. Value cannot be negative.
1374 */
1375__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
1376{
1377 NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
1378}
1379
1380
1381/** \brief Get Active Interrupt
1382
1383 The function reads the active register in NVIC and returns the active bit.
1384
1385 \param [in] IRQn Interrupt number.
1386
1387 \return 0 Interrupt status is not active.
1388 \return 1 Interrupt status is active.
1389 */
1390__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
1391{
1392 return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
1393}
1394
1395
1396/** \brief Set Interrupt Priority
1397
1398 The function sets the priority of an interrupt.
1399
1400 \note The priority cannot be set for every core interrupt.
1401
1402 \param [in] IRQn Interrupt number.
1403 \param [in] priority Priority to set.
1404 */
1405__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
1406{
1407 if(IRQn < 0) {
1408 SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
1409 else {
1410 NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
1411}
1412
1413
1414/** \brief Get Interrupt Priority
1415
1416 The function reads the priority of an interrupt. The interrupt
1417 number can be positive to specify an external (device specific)
1418 interrupt, or negative to specify an internal (core) interrupt.
1419
1420
1421 \param [in] IRQn Interrupt number.
1422 \return Interrupt Priority. Value is aligned automatically to the implemented
1423 priority bits of the microcontroller.
1424 */
1425__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
1426{
1427
1428 if(IRQn < 0) {
1429 return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
1430 else {
1431 return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
1432}
1433
1434
1435/** \brief Encode Priority
1436
1437 The function encodes the priority for an interrupt with the given priority group,
1438 preemptive priority value, and subpriority value.
1439 In case of a conflict between priority grouping and available
1440 priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
1441
1442 \param [in] PriorityGroup Used priority group.
1443 \param [in] PreemptPriority Preemptive priority value (starting from 0).
1444 \param [in] SubPriority Subpriority value (starting from 0).
1445 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
1446 */
1447__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
1448{
1449 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
1450 uint32_t PreemptPriorityBits;
1451 uint32_t SubPriorityBits;
1452
1453 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
1454 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
1455
1456 return (
1457 ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
1458 ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
1459 );
1460}
1461
1462
1463/** \brief Decode Priority
1464
1465 The function decodes an interrupt priority value with a given priority group to
1466 preemptive priority value and subpriority value.
1467 In case of a conflict between priority grouping and available
1468 priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
1469
1470 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
1471 \param [in] PriorityGroup Used priority group.
1472 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
1473 \param [out] pSubPriority Subpriority value (starting from 0).
1474 */
1475__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
1476{
1477 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
1478 uint32_t PreemptPriorityBits;
1479 uint32_t SubPriorityBits;
1480
1481 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
1482 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
1483
1484 *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
1485 *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
1486}
1487
1488
1489/** \brief System Reset
1490
1491 The function initiates a system reset request to reset the MCU.
1492 */
1493__STATIC_INLINE void NVIC_SystemReset(void)
1494{
1495 __DSB(); /* Ensure all outstanding memory accesses included
1496 buffered write are completed before reset */
1497 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
1498 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
1499 SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
1500 __DSB(); /* Ensure completion of memory access */
1501 while(1); /* wait until reset */
1502}
1503
1504/*@} end of CMSIS_Core_NVICFunctions */
1505
1506
1507
1508/* ################################## SysTick function ############################################ */
1509/** \ingroup CMSIS_Core_FunctionInterface
1510 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
1511 \brief Functions that configure the System.
1512 @{
1513 */
1514
1515#if (__Vendor_SysTickConfig == 0)
1516
1517/** \brief System Tick Configuration
1518
1519 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
1520 Counter is in free running mode to generate periodic interrupts.
1521
1522 \param [in] ticks Number of ticks between two interrupts.
1523
1524 \return 0 Function succeeded.
1525 \return 1 Function failed.
1526
1527 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
1528 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
1529 must contain a vendor-specific implementation of this function.
1530
1531 */
1532__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
1533{
1534 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
1535
1536 SysTick->LOAD = ticks - 1; /* set reload register */
1537 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
1538 SysTick->VAL = 0; /* Load the SysTick Counter Value */
1539 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
1540 SysTick_CTRL_TICKINT_Msk |
1541 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
1542 return (0); /* Function successful */
1543}
1544
1545#endif
1546
1547/*@} end of CMSIS_Core_SysTickFunctions */
1548
1549
1550
1551/* ##################################### Debug In/Output function ########################################### */
1552/** \ingroup CMSIS_Core_FunctionInterface
1553 \defgroup CMSIS_core_DebugFunctions ITM Functions
1554 \brief Functions that access the ITM debug interface.
1555 @{
1556 */
1557
1558extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
1559#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
1560
1561
1562/** \brief ITM Send Character
1563
1564 The function transmits a character via the ITM channel 0, and
1565 \li Just returns when no debugger is connected that has booked the output.
1566 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
1567
1568 \param [in] ch Character to transmit.
1569
1570 \returns Character to transmit.
1571 */
1572__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
1573{
1574 if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
1575 (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
1576 {
1577 while (ITM->PORT[0].u32 == 0);
1578 ITM->PORT[0].u8 = (uint8_t) ch;
1579 }
1580 return (ch);
1581}
1582
1583
1584/** \brief ITM Receive Character
1585
1586 The function inputs a character via the external variable \ref ITM_RxBuffer.
1587
1588 \return Received character.
1589 \return -1 No character pending.
1590 */
1591__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
1592 int32_t ch = -1; /* no character available */
1593
1594 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
1595 ch = ITM_RxBuffer;
1596 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
1597 }
1598
1599 return (ch);
1600}
1601
1602
1603/** \brief ITM Check Character
1604
1605 The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
1606
1607 \return 0 No character available.
1608 \return 1 Character available.
1609 */
1610__STATIC_INLINE int32_t ITM_CheckChar (void) {
1611
1612 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
1613 return (0); /* no character available */
1614 } else {
1615 return (1); /* character available */
1616 }
1617}
1618
1619/*@} end of CMSIS_core_DebugFunctions */
1620
1621#endif /* __CORE_CM3_H_DEPENDANT */
1622
1623#endif /* __CMSIS_GENERIC */
1624
1625#ifdef __cplusplus
1626}
1627#endif
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