source: EcnlProtoTool/trunk/asp3_dcre/mbed/targets/cmsis/core_cm0plus.h@ 321

Last change on this file since 321 was 321, checked in by coas-nagasima, 7 years ago

文字コードを設定
  • Property svn:eol-style set to native
  • Property svn:mime-type set to text/x-chdr;charset=UTF-8
File size: 38.7 KB
Line 
1/**************************************************************************//**
2 * @file core_cm0plus.h
3 * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
4 * @version V3.20
5 * @date 25. February 2013
6 *
7 * @note
8 *
9 ******************************************************************************/
10/* Copyright (c) 2009 - 2013 ARM LIMITED
11
12 All rights reserved.
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 - Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 - Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 - Neither the name of ARM nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23 *
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ---------------------------------------------------------------------------*/
36
37
38#if defined ( __ICCARM__ )
39 #pragma system_include /* treat file as system include file for MISRA check */
40#endif
41
42#ifdef __cplusplus
43 extern "C" {
44#endif
45
46#ifndef __CORE_CM0PLUS_H_GENERIC
47#define __CORE_CM0PLUS_H_GENERIC
48
49/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
50 CMSIS violates the following MISRA-C:2004 rules:
51
52 \li Required Rule 8.5, object/function definition in header file.<br>
53 Function definitions in header files are used to allow 'inlining'.
54
55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
56 Unions are used for effective representation of core registers.
57
58 \li Advisory Rule 19.7, Function-like macro defined.<br>
59 Function-like macros are used to allow more efficient code.
60 */
61
62
63/*******************************************************************************
64 * CMSIS definitions
65 ******************************************************************************/
66/** \ingroup Cortex-M0+
67 @{
68 */
69
70/* CMSIS CM0P definitions */
71#define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
72#define __CM0PLUS_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
73#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
74 __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
75
76#define __CORTEX_M (0x00) /*!< Cortex-M Core */
77
78
79#if defined ( __CC_ARM )
80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
82 #define __STATIC_INLINE static __inline
83
84#elif defined ( __ICCARM__ )
85 #define __ASM __asm /*!< asm keyword for IAR Compiler */
86 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
87 #define __STATIC_INLINE static inline
88
89#elif defined ( __GNUC__ )
90 #define __ASM __asm /*!< asm keyword for GNU Compiler */
91 #define __INLINE inline /*!< inline keyword for GNU Compiler */
92 #define __STATIC_INLINE static inline
93
94#elif defined ( __TASKING__ )
95 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
96 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
97 #define __STATIC_INLINE static inline
98
99#endif
100
101/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
102*/
103#define __FPU_USED 0
104
105#if defined ( __CC_ARM )
106 #if defined __TARGET_FPU_VFP
107 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
108 #endif
109
110#elif defined ( __ICCARM__ )
111 #if defined __ARMVFP__
112 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
113 #endif
114
115#elif defined ( __GNUC__ )
116 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
117 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
118 #endif
119
120#elif defined ( __TASKING__ )
121 #if defined __FPU_VFP__
122 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
123 #endif
124#endif
125
126#include <stdint.h> /* standard types definitions */
127#include <core_cmInstr.h> /* Core Instruction Access */
128#include <core_cmFunc.h> /* Core Function Access */
129
130#endif /* __CORE_CM0PLUS_H_GENERIC */
131
132#ifndef __CMSIS_GENERIC
133
134#ifndef __CORE_CM0PLUS_H_DEPENDANT
135#define __CORE_CM0PLUS_H_DEPENDANT
136
137/* check device defines and use defaults */
138#if defined __CHECK_DEVICE_DEFINES
139 #ifndef __CM0PLUS_REV
140 #define __CM0PLUS_REV 0x0000
141 #warning "__CM0PLUS_REV not defined in device header file; using default!"
142 #endif
143
144 #ifndef __MPU_PRESENT
145 #define __MPU_PRESENT 0
146 #warning "__MPU_PRESENT not defined in device header file; using default!"
147 #endif
148
149 #ifndef __VTOR_PRESENT
150 #define __VTOR_PRESENT 0
151 #warning "__VTOR_PRESENT not defined in device header file; using default!"
152 #endif
153
154 #ifndef __NVIC_PRIO_BITS
155 #define __NVIC_PRIO_BITS 2
156 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
157 #endif
158
159 #ifndef __Vendor_SysTickConfig
160 #define __Vendor_SysTickConfig 0
161 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
162 #endif
163#endif
164
165/* IO definitions (access restrictions to peripheral registers) */
166/**
167 \defgroup CMSIS_glob_defs CMSIS Global Defines
168
169 <strong>IO Type Qualifiers</strong> are used
170 \li to specify the access to peripheral variables.
171 \li for automatic generation of peripheral register debug information.
172*/
173#ifdef __cplusplus
174 #define __I volatile /*!< Defines 'read only' permissions */
175#else
176 #define __I volatile const /*!< Defines 'read only' permissions */
177#endif
178#define __O volatile /*!< Defines 'write only' permissions */
179#define __IO volatile /*!< Defines 'read / write' permissions */
180
181/*@} end of group Cortex-M0+ */
182
183
184
185/*******************************************************************************
186 * Register Abstraction
187 Core Register contain:
188 - Core Register
189 - Core NVIC Register
190 - Core SCB Register
191 - Core SysTick Register
192 - Core MPU Register
193 ******************************************************************************/
194/** \defgroup CMSIS_core_register Defines and Type Definitions
195 \brief Type definitions and defines for Cortex-M processor based devices.
196*/
197
198/** \ingroup CMSIS_core_register
199 \defgroup CMSIS_CORE Status and Control Registers
200 \brief Core Register type definitions.
201 @{
202 */
203
204/** \brief Union type to access the Application Program Status Register (APSR).
205 */
206typedef union
207{
208 struct
209 {
210#if (__CORTEX_M != 0x04)
211 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
212#else
213 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
214 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
215 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
216#endif
217 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
218 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
219 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
220 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
221 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
222 } b; /*!< Structure used for bit access */
223 uint32_t w; /*!< Type used for word access */
224} APSR_Type;
225
226
227/** \brief Union type to access the Interrupt Program Status Register (IPSR).
228 */
229typedef union
230{
231 struct
232 {
233 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
234 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
235 } b; /*!< Structure used for bit access */
236 uint32_t w; /*!< Type used for word access */
237} IPSR_Type;
238
239
240/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
241 */
242typedef union
243{
244 struct
245 {
246 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
247#if (__CORTEX_M != 0x04)
248 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
249#else
250 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
251 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
252 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
253#endif
254 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
255 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
256 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
257 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
258 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
259 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
260 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
261 } b; /*!< Structure used for bit access */
262 uint32_t w; /*!< Type used for word access */
263} xPSR_Type;
264
265
266/** \brief Union type to access the Control Registers (CONTROL).
267 */
268typedef union
269{
270 struct
271 {
272 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
273 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
274 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
275 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
276 } b; /*!< Structure used for bit access */
277 uint32_t w; /*!< Type used for word access */
278} CONTROL_Type;
279
280/*@} end of group CMSIS_CORE */
281
282
283/** \ingroup CMSIS_core_register
284 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
285 \brief Type definitions for the NVIC Registers
286 @{
287 */
288
289/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
290 */
291typedef struct
292{
293 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
294 uint32_t RESERVED0[31];
295 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
296 uint32_t RSERVED1[31];
297 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
298 uint32_t RESERVED2[31];
299 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
300 uint32_t RESERVED3[31];
301 uint32_t RESERVED4[64];
302 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
303} NVIC_Type;
304
305/*@} end of group CMSIS_NVIC */
306
307
308/** \ingroup CMSIS_core_register
309 \defgroup CMSIS_SCB System Control Block (SCB)
310 \brief Type definitions for the System Control Block Registers
311 @{
312 */
313
314/** \brief Structure type to access the System Control Block (SCB).
315 */
316typedef struct
317{
318 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
319 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
320#if (__VTOR_PRESENT == 1)
321 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
322#else
323 uint32_t RESERVED0;
324#endif
325 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
326 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
327 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
328 uint32_t RESERVED1;
329 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
330 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
331} SCB_Type;
332
333/* SCB CPUID Register Definitions */
334#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
335#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
336
337#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
338#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
339
340#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
341#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
342
343#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
344#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
345
346#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
347#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
348
349/* SCB Interrupt Control State Register Definitions */
350#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
351#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
352
353#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
354#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
355
356#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
357#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
358
359#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
360#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
361
362#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
363#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
364
365#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
366#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
367
368#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
369#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
370
371#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
372#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
373
374#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
375#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
376
377#if (__VTOR_PRESENT == 1)
378/* SCB Interrupt Control State Register Definitions */
379#define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */
380#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
381#endif
382
383/* SCB Application Interrupt and Reset Control Register Definitions */
384#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
385#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
386
387#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
388#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
389
390#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
391#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
392
393#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
394#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
395
396#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
397#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
398
399/* SCB System Control Register Definitions */
400#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
401#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
402
403#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
404#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
405
406#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
407#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
408
409/* SCB Configuration Control Register Definitions */
410#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
411#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
412
413#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
414#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
415
416/* SCB System Handler Control and State Register Definitions */
417#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
418#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
419
420/*@} end of group CMSIS_SCB */
421
422
423/** \ingroup CMSIS_core_register
424 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
425 \brief Type definitions for the System Timer Registers.
426 @{
427 */
428
429/** \brief Structure type to access the System Timer (SysTick).
430 */
431typedef struct
432{
433 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
434 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
435 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
436 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
437} SysTick_Type;
438
439/* SysTick Control / Status Register Definitions */
440#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
441#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
442
443#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
444#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
445
446#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
447#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
448
449#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
450#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
451
452/* SysTick Reload Register Definitions */
453#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
454#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
455
456/* SysTick Current Register Definitions */
457#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
458#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
459
460/* SysTick Calibration Register Definitions */
461#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
462#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
463
464#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
465#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
466
467#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
468#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
469
470/*@} end of group CMSIS_SysTick */
471
472#if (__MPU_PRESENT == 1)
473/** \ingroup CMSIS_core_register
474 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
475 \brief Type definitions for the Memory Protection Unit (MPU)
476 @{
477 */
478
479/** \brief Structure type to access the Memory Protection Unit (MPU).
480 */
481typedef struct
482{
483 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
484 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
485 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
486 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
487 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
488} MPU_Type;
489
490/* MPU Type Register */
491#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
492#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
493
494#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
495#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
496
497#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
498#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
499
500/* MPU Control Register */
501#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
502#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
503
504#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
505#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
506
507#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
508#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
509
510/* MPU Region Number Register */
511#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
512#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
513
514/* MPU Region Base Address Register */
515#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
516#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
517
518#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
519#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
520
521#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
522#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
523
524/* MPU Region Attribute and Size Register */
525#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
526#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
527
528#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
529#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
530
531#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
532#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
533
534#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
535#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
536
537#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
538#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
539
540#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
541#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
542
543#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
544#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
545
546#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
547#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
548
549#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
550#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
551
552#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
553#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
554
555/*@} end of group CMSIS_MPU */
556#endif
557
558
559/** \ingroup CMSIS_core_register
560 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
561 \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
562 are only accessible over DAP and not via processor. Therefore
563 they are not covered by the Cortex-M0 header file.
564 @{
565 */
566/*@} end of group CMSIS_CoreDebug */
567
568
569/** \ingroup CMSIS_core_register
570 \defgroup CMSIS_core_base Core Definitions
571 \brief Definitions for base addresses, unions, and structures.
572 @{
573 */
574
575/* Memory mapping of Cortex-M0+ Hardware */
576#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
577#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
578#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
579#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
580
581#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
582#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
583#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
584
585#if (__MPU_PRESENT == 1)
586 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
587 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
588#endif
589
590/*@} */
591
592
593
594/*******************************************************************************
595 * Hardware Abstraction Layer
596 Core Function Interface contains:
597 - Core NVIC Functions
598 - Core SysTick Functions
599 - Core Register Access Functions
600 ******************************************************************************/
601/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
602*/
603
604
605
606/* ########################## NVIC functions #################################### */
607/** \ingroup CMSIS_Core_FunctionInterface
608 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
609 \brief Functions that manage interrupts and exceptions via the NVIC.
610 @{
611 */
612
613/* Interrupt Priorities are WORD accessible only under ARMv6M */
614/* The following MACROS handle generation of the register offset and byte masks */
615#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
616#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
617#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
618
619
620/** \brief Enable External Interrupt
621
622 The function enables a device-specific interrupt in the NVIC interrupt controller.
623
624 \param [in] IRQn External interrupt number. Value cannot be negative.
625 */
626__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
627{
628 NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
629}
630
631
632/** \brief Disable External Interrupt
633
634 The function disables a device-specific interrupt in the NVIC interrupt controller.
635
636 \param [in] IRQn External interrupt number. Value cannot be negative.
637 */
638__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
639{
640 NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
641}
642
643
644/** \brief Get Pending Interrupt
645
646 The function reads the pending register in the NVIC and returns the pending bit
647 for the specified interrupt.
648
649 \param [in] IRQn Interrupt number.
650
651 \return 0 Interrupt status is not pending.
652 \return 1 Interrupt status is pending.
653 */
654__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
655{
656 return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
657}
658
659
660/** \brief Set Pending Interrupt
661
662 The function sets the pending bit of an external interrupt.
663
664 \param [in] IRQn Interrupt number. Value cannot be negative.
665 */
666__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
667{
668 NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
669}
670
671
672/** \brief Clear Pending Interrupt
673
674 The function clears the pending bit of an external interrupt.
675
676 \param [in] IRQn External interrupt number. Value cannot be negative.
677 */
678__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
679{
680 NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
681}
682
683
684/** \brief Set Interrupt Priority
685
686 The function sets the priority of an interrupt.
687
688 \note The priority cannot be set for every core interrupt.
689
690 \param [in] IRQn Interrupt number.
691 \param [in] priority Priority to set.
692 */
693__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
694{
695 if(IRQn < 0) {
696 SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
697 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
698 else {
699 NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
700 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
701}
702
703
704/** \brief Get Interrupt Priority
705
706 The function reads the priority of an interrupt. The interrupt
707 number can be positive to specify an external (device specific)
708 interrupt, or negative to specify an internal (core) interrupt.
709
710
711 \param [in] IRQn Interrupt number.
712 \return Interrupt Priority. Value is aligned automatically to the implemented
713 priority bits of the microcontroller.
714 */
715__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
716{
717
718 if(IRQn < 0) {
719 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
720 else {
721 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
722}
723
724
725/** \brief System Reset
726
727 The function initiates a system reset request to reset the MCU.
728 */
729__STATIC_INLINE void NVIC_SystemReset(void)
730{
731 __DSB(); /* Ensure all outstanding memory accesses included
732 buffered write are completed before reset */
733 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
734 SCB_AIRCR_SYSRESETREQ_Msk);
735 __DSB(); /* Ensure completion of memory access */
736 while(1); /* wait until reset */
737}
738
739/*@} end of CMSIS_Core_NVICFunctions */
740
741
742
743/* ################################## SysTick function ############################################ */
744/** \ingroup CMSIS_Core_FunctionInterface
745 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
746 \brief Functions that configure the System.
747 @{
748 */
749
750#if (__Vendor_SysTickConfig == 0)
751
752/** \brief System Tick Configuration
753
754 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
755 Counter is in free running mode to generate periodic interrupts.
756
757 \param [in] ticks Number of ticks between two interrupts.
758
759 \return 0 Function succeeded.
760 \return 1 Function failed.
761
762 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
763 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
764 must contain a vendor-specific implementation of this function.
765
766 */
767__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
768{
769 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
770
771 SysTick->LOAD = ticks - 1; /* set reload register */
772 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
773 SysTick->VAL = 0; /* Load the SysTick Counter Value */
774 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
775 SysTick_CTRL_TICKINT_Msk |
776 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
777 return (0); /* Function successful */
778}
779
780#endif
781
782/*@} end of CMSIS_Core_SysTickFunctions */
783
784
785
786
787#endif /* __CORE_CM0PLUS_H_DEPENDANT */
788
789#endif /* __CMSIS_GENERIC */
790
791#ifdef __cplusplus
792}
793#endif
Note: See TracBrowser for help on using the repository browser.