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1/**************************************************************************//**
2 * @file core_cm0.h
3 * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
4 * @version V3.20
5 * @date 25. February 2013
6 *
7 * @note
8 *
9 ******************************************************************************/
10/* Copyright (c) 2009 - 2013 ARM LIMITED
11
12 All rights reserved.
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 - Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 - Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 - Neither the name of ARM nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23 *
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ---------------------------------------------------------------------------*/
36
37
38#if defined ( __ICCARM__ )
39 #pragma system_include /* treat file as system include file for MISRA check */
40#endif
41
42#ifdef __cplusplus
43 extern "C" {
44#endif
45
46#ifndef __CORE_CM0_H_GENERIC
47#define __CORE_CM0_H_GENERIC
48
49/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
50 CMSIS violates the following MISRA-C:2004 rules:
51
52 \li Required Rule 8.5, object/function definition in header file.<br>
53 Function definitions in header files are used to allow 'inlining'.
54
55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
56 Unions are used for effective representation of core registers.
57
58 \li Advisory Rule 19.7, Function-like macro defined.<br>
59 Function-like macros are used to allow more efficient code.
60 */
61
62
63/*******************************************************************************
64 * CMSIS definitions
65 ******************************************************************************/
66/** \ingroup Cortex_M0
67 @{
68 */
69
70/* CMSIS CM0 definitions */
71#define __CM0_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
72#define __CM0_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
73#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \
74 __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
75
76#define __CORTEX_M (0x00) /*!< Cortex-M Core */
77
78
79#if defined ( __CC_ARM )
80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
82 #define __STATIC_INLINE static __inline
83
84#elif defined ( __ICCARM__ )
85 #define __ASM __asm /*!< asm keyword for IAR Compiler */
86 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
87 #define __STATIC_INLINE static inline
88
89#elif defined ( __GNUC__ )
90 #define __ASM __asm /*!< asm keyword for GNU Compiler */
91 #define __INLINE inline /*!< inline keyword for GNU Compiler */
92 #define __STATIC_INLINE static inline
93
94#elif defined ( __TASKING__ )
95 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
96 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
97 #define __STATIC_INLINE static inline
98
99#endif
100
101/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
102*/
103#define __FPU_USED 0
104
105#if defined ( __CC_ARM )
106 #if defined __TARGET_FPU_VFP
107 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
108 #endif
109
110#elif defined ( __ICCARM__ )
111 #if defined __ARMVFP__
112 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
113 #endif
114
115#elif defined ( __GNUC__ )
116 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
117 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
118 #endif
119
120#elif defined ( __TASKING__ )
121 #if defined __FPU_VFP__
122 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
123 #endif
124#endif
125
126#include <stdint.h> /* standard types definitions */
127#include <core_cmInstr.h> /* Core Instruction Access */
128#include <core_cmFunc.h> /* Core Function Access */
129
130#endif /* __CORE_CM0_H_GENERIC */
131
132#ifndef __CMSIS_GENERIC
133
134#ifndef __CORE_CM0_H_DEPENDANT
135#define __CORE_CM0_H_DEPENDANT
136
137/* check device defines and use defaults */
138#if defined __CHECK_DEVICE_DEFINES
139 #ifndef __CM0_REV
140 #define __CM0_REV 0x0000
141 #warning "__CM0_REV not defined in device header file; using default!"
142 #endif
143
144 #ifndef __NVIC_PRIO_BITS
145 #define __NVIC_PRIO_BITS 2
146 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
147 #endif
148
149 #ifndef __Vendor_SysTickConfig
150 #define __Vendor_SysTickConfig 0
151 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
152 #endif
153#endif
154
155/* IO definitions (access restrictions to peripheral registers) */
156/**
157 \defgroup CMSIS_glob_defs CMSIS Global Defines
158
159 <strong>IO Type Qualifiers</strong> are used
160 \li to specify the access to peripheral variables.
161 \li for automatic generation of peripheral register debug information.
162*/
163#ifdef __cplusplus
164 #define __I volatile /*!< Defines 'read only' permissions */
165#else
166 #define __I volatile const /*!< Defines 'read only' permissions */
167#endif
168#define __O volatile /*!< Defines 'write only' permissions */
169#define __IO volatile /*!< Defines 'read / write' permissions */
170
171/*@} end of group Cortex_M0 */
172
173
174
175/*******************************************************************************
176 * Register Abstraction
177 Core Register contain:
178 - Core Register
179 - Core NVIC Register
180 - Core SCB Register
181 - Core SysTick Register
182 ******************************************************************************/
183/** \defgroup CMSIS_core_register Defines and Type Definitions
184 \brief Type definitions and defines for Cortex-M processor based devices.
185*/
186
187/** \ingroup CMSIS_core_register
188 \defgroup CMSIS_CORE Status and Control Registers
189 \brief Core Register type definitions.
190 @{
191 */
192
193/** \brief Union type to access the Application Program Status Register (APSR).
194 */
195typedef union
196{
197 struct
198 {
199#if (__CORTEX_M != 0x04)
200 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
201#else
202 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
203 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
204 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
205#endif
206 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
207 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
208 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
209 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
210 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
211 } b; /*!< Structure used for bit access */
212 uint32_t w; /*!< Type used for word access */
213} APSR_Type;
214
215
216/** \brief Union type to access the Interrupt Program Status Register (IPSR).
217 */
218typedef union
219{
220 struct
221 {
222 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
223 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
224 } b; /*!< Structure used for bit access */
225 uint32_t w; /*!< Type used for word access */
226} IPSR_Type;
227
228
229/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
230 */
231typedef union
232{
233 struct
234 {
235 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
236#if (__CORTEX_M != 0x04)
237 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
238#else
239 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
240 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
241 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
242#endif
243 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
244 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
245 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
246 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
247 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
248 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
249 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
250 } b; /*!< Structure used for bit access */
251 uint32_t w; /*!< Type used for word access */
252} xPSR_Type;
253
254
255/** \brief Union type to access the Control Registers (CONTROL).
256 */
257typedef union
258{
259 struct
260 {
261 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
262 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
263 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
264 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
265 } b; /*!< Structure used for bit access */
266 uint32_t w; /*!< Type used for word access */
267} CONTROL_Type;
268
269/*@} end of group CMSIS_CORE */
270
271
272/** \ingroup CMSIS_core_register
273 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
274 \brief Type definitions for the NVIC Registers
275 @{
276 */
277
278/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
279 */
280typedef struct
281{
282 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
283 uint32_t RESERVED0[31];
284 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
285 uint32_t RSERVED1[31];
286 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
287 uint32_t RESERVED2[31];
288 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
289 uint32_t RESERVED3[31];
290 uint32_t RESERVED4[64];
291 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
292} NVIC_Type;
293
294/*@} end of group CMSIS_NVIC */
295
296
297/** \ingroup CMSIS_core_register
298 \defgroup CMSIS_SCB System Control Block (SCB)
299 \brief Type definitions for the System Control Block Registers
300 @{
301 */
302
303/** \brief Structure type to access the System Control Block (SCB).
304 */
305typedef struct
306{
307 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
308 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
309 uint32_t RESERVED0;
310 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
311 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
312 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
313 uint32_t RESERVED1;
314 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
315 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
316} SCB_Type;
317
318/* SCB CPUID Register Definitions */
319#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
320#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
321
322#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
323#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
324
325#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
326#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
327
328#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
329#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
330
331#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
332#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
333
334/* SCB Interrupt Control State Register Definitions */
335#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
336#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
337
338#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
339#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
340
341#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
342#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
343
344#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
345#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
346
347#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
348#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
349
350#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
351#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
352
353#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
354#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
355
356#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
357#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
358
359#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
360#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
361
362/* SCB Application Interrupt and Reset Control Register Definitions */
363#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
364#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
365
366#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
367#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
368
369#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
370#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
371
372#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
373#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
374
375#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
376#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
377
378/* SCB System Control Register Definitions */
379#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
380#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
381
382#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
383#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
384
385#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
386#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
387
388/* SCB Configuration Control Register Definitions */
389#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
390#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
391
392#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
393#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
394
395/* SCB System Handler Control and State Register Definitions */
396#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
397#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
398
399/*@} end of group CMSIS_SCB */
400
401
402/** \ingroup CMSIS_core_register
403 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
404 \brief Type definitions for the System Timer Registers.
405 @{
406 */
407
408/** \brief Structure type to access the System Timer (SysTick).
409 */
410typedef struct
411{
412 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
413 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
414 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
415 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
416} SysTick_Type;
417
418/* SysTick Control / Status Register Definitions */
419#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
420#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
421
422#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
423#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
424
425#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
426#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
427
428#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
429#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
430
431/* SysTick Reload Register Definitions */
432#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
433#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
434
435/* SysTick Current Register Definitions */
436#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
437#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
438
439/* SysTick Calibration Register Definitions */
440#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
441#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
442
443#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
444#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
445
446#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
447#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
448
449/*@} end of group CMSIS_SysTick */
450
451
452/** \ingroup CMSIS_core_register
453 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
454 \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
455 are only accessible over DAP and not via processor. Therefore
456 they are not covered by the Cortex-M0 header file.
457 @{
458 */
459/*@} end of group CMSIS_CoreDebug */
460
461
462/** \ingroup CMSIS_core_register
463 \defgroup CMSIS_core_base Core Definitions
464 \brief Definitions for base addresses, unions, and structures.
465 @{
466 */
467
468/* Memory mapping of Cortex-M0 Hardware */
469#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
470#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
471#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
472#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
473
474#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
475#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
476#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
477
478
479/*@} */
480
481
482
483/*******************************************************************************
484 * Hardware Abstraction Layer
485 Core Function Interface contains:
486 - Core NVIC Functions
487 - Core SysTick Functions
488 - Core Register Access Functions
489 ******************************************************************************/
490/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
491*/
492
493
494
495/* ########################## NVIC functions #################################### */
496/** \ingroup CMSIS_Core_FunctionInterface
497 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
498 \brief Functions that manage interrupts and exceptions via the NVIC.
499 @{
500 */
501
502/* Interrupt Priorities are WORD accessible only under ARMv6M */
503/* The following MACROS handle generation of the register offset and byte masks */
504#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
505#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
506#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
507
508
509/** \brief Enable External Interrupt
510
511 The function enables a device-specific interrupt in the NVIC interrupt controller.
512
513 \param [in] IRQn External interrupt number. Value cannot be negative.
514 */
515__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
516{
517 NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
518}
519
520
521/** \brief Disable External Interrupt
522
523 The function disables a device-specific interrupt in the NVIC interrupt controller.
524
525 \param [in] IRQn External interrupt number. Value cannot be negative.
526 */
527__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
528{
529 NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
530}
531
532
533/** \brief Get Pending Interrupt
534
535 The function reads the pending register in the NVIC and returns the pending bit
536 for the specified interrupt.
537
538 \param [in] IRQn Interrupt number.
539
540 \return 0 Interrupt status is not pending.
541 \return 1 Interrupt status is pending.
542 */
543__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
544{
545 return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
546}
547
548
549/** \brief Set Pending Interrupt
550
551 The function sets the pending bit of an external interrupt.
552
553 \param [in] IRQn Interrupt number. Value cannot be negative.
554 */
555__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
556{
557 NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
558}
559
560
561/** \brief Clear Pending Interrupt
562
563 The function clears the pending bit of an external interrupt.
564
565 \param [in] IRQn External interrupt number. Value cannot be negative.
566 */
567__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
568{
569 NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
570}
571
572
573/** \brief Set Interrupt Priority
574
575 The function sets the priority of an interrupt.
576
577 \note The priority cannot be set for every core interrupt.
578
579 \param [in] IRQn Interrupt number.
580 \param [in] priority Priority to set.
581 */
582__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
583{
584 if(IRQn < 0) {
585 SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
586 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
587 else {
588 NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
589 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
590}
591
592
593/** \brief Get Interrupt Priority
594
595 The function reads the priority of an interrupt. The interrupt
596 number can be positive to specify an external (device specific)
597 interrupt, or negative to specify an internal (core) interrupt.
598
599
600 \param [in] IRQn Interrupt number.
601 \return Interrupt Priority. Value is aligned automatically to the implemented
602 priority bits of the microcontroller.
603 */
604__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
605{
606
607 if(IRQn < 0) {
608 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
609 else {
610 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
611}
612
613
614/** \brief System Reset
615
616 The function initiates a system reset request to reset the MCU.
617 */
618__STATIC_INLINE void NVIC_SystemReset(void)
619{
620 __DSB(); /* Ensure all outstanding memory accesses included
621 buffered write are completed before reset */
622 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
623 SCB_AIRCR_SYSRESETREQ_Msk);
624 __DSB(); /* Ensure completion of memory access */
625 while(1); /* wait until reset */
626}
627
628/*@} end of CMSIS_Core_NVICFunctions */
629
630
631
632/* ################################## SysTick function ############################################ */
633/** \ingroup CMSIS_Core_FunctionInterface
634 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
635 \brief Functions that configure the System.
636 @{
637 */
638
639#if (__Vendor_SysTickConfig == 0)
640
641/** \brief System Tick Configuration
642
643 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
644 Counter is in free running mode to generate periodic interrupts.
645
646 \param [in] ticks Number of ticks between two interrupts.
647
648 \return 0 Function succeeded.
649 \return 1 Function failed.
650
651 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
652 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
653 must contain a vendor-specific implementation of this function.
654
655 */
656__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
657{
658 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
659
660 SysTick->LOAD = ticks - 1; /* set reload register */
661 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
662 SysTick->VAL = 0; /* Load the SysTick Counter Value */
663 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
664 SysTick_CTRL_TICKINT_Msk |
665 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
666 return (0); /* Function successful */
667}
668
669#endif
670
671/*@} end of CMSIS_Core_SysTickFunctions */
672
673
674
675
676#endif /* __CORE_CM0_H_DEPENDANT */
677
678#endif /* __CMSIS_GENERIC */
679
680#ifdef __cplusplus
681}
682#endif
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