1 | /**************************************************************************//**
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2 | * @file pl310.c
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3 | * @brief Implementation of PL310 PrimeCell Level 2 Cache Controller functions
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4 | * @version
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5 | * @date 3 December 2014
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6 | *
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7 | * @note
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8 | *
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9 | ******************************************************************************/
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10 | /* Copyright (c) 2011 - 2013 ARM LIMITED
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11 |
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12 | All rights reserved.
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13 | Redistribution and use in source and binary forms, with or without
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14 | modification, are permitted provided that the following conditions are met:
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15 | - Redistributions of source code must retain the above copyright
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16 | notice, this list of conditions and the following disclaimer.
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17 | - Redistributions in binary form must reproduce the above copyright
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18 | notice, this list of conditions and the following disclaimer in the
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19 | documentation and/or other materials provided with the distribution.
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20 | - Neither the name of ARM nor the names of its contributors may be used
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21 | to endorse or promote products derived from this software without
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22 | specific prior written permission.
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23 | *
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24 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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25 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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26 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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27 | ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
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28 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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29 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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30 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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31 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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32 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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33 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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34 | POSSIBILITY OF SUCH DAMAGE.
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35 | ---------------------------------------------------------------------------*/
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36 | #include "MBRZA1H.h"
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37 |
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38 | //Cache Sync operation
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39 | void PL310_Sync(void)
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40 | {
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41 | PL310->CACHE_SYNC = 0x0;
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42 | }
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43 |
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44 | //return Cache controller cache ID
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45 | int PL310_GetID (void)
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46 | {
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47 | return PL310->CACHE_ID;
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48 | }
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49 |
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50 | //return Cache controller cache Type
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51 | int PL310_GetType (void)
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52 | {
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53 | return PL310->CACHE_TYPE;
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54 | }
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55 |
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56 | //Invalidate all cache by way
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57 | void PL310_InvAllByWay (void)
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58 | {
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59 | unsigned int assoc;
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60 |
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61 | if (PL310->AUX_CNT & (1<<16))
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62 | assoc = 16;
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63 | else
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64 | assoc = 8;
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65 |
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66 | PL310->INV_WAY = (1 << assoc) - 1;
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67 | while(PL310->INV_WAY & ((1 << assoc) - 1)); //poll invalidate
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68 |
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69 | PL310_Sync();
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70 | }
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71 |
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72 | //Clean and Invalidate all cache by way
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73 | void PL310_CleanInvAllByWay (void)
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74 | {
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75 | unsigned int assoc;
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76 |
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77 | if (PL310->AUX_CNT & (1<<16))
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78 | assoc = 16;
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79 | else
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80 | assoc = 8;
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81 |
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82 | PL310->CLEAN_INV_WAY = (1 << assoc) - 1;
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83 | while(PL310->CLEAN_INV_WAY & ((1 << assoc) - 1)); //poll invalidate
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84 |
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85 | PL310_Sync();
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86 | }
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87 |
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88 | //Enable Cache
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89 | void PL310_Enable(void)
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90 | {
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91 | PL310->CONTROL = 0;
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92 | PL310->INTERRUPT_CLEAR = 0x000001FFuL;
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93 | PL310->DEBUG_CONTROL = 0;
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94 | PL310->DATA_LOCK_0_WAY = 0;
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95 | PL310->CACHE_SYNC = 0;
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96 |
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97 | PL310->CONTROL = 0x01;
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98 | PL310_Sync();
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99 | }
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100 | //Disable Cache
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101 | void PL310_Disable(void)
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102 | {
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103 | PL310->CONTROL = 0x00;
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104 | PL310_Sync();
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105 | }
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106 |
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107 | //Invalidate cache by physical address
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108 | void PL310_InvPa (void *pa)
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109 | {
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110 | PL310->INV_LINE_PA = (unsigned int)pa;
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111 | PL310_Sync();
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112 | }
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113 |
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114 | //Clean cache by physical address
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115 | void PL310_CleanPa (void *pa)
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116 | {
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117 | PL310->CLEAN_LINE_PA = (unsigned int)pa;
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118 | PL310_Sync();
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119 | }
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120 |
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121 | //Clean and invalidate cache by physical address
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122 | void PL310_CleanInvPa (void *pa)
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123 | {
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124 | PL310->CLEAN_INV_LINE_PA = (unsigned int)pa;
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125 | PL310_Sync();
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126 | }
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127 |
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128 |
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